Patent Application
20170132003
The present invention relates generally to managing the allocation of resources in a computer, and in particular embodiments, to techniques and mechanisms for hardware multithreading to improve very long instruction word (VLIW) digital signal processor (DSP) performance and efficiency.
In DSP design, better performance may be achieved by creating a smaller number of higher-performing DSP cores, as opposed to a greater number of lower-performing DSP cores. A fewer quantity of cores may reduce the interconnection cost when fabricating the DSP. For example, a DSP with fewer cores may achieve reduced silicon area and/or power consumption. Further, a reduction in the interconnect complexity may simplify inter-core communication and reduce synchronization overhead, thereby increasing the power efficiency of a DSP.
DSP performance may also be increased by the use of VLIW instructions, whereby multiple instructions may be issued to a DSP in a single VLIW instruction bundle. Instructions in a VLIW bundle may be executed in parallel. However, this increase in efficiency may be limited by the amount of parallelism in algorithms or software. For example, certain types of wireless baseband signal processing may not “scale out” efficiently at the instruction level. Additionally, some types of single instruction, multiple data (SIMD) operations may not scale out efficiently. Techniques to increase the performance of algorithms that do not scale out well at the instruction level are thus needed.
Technical advantages are generally achieved, by embodiments of this disclosure which describe hardware multithreading to improve VLIW DSP performance and efficiency.
In accordance with an embodiment, a processor includes an instruction fetch and dispatch unit, a plurality of program control units coupled to the instruction fetch and dispatch unit, a plurality of function units coupled to the plurality of program control units, and a mode control unit coupled to the function units and the program control units, the mode control unit configured to dynamically organize the plurality of function units and the plurality of program control units into one or more threads, each thread comprising a program control of the plurality of program control units and a subset of the plurality of function units.
In accordance with another embodiment, a method for organizing a processor includes selecting, by a mode control unit, a quantity of threads into which to divide a processor, dividing, by the mode control unit, function units into function unit groups, the quantity of function unit groups being equal to the quantity of threads, and allocating, by the mode control unit, a register file into a plurality of thread register files, each of the thread register files being allocated to one of the function unit groups.
In accordance with yet another embodiment, a device includes a processor comprising function units and a register file, and a computer-readable storage medium storing a program to be executed by the processor, the program including instructions for selecting a quantity of threads into which to divide the processor, dividing the function units into function unit groups, the quantity of function unit groups being equal to the quantity of threads, and allocating the register file into a plurality of thread register files, each of the thread register files being allocated to one of the function unit groups.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which:
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.
The making and using of embodiments of this disclosure are discussed in detail below. It should be appreciated, however, that the concepts disclosed herein can be embodied in a wide variety of specific contexts, and that the specific embodiments discussed herein are merely illustrative and do not serve to limit the scope of the claims. Further, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims.
Disclosed herein is a multithreading technique to improve VLIW DSP performance and efficiency. In an M-way VLIW processor, up to M instructions may be executed in each clock cycle. In other words, each VLIW instruction word may include M instructions. Embodiment VLIW DSPs may adapt to run in single thread mode for applications that have sufficient instruction-level parallelism. For applications that do not contain sufficient instruction-level parallelism, embodiment VLIW DSPs may run in a multithreading mode, which may include dividing an M-way VLIW processor into N smaller processors (or “threads”). Accordingly, each smaller processor may be capable of executing (M÷N) instructions in each clock cycle. For example, an embodiment DSP that supports an 8-instruction VLIW may configure itself into two threads that each support a 4-instruction VLIW. Likewise, a register file in an embodiment VLIW DSP may be divided into N smaller register files, each of which is used by one of the N smaller processors. Applications that do not scale well through instruction-level parallelism may perform better if there are more threads available for the application, even if those threads are less capable than a single large processor. Such applications may be designed with thread-level parallelism (sometimes called “coarse-grained parallelism”), so that they take advantage of the more numerous but less capable threads.
Embodiment VLIW DSPs contain many function units that respond to different instructions, and may adapt to different multithreading configurations through a mode control unit that maps and groups the function units. For example, embodiment VLIW DSPs may be configured as a single large processor with a high degree of parallelism by grouping all function units into a single thread. Alternatively, embodiment VLIW DSPs may be configured to include multiple smaller threads by grouping the function units into several smaller groups. Function units may be exclusively assigned to, or shared between different threads.
Various embodiments may achieve advantages. Because the efficiency of VLIW processors and SIMD parallel processing has been reached, embodiments may offer other ways to increase the performance of DSPs. By implementing multithreaded parallel processing in DSP cores, the execution efficiency of software on DSP cores may be increased. Depending on the application being executed, embodiments may increase the performance of DSP cores by up to 33% with a corresponding increase in silicon area of only about 10%. Increases in the efficient of silicon area may result in cost reductions and increased power efficiency.
The DSP 110 may be a standalone device in the processing system 100, or may be co-located with another component of the processing system 100. In some embodiments, the processor 102 may be part of the DSP 110, i.e., the DSP 110 has processing capabilities as well as digital signal processing capabilities.
In some embodiments, the processing system 100 is included in a network device that is accessing, or part otherwise of, a telecommunications network. In one example, the processing system 100 is in a network-side device in a wireless or wireline telecommunications network, such as a base station, a relay station, a scheduler, a controller, a gateway, a router, an applications server, or any other device in the telecommunications network. In other embodiments, the processing system 100 is in a user-side device accessing a wireless or wireline telecommunications network, such as a mobile station, a user equipment (UE), a personal computer (PC), a tablet, a wearable communications device (e.g., a smartwatch, etc.), or any other device adapted to access a telecommunications network.
The DSP core 210 is configured to contain duplicates of some function units. For example, the DSP core 210 includes two of each scalar arithmetic, load, and store units. It also includes two of each vector multiply and auxiliary units. By configuring the DSP core 210 with more function units, it is thus able to execute more instructions in a VLIW, and therefore has a higher degree of instruction-level parallelism. For example, if the single-threaded VLIW DSP 200 can respond to an 8-instruction VLIW, then the DSP core 210 may handle all eight instructions.
The PCU 211 may act as the central control function unit for a thread. The PCU 211 may be configured so a thread operates in wide mode, where it has many function units, or in narrow mode, where it has fewer function units. A single, wide thread may be beneficial for applications that include sufficient instruction-level parallelism. Conversely, multiple, narrow threads may be beneficial for application that lack instruction-level parallelism but have been designed to include sufficient thread-level parallelism. In some embodiments, the PCUs may be switched between wide and narrow mode semi-statically or dynamically. For example, some applications may have some portions that are designed to take advantage of instruction-level parallelism and other portions that are designed to take advantage of thread-level parallelism. The portions designed for instruction-level parallelism may be performed when the VLIW DSP is configured to include a single, wide thread, e.g., the single-threaded VLIW DSP 200, and the portions designed for thread-level parallelism may be performed after the VLIW DSP is reconfigured to include multiple, narrow threads, as will be discussed in greater detail below. If a workload can be balanced across multiple threads, overall processing efficiency may be increased since the function units will be better utilized.
The PCU 211 reads instructions from the instruction cache 230 and executes them on the DSP core 210. The instruction cache 230 may cache instructions from the L2 memory 250. As will be discussed below, there may be multiple PCUs executing instructions from the instruction cache 230. The data cache 240 may buffer reads and writes to/from the L2 memory 250 performed by the function units.
Each of the threads 310, 320 includes PCUs 311, 321, scalar arithmetic units 312, 322, scalar load units 313, 323, scalar store units 314, 324, vector multiply units 315, 325, vector auxiliary units 316, 326, scalar register files 317, 327, and vector register files 318, 328. Like the single-threaded VLIW DSP 200 in
The PCUs 311, 321 may each comprise an interrupt controller so that each of the threads 310, 320 are capable of responding to different interrupt requests without disrupting one another. Assignment of the interrupt requests to the PCUs 311, 321 may be controlled by an application executed on the symmetrically partitioned multithreaded VLIW DSP 300.
The instruction cache 330 may be shared by the threads 310, 320. In some embodiments, both of the threads 310, 320 may alternate use of the same read port of the instruction cache 330. In some embodiments, each of the threads 310, 320 may be connected to a dedicated port of the instruction cache 330. In embodiments where the instruction cache 330 is a multiple-banked cache, the instruction cache 330 may be designed to support multiple read ports. The data cache 340, like the instruction cache 330, may also have one or a plurality of ports shared by multiple threads.
In some embodiments, the threads 310, 320 may share the same program code. In such embodiments, each of the threads 310, 320 may have its own copies of global and static variables. Allowing each of the threads 310, 320 to have their own copies of the data may be accomplished through address translation. For example, the values of duplicate global and static variables may be fixed in the data cache 340 and/or the L2 memory 350 and then the different addresses for each thread's copy may be mapped to that thread through memory mapping.
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The threads 410, 430 include PCUs 411, 431, scalar arithmetic units 412, 432, scalar load units 413, 433, scalar store units 414, 434, and scalar register files 419, 435. However, unlike the symmetrically partitioned multithreaded VLIW DSP 300 illustrated in
The asymmetrically partitioned multithreaded VLIW DSP 400 may be asymmetrically split to accommodate the needs of various threads in an application that supports thread-level parallelism. For example, when executing an application where one thread demands a higher degree of instruction-level parallelism than another thread, a VLIW DSP may be split asymmetrically, like the asymmetrically partitioned multithreaded VLIW DSP 400 of
Unlike some embodiment symmetric or asymmetric multithreaded VLIW DSPs, the threads 510, 520 share the shared units 530. The shared units 530 include vector multiply units 531, 532 and vector auxiliary units 533, 534. These function units may be accessed by one of the threads 510, 520 in a given clock cycle. For example, the threads 510, 520 may equally share access to the shared units 530. As another example, the thread 510 may access the shared units 530 for more or less clock cycles than the thread 520. It should be appreciated that any division of access to the shared units 530 is possible, and the division may depend on the needs of applications running on the multithreaded VLIW DSP with shared function units 500.
The instruction fetch and dispatch unit 710 is coupled to the mode control unit 720 and the other function units in the symmetric thread partition 700. The instruction fetch and dispatch unit 710 separates the instructions packed in a VLIW and dispatches them to the different threads. It may have one shared read port, or different read ports for different threads.
The mode control unit 720 organizes function units into threads and allocates function units and registers to different threads. The mode control unit 720 has control lines that are connected to the multiplexers in the different function units, as illustrated above with respect to the control lines 608 of
The function units illustrated in the symmetric thread partition 700 are organized into two threads: a first thread (indicated by the dotted hash pattern), and a second thread (indicated by the diagonal hash pattern). However, the PCU 730 is connected to all function units in the symmetric thread partition 700, including function units in threads that the PCU 730 does not participate in. That is, the PCU 730 is physically connected to function units in the second thread even though the PCU 730 is participating in the first thread. Likewise, the PCU 740 is also physically connected to all other function units in the symmetric thread partition 700, including those in threads the PCU 740 does not participate in. This function unit interconnection is possible due to the multiplexer in each function unit, discussed above with respect to
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Although the description has been described in detail, it should be understood that various changes, substitutions and alterations can be made without departing from the spirit and scope of this disclosure as defined by the appended claims. Moreover, the scope of the disclosure is not intended to be limited to the particular embodiments described herein, as one of ordinary skill in the art will readily appreciate from this disclosure that processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, may perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
