Claims
- 1. A power regulation system coupled to an input source voltage (Vin) and an output voltage (Vout), said Vout electrically coupled to a load, the system comprising:
a plurality of power conversion blocks in a multi-phase configuration, each block electrically coupled to said Vin at a power IC and coupled to said Vout at an output inductance, said power IC including a command interface having read/write capabilities for storing data; a controller in communication with and providing an instruction to each of said power conversion blocks, said controller having an adaptive algorithm configured to receive digital power conversion data from said blocks and to determine a power compensation from said data, said power compensation modifying said instruction to each of said power conversion blocks; and a digital bus providing a communication channel between said plurality of power conversion blocks and said controller.
- 2. The power regulation system of claim 1, wherein said controller comprises one of a digital signal processor (DSP) or a microprocessor.
- 3. The power regulation system of claim 1, further comprising a current feedback line between each of said power conversion blocks and said controller to facilitate current balancing.
- 4. The power regulation system of claim 1, wherein said command interface of said power IC further comprises a fault register.
- 5. The power regulation system of claim 4, wherein said controller periodically polls said fault register via said digital bus to determine if a fault within said power IC has occurred.
- 6. The power regulation system of claim 1, wherein each of said power ICs comprises an identification (ID) as assigned by said controller.
- 7. The power regulation system of claim 1, wherein said power compensation comprises an adaptive slope control algorithm for peak current mode control.
- 8. The power regulation system of claim 1, wherein said power compensation comprises a proportional-integral-derivative (PID) control algorithm.
- 9. The power regulation system of claim 8, wherein said PID control algorithm comprises a proportional gain (Kp), an integral gain (Ki), and a differential gain (Kd).
- 10. The power regulation system of claim 9, wherein said PID control algorithm further comprises an error signal.
- 11. The power regulation system of claim 10, wherein said error signal comprises a summation of said digital power conversion data from said power conversion blocks.
- 12. The power regulation system of claim 10, wherein said error signal comprises a summation of a voltage error and a load current.
- 13. The power regulation system of claim 10, wherein said instruction is offset by said (Kd).
- 14. The power regulation system of claim 13, wherein said instruction is offset during a load step.
- 15. A method of compensation control in a multi-phased power regulation system, said method comprising the steps of:
receiving, at a controller, a plurality of digital information from each of a plurality of power conversion blocks in a multi-phase configuration, said information comprising a net error; optimizing a set of coefficients of a compensation transfer function in response to said received digital information by modifying said set of coefficients to compensate for system changes; and transmitting control information from said controller to each of said power conversion blocks in response to said optimizing step.
- 16. The method of claim 15, wherein said optimizing step comprises optimizing a proportional gain (Kp), an integral gain (Ki), and a differential gain (Kd).
- 17. The method of claim 16, wherein said optimizing step further comprises forming a PI block comprising said (Kp) and said (Ki), and forming a D block comprising said (Kd).
- 18. The method of claim 17, wherein said optimizing step further comprises offsetting said PI block by said D block during a load step.
- 19. The method of claim 15, wherein said controller comprises a digital signal processor (DSP) and said receiving step occurs at said DSP.
- 20. The method of claim 15, further comprising the step of forming a synchronized current share line between said controller and each of said power conversion blocks.
- 21. The method of claim 15, further comprising the step of addressing each of said power conversion blocks.
- 22. The method of claim 21, further comprising the step of determining a number of available power conversion blocks in response to said addressing step.
- 23. The method of claim 21, further comprising the step of determining a relative phase relationship between a plurality of channels in response to said addressing step.
- 24. The method of claim 16, wherein said optimizing step further comprises increasing said (Kd) and decreasing said (Ki) to increase a transient response of said system.
- 25. The method of claim 16, wherein said optimizing step further comprises decreasing said (Kd) and increasing said (Ki) to increase a steady-state response of said system.
- 26. A method of proportional-integral-derivative (PID) compensation control in a highly phased power conversion system, said system having a voltage input and a voltage output, said voltage output received at a load, method comprising the steps of:
comparing a voltage output from a power conversion block to a predetermined voltage to determine a voltage error; converting said voltage error to a digital representation of said voltage error; converting a current received at said load to a digital representation; determining a net error from said voltage digital representation and said current digital representation; receiving said net error at a Pi block of said compensation control; receiving said current digital representation at a D block of said compensation control; offsetting said Pi block with said D block during a load change; determining a set of PID coefficients in accordance with static and transient conditions of said system; outputting a compensated instruction in response to said Pi and said D blocks; and modifying said voltage output in response to said compensated instruction.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. patent application Ser. No. 09/978,294, filed on Oct. 15, 2001, the disclosure of which is hereby incorporated by reference.
[0002] This application includes subject matter that is related to and claims priority from U.S. Provisional Patent Application Ser. No. 60/240,337, filed on Oct. 13, 2000, entitled, “Adaptive Slope Compensation with DSP Control.”
[0003] This application also includes subject matter that is related to and is a continuation-in-part of U.S. patent application Ser. No. 09/975,195, filed Oct. 10, 2001, entitled, “System and Method for Highly Phased Power Regulation” which claims priority from the following U.S. Provisional Patent Applications filed on Oct. 10, 2000: patent application Ser. No. 60/238,993 entitled, “Multi Output Switching Power Converter with Optical I/O Microprocessor Control;” patent application Ser. No. 60/239,049 entitled, “Multi Output Synchronous Power Conversion with DSP Control;” and patent application Ser. No. 60/239,166 entitled, “Highly Phased Switching Regulator with DSP Control.”
Provisional Applications (4)
|
Number |
Date |
Country |
|
60240337 |
Oct 2000 |
US |
|
60238993 |
Oct 2000 |
US |
|
60239049 |
Oct 2000 |
US |
|
60239166 |
Oct 2000 |
US |
Continuations (1)
|
Number |
Date |
Country |
Parent |
09978294 |
Oct 2001 |
US |
Child |
10109801 |
Mar 2002 |
US |
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09975195 |
Oct 2001 |
US |
Child |
10109801 |
Mar 2002 |
US |