1. Field of the Invention
The present invention is directed to liquid crystal display panels. More particularly, methods and systems relating to differential signaling and timing controls for a liquid crystal display panel are provided.
2. Discussion of the Related Art
Liquid crystal display (LCD) panels are used in a wide range of electronic products, including computers, monitors, flat panel displays, and televisions, among others. LCD displays are matrices of liquid-filled cells that form pixels. LCD panels offer the high resolution, refresh rates, and response times necessary for high-definition viewing of software, graphics, videos, and other media.
LCD panels are typically controlled by display system controllers that are responsible for receiving image data from a graphics card, a video controller, a DVD player, etc., and sending it to an external panel timing controller. Some display system controllers may include additional functionality, such as the SupraHD® 780 processor from Zoran Corporation of Sunnyvale Calif., which integrates a display system control processor with an MPEG-2 decoder, an 8VSB demodulator, NTSC video decoder, HDMI interface, low-voltage differential signaling (LVDS) drivers, memory, and other peripherals to provide a single-chip HDTV controller capable of driving various LCD panels. In such systems, the external panel timing controller may transmit the image data to the LCD panel for display. The external panel timing controller may also generate and send complex timing and control signals to ensure that the image data is displayed at the correct time.
Many LCD panels use some form of differential signaling for interaction between the display system controller, external panel timing controller, and the LCD panel itself. Differential signaling is a form of serial communication performed by sending low-voltage electrical pulses over a pair of electrically-coupled wires. An example of a typical differential signal transmission interface 10 is shown in
Differential signaling offers many benefits in the context of LCD panels. First, the balanced differential lines represented by wires 14, 16 have equal but opposite currents, called odd-mode signals. These odd-mode signals tend to cancel each other out, resulting in low electromagnetic interference. Furthermore, the relatively low voltage reduces the signal swing, allowing for communication speeds of over 5 Gigabits per second (Gbps). Using low voltage signals is possible with differential signaling because any electromagnetic “noise” in the form of inductive radiation from nearby components or electrical fields will affect both lines equally, thereby not affecting the voltage difference between the lines. By contrast, single line transmissions must generate a voltage high enough to overcome this background noise. The low power consumption required for differential signaling allows for the integration of many differential signaling channels on a microchip without generating excessive heat or noise.
Several standards implementing differential signaling are known in the art. Such standards include Low-Voltage Differential Signaling (LVDS), mini-LVDS, Reduced-Swing Differential Signaling (RSDS), and Bussed Low-Voltage Differential Signaling (BLVDS). Standard values for the differential output voltage swing, offset voltage, and output currents for LVDS, RSDS, and mini-LVDS are shown in
The components in LCD panels may utilize several of these standards. For example, the display system controller may transmit image data and timing signals to the external panel timing controller using an LVDS interface. The external panel timing controller may then send the image data to the panel according to the RSDS or mini-LVDS standards.
The present invention eliminates the need for an external, dedicated panel timing controller (TCON) in LCD panels. In the past, a customized external panel timing controller typically was designed and developed for each LCD display panel. When a new LCD display panel was developed, the signal and timing requirements would be carefully measured, and a custom external panel timing controller chip would be developed for the LCD display panel. As the timings were fine-tuned during the development process, numerous iterations of the external panel timing controller had to be designed and tested before the optimal settings were determined. Since every LCD display panel's particular dimensions and timing needs were different, substantial research and development was required to develop a dedicated external panel timing controller for each new LCD display panel that was developed.
Embodiments of the present invention eliminate the need for a dedicated external panel timing controller by providing a programmable generic panel timing controller that can be configured, through the use of parameters and logic gates, to generate correct timing signals for a variety of LCD panels. In this way, design and development costs can be reduced.
Embodiments of the present invention thus simplify the design of display systems by eliminating the need for external panel timing controllers. In accordance with one embodiment, an integrated circuit (a “system on a chip”) is provided that incorporates a data framer, a data transmitter, and a programmable timing controller. The data framer may be configured to format the data according to one of the LVDS, RSDS, or mini-LVDS transmission standards. The data is then passed to the data transmitter, which sends the data to components on the LCD panel responsible for displaying pixels at the appropriate time. Embodiments of the present invention further simplify the design of display systems by providing a display system controller with common output interface whereby data can be transmitted according to one of the LVDS, RSDS, or mini-LVDS standards. This eliminates the need for an external timing controller, in that the display system controller can generate pixel data in the RSDS or mini-LVDS standards, as well as the necessary timing signals, and transmit them to the column and gate drivers that control the display of pixels on the panel. However, where an external timing controller is desired or necessary, for example, to provide backwards compatibility or to drive a larger high-definition panel, the display system controller can transmit data to the external timing controller according to the LVDS standard.
According to one aspect of the present invention, a television display system is provided. The television display system comprises a display system controller, a transmitter, and an integrated timing controller. The display system controller is configured to receive pixel data and pixel timing and control signals, and responsive to a pixel data format corresponding to a selected communication standard of a plurality of differential signaling communication standards that includes LVDS and at least one of RSDS and mini-LVDS, to provide formatted pixel data that is formatted according to the pixel data format of said selected communication standard. The transmitter is configured to receive the formatted pixel data, and to transmit the formatted pixel data for receipt according to a pixel data rate corresponding to said selected communication standard. The integrated timing controller is configured to receive the pixel timing and control data, and responsive to said selected communication standard being one of RSDS and mini-LVDS, to generate pixel display timing and control signals to display the formatted pixel data at the pixel data rate corresponding to said selected communication standard on a television display.
In accordance with one embodiment, the display system controller, the transmitter, and the integrated timing controller are implemented on a single integrated circuit. In a further embodiment, the plurality of differential signaling communication standards includes LVDS, RSDS, and mini-LVDS.
In accordance with an aspect of this embodiment, the transmitter includes a plurality of drivers. The plurality of drivers includes a first plurality of channel drivers that are configured to transmit the formatted pixel data for receipt according to the pixel data rate of LVDS responsive to LVDS being said selected communication standard and to transmit instead the formatted pixel data for receipt according to the pixel data rate of RSDS and mini-LVDS responsive to one of RSDS and mini-LVDS being said selected communication standard.
In accordance with a further aspect of this embodiment, the plurality of drivers includes at least one clock driver. The at least one clock driver is configured to transmit a clock signal having a clock rate that is either one seventh or one eighth the pixel data rate of LVDS responsive to any one of LVDS, RSDS and mini-LVDS being said selected communication standard.
In accordance with another aspect of this embodiment, the television display system further comprises a data framer. The data framer is configured to receive the pixel data and the pixel timing and control signals, and to format the pixel data along with the pixel timing and control signals according to the pixel data format of LVDS responsive to LVDS being said selected communication standard, and to receive the pixel data and the pixel timing and control signals and to format only the pixel data according to the pixel data format of RSDS and mini-LVDS responsive to the selected one of RSDS and mini-LVDS being said selected communication standard.
In accordance with a further aspect of the present invention, the data framer is further configured to repeat each bit of the pixel data during formatting of the pixel data according to the pixel data format of RSDS and mini-LVDS responsive to the selected one of RSDS and mini-LVDS being said selected communication standard.
In accordance with an embodiment of the present invention, the integrated timing controller includes a counter circuit and a plurality of programmable timing control circuits. The counter receives the pixel timing and control signals and provides a line count signal and a pixel count signal, the line count signal identifying a line of the television display at which the formatted pixel data is to be displayed and the pixel count signal identifying pixel position of the television display at which the formatted pixel data is to be displayed. Each of the plurality of programmable timing control circuits is coupled to the counter circuit to receive the line count signal and the pixel count signal. The plurality of programmable timing control circuits includes a first plurality of programmable timing control circuits for respectively providing a respective one of a plurality of source driver timing and control signals to the television display based upon the line count signal and the pixel count signal, and a second plurality of programmable timing control circuits for respectively providing a respective one of a plurality of gate driver timing and control signals to the television display based upon the line count signal and the pixel count signal. In accordance with a further aspect of this embodiment, at least one of an assertion level, an assertion time, and an assertion width of each respective one of the plurality of source driver timing and control signals and each respective one of the plurality of gate driver timing and control signals is programmable.
In accordance with another aspect of the present invention, a method of displaying an image is provided. The method comprises acts of receiving pixel data and pixel timing and control signals corresponding to the image; formatting, responsive to selection of a communication standard from a plurality of differential signaling communication standards that includes LVDS and a least one of RSDS and mini-LVDS, the pixel data according to a pixel data format of said selected communication standard; transmitting the formatted pixel data for receipt according to a pixel data rate corresponding said selected communication standard; and generating, responsive to said selected communication standard being one of RSDS and mini-LVDS, pixel display timing and control signals to display the formatted pixel data at the pixel data rate corresponding to said selected communication standard on a television display.
In accordance with one embodiment of the present invention, the act of formatting includes an act of formatting, responsive to selection of the communication standard from a plurality of differential signaling communication standards that includes LVDS, RSDS, and mini-LVDS, the pixel data according to a pixel data format of said selected communication standard.
In accordance with another embodiment, the act of transmitting includes acts of transmitting the formatted pixel data for receipt according to the pixel data rate of LVDS in response to LVDS being said selected communication standard, and transmitting the formatted pixel data for receipt according to the pixel data rate of RSDS and mini-LVDS in response to one of RSDS and mini-LVDS being said selected communication standard.
In accordance with further embodiment, the act of transmitting the formatted pixel data for receipt according to the pixel data rate of LVDS in response to LVDS being said selected communication standard includes transmitting a first portion of the formatted pixel data for receipt according to the pixel data rate of LVDS using a first channel driver, and the act of transmitting the formatted pixel data for receipt according to the pixel data rate of RSDS and mini-LVDS in response to one of RSDS and mini-LVDS being said selected communication standard includes transmitting a second portion of the formatted pixel data for receipt according to the pixel data rate of RSDS and mini-LVDS using the first channel driver.
In accordance with another aspect of the present invention, the method further comprises an act of transmitting a clock signal having a clock rate that is either one seventh or one eighth the pixel data rate of LVDS in response to any one of LVDS, RSDS and mini-LVDS being said selected communication standard.
In accordance with one embodiment, the act of formatting the pixel data according to a pixel data format of said selected communication standard includes acts of formatting the pixel data along with the pixel timing and control signals according to the pixel data format of LVDS in response to LVDS being said selected communication standard, and formatting only the pixel data according to the pixel data format of RSDS and mini-LVDS in response to the selected one of RSDS and mini-LVDS being said selected communication standard.
In accordance with another embodiment of the present invention, the act of formatting only the pixel data includes an act of repeating each bit of the pixel data a plurality of times during the act of formatting only the pixel data to provide an effective pixel data rate that is received according to the pixel data rate of RSDS and mini-LVDS.
In accordance with yet another aspect of the present invention, the method further comprises an act of receiving a plurality of parameters corresponding to a viewable area of the television display, wherein the act of generating includes an act of generating, responsive to said selected communication standard being one of RSDS and mini-LVDS, the pixel display timing and control signals to display the formatted pixel data at the pixel data rate corresponding to the selected communication standard on a television display based upon the plurality of parameters corresponding to the viewable area of the television display.
Still other aspects, embodiments, and advantages of these exemplary aspects and embodiments, are discussed in detail below. Moreover, it is to be understood that both the foregoing information and the following detailed description are merely illustrative examples of various aspects and embodiments, and are intended to provide an overview or framework for understanding the nature and character of the claimed aspects and embodiments. Any embodiment disclosed herein may be combined with any other embodiment in any manner consistent with the objects, aims, and needs disclosed herein, and references to “an embodiment,” “some embodiments,” “an alternate embodiment,” “various embodiments,” “one embodiment” or the like are not necessarily mutually exclusive and are intended to indicate that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment. The appearances of such terms herein are not necessarily all referring to the same embodiment.
Various aspects of at least one embodiment are discussed below with reference to the accompanying figures, which are not intended to be drawn to scale. In the figures, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every figure. In the drawings:
The systems and methods described herein are not limited in their application to the details of construction and the arrangement of components set forth in the description or illustrated in the drawings. The invention is capable of other embodiments and of being practiced or of being carried out in various ways. Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including” “comprising” “having” “containing” “involving” and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.
In many LCD panels, the LVDS communication standard is used to transfer data between subsystems on the panel. For example, some display system controllers use LVDS to send pixel data, such as RGB color values, to an external panel timing controller. The external panel timing controller will generate the timing/control signals necessary to display the pixel on the LCD panel. Such systems incorporating external timing controllers are known in the art, such as the previously mentioned SupraHD® 780 integrated HDTV LCD display control processor, an example of which is functionally depicted in
The pixel data in the LVDS standard and the associated timing/control signals may be used by the external panel timing controller 320 to generate complex timing schemes according to which the pixel data should be displayed on the LCD panel 330. The behavior of each column and row in LCD panel 330 is driven by a respective source driver 340 and a gate driver 350, respectively. Thus, the timing/control schemes generated by the external panel timing controller 320 are transmitted to the source drivers 340 and gate drivers 350. These timing/control schemes may include delay durations that indicate the number of clock cycles that a source driver 340 or gate driver 350 should wait before displaying some particular pixel data on the LCD panel 330. The pixel data itself is typically sent from the external panel timing controller 320 to the source drivers 340 at the panel 330 through the use of a differential signaling interface other than LVDS, for example, RSDS or mini-LVDS. Both the RSDS and mini-LVDS standards operate at a rate of 2 bits per clock cycle, a different rate than the 7 bits per clock cycle used in the LVDS transmission standard.
Embodiments of the present invention eliminate or reduce the cost and complexity associated with an external panel timing controller by providing a display system controller that is capable of both generating timing/control signals and transmitting pixel data according to one of LVDS, RSDS, and mini-LVDS standards. A system 400 in accordance with one such embodiment is illustrated in
The components of the display system controller 410 in an exemplary embodiment can be seen in
The packed pixel data is then sent to the transmitter 530. Since the transmitter 530 may receive the pixel data from the data framer 520 in parallel communication format, the transmitter 530 may include a plurality of parallel-to-serial converters 532 configured to convert the pixel data from parallel to serial format, as is required for differential signaling in accordance with LVDS, RSDS, and mini-LVDS standards. In accordance with an aspect of the present invention, the parallel-to-serial converters 532 convert the parallel data to serial data at a rate that is 7 times or 8 times the pixel clock rate, although the effective data rate may differ as discussed in more detail below. Depending on the desired transmission format, a plurality of channel drivers 534 then transmit the pixel data via differential signaling according to the desired transmission standard either directly to the source drivers 440 or to an external panel timing controller. As will be explained in more detail below, the transmitter 530 may be configured to transmit pixel data at one particular bit rate, for example, 7 bits per clock cycle, or 8 bits per clock cycle although the effective pixel data transmission rate as seen by the receiver may differ, for example, 2 bits per clock cycle.
An integrated timing controller 540 is also provided which may generate timing/control signals that can be transmitted directly to the source drivers 440 and the gate drivers 450, thereby obviating the need for an external panel timing controller. The display system controller 410 may be configured to allow the selection of a desired transmission standard from a plurality of transmission standards for which standard-specific timing/control signals can be generated by the integrated timing controller 540, for example, RSDS or mini-LVDS.
In some embodiments, the data framer 520, the transmitter 530, and the integrated timing controller 540 may be integrated into a single processor-based circuit on a single microchip 510. This type of integrated configuration is commonly referred to as a “system on a chip.” The microchip 510 may comprise a processor such as a programmable general purpose Digital Signal Processor (DSP), available from companies such as Analog Devices, Motorola, or Texas Instruments, or an application-specific DSP designed for a particular application and provided by a company such as Zoran Corporation of Sunnyvale, Calif. The microchip may also include other functionality, such as an MPEG-2 decoder, an 8VSB demodulator, and an NTSC video decoder, as in the previously mentioned SupraHD® 780 line of processors. Each of the data framer 520, the transmitter 530, and the integrated timing controller 540 may be implemented as a microcontroller or state machine on the microchip 510. In other embodiments, the data framer 520, the transmitter 530, and the integrated timing controller 540 may be implemented in software or firmware executed on a main processor, or in a combination of hardware and software (and/or firmware). The microchip 510 may further include memory components such as ROM, RAM, Flash, or other memory components known in the art. The memory components generally include a combination of RAM memory and ROM memory, but may also include other types of memory, such as flash or disk-based memory. In accordance with embodiments of the present invention, the memory components may be adapted to store instructions for the processor, as well as image data or pixel data.
The microchip 510 may further include one or more timing sources, for example, oscillators or phase-locked loops. The microchip 510 may include one or more interfaces operating according to various industry standards, for example, LVDS, RSDS, mini-LVDS, BLVDS, USB, FireWire, Ethernet, USART, SPI, HDMI, or other interfaces known in the art. The microchip 510 may also include one or more voltage regulators or power management circuits.
The display system controller 410 may be configured to format and transmit pixel data and generate timing and control schemes according to one or more transmission standards, for example, LVDS, RSDS, or mini-LVDS. This configuration may be set on the microchip 510 during or prior to its incorporation in the system 400. The display system controller 410 may require the incorporation of additional components in order to operate according to some transmission standards. For example, an external resistor (not shown) may be electrically coupled to the transmitter 530 or other component in order to bring the differential signal being transmitted into an expected range, or to achieve an expected voltage swing. In some embodiments, a different transmission standard may be set later. In other embodiments, once a transmission standard is set it cannot be changed. However, it will be appreciated that the data framer 520, the transmitter 530, and the integrated timing controller 540 are otherwise selectively configurable to operate in any one of a number of transmission standards without modification.
Referring still to
In one embodiment, the data framer 520 may be selectively configured to provide data in the LVDS format to the transmitter 530. An example of a data scheme 600 for 12-bit color pixel data in accordance with LVDS transmission standards can be seen in
The data framer 520 may be configured to arrange the pixel data in the LVDS standard data format as described above and send it to the transmitter 530. In several embodiments, the transmitter 530 is an LVDS transmitter that operates in a well known manner, and is configured to transmit data at 7 bits per LVDS clock cycle via a differential signaling interface (not shown) in serial communication format. The transmitter 530 may be further configured to transmit a clocking signal to facilitate coordination or synchronization with a component receiving the pixel data. In this way, during each clock cycle 7 bits of data are transferred via the transmitter 530 operating at 7 bits per clock cycle.
In some embodiments, the data framer 520 may be selectively configured to provide data in a format operating at a different bit rate than the transmitter 530. For example, both RSDS and mini-LVDS operate at 2 bits per clock cycle. An example of a data scheme 700 for 8-bit color pixel data in accordance with mini-LVDS and RSDS transmission standards can be seen in
In the data scheme 700, bits of pixel data are arranged by the data framer 520 according to the mini-LVDS or RSDS transmission standards. As can be seen in
In the data scheme 700 and other data schemes, the upper channel 720 and the lower channel 730 may be used to transmit pixel data for different regions of the panel 430. For example, the upper channel 720 may be used to transmit pixel data for the left side of the panel 430, whereas the lower channel 730 may be used to transmit pixel data for the right side of the panel 430.
As will be noted, the data mapping 700 includes 6 data lines divided into an upper channel 720 and a lower channel 730. In embodiments where the transmitter 520 is configured to transmit more than 6 differential signals simultaneously, more data lines and upper and lower channels may be incorporated. The exemplary embodiment seen in
The data framer 520 may be configured to arrange the pixel data in the mini-LVDS or RSDS standard data format as described above and send it to the transmitter 530. In several embodiments as described above, the transmitter 530 is an LVDS transmitter that operates in a well known manner, and is configured to transmit data at 7 bits per clock cycle via a differential signaling interface (not shown) in serial communication format. However, components (such as receivers associated with the source drivers 440 and the gate drivers 450) electrically coupled to receive the mini-LVDS or RSDS data may be configured to receive the data at 2 bits per clock cycle. Several embodiments of the present invention deal with this difference in bit rates by repeating bits in order to simulate the lower bit rate when using a transmitter that operates at the higher bit rate.
An example embodiment in which bits 722 and 724 are transferred at 7 bits per clock cycle is shown in
It should be noted that other variations of data mapping can be implemented and are contemplated within the scope of this disclosure. For example, in some embodiments the first bit 722 may be mapped for the first 4 bits of the 7 bit clock cycle, while the second bit 724 may be mapped for the remaining 3 bits of the cycle. In other embodiments, to achieve a 50% duty cycle, 8 bits per clock cycle may be used, in which case the first bit 722 may be mapped to the first half of the 8 bit clock cycle, and the second bit 724 may be mapped to the second half of the 8 bit clock cycle. This embodiment is depicted in
It should be appreciated that the data schemes 600 and 700 are offered for exemplary purposes only, and that other data schemes may be mapped and sent in the manner described above.
Referring again to
The transmitter 530 may be provided with an interface (not shown) through which it can send differential signals. This interface may comprise one or more data pins that can be coupled to other components, for example, receivers associated with the source drivers 440 and the gate drivers 450. The configuration of the interface and the assignment of the data pins may vary depending on which transmission standard is selected. In some embodiments, the transmitter 530 may further transmit differential signals through the interface at a set current. In other embodiments, the current may be variable. In some embodiments, one or more external resistors may be incorporated into the interface in order to bring the voltage swings within an expected range for the chosen transmission standard.
In accordance with an embodiment of the present invention, the display system controller 410 incorporates an integrated timing controller 540 that generates timing/control signals that are necessary to control the function of the LCD panel 430 in some transmission standards. For example, pixel data sent to the source drivers 440 and the gate drivers 450 according to the RSDS or mini-LVDS standards must be accompanied by timing/control signals to ensure the pixel data is displayed correctly by the panel 430 at the correct time. Embodiments of the present invention obviate the need for an external panel timing controller by incorporating the integrated timing controller 540, which may be provided in the same circuit as the data framer 520 and the transmitter 530 on the microchip 510. The integrated timing controller 540 can be configured by being programmed through the use of programmable registers or other memory locations and logic gates to generate timing signals for a variety of panels.
In some embodiments, the integrated timing controller 540 may be configured to receive timing/control signals such from an external source, such as a graphics card, video controller, or set top box (not shown). In other embodiments, these timing/control signals may be generated on chip 510 and provided to the integrated timing controller 540 and the data framer 520. The timing/control signals that are received by the integrated timing controller 540 may include those used to provide pixel data in the LVDS transmission standard, for example, VSYNC, HSYNC, DE, and the pixel clock signal, or other timing/control signals. These timing/control signals can then be used to generate other timing/control signals that can be directly sent to the source drivers 440 and the gate drivers 450 without the use of an external panel timing controller. These signals can be used to correctly time the display of pixel data sent from the transmitter 530 to the panel 430 when the pixel data is sent in a transmission standard such as RSDS or mini-LVDS.
Each of the timing control circuits 920a-j is responsible for providing a single source or gate driver control signal, STH, STV, CPV, OE, etc., whose starting point (e.g., the point in time at which the signal is asserted) and width (and/or assertion level) is fully programmable. These timing/control signals may include the signals identified in
Each programmable timing control circuit 920 includes a plurality of programmable comparators 1020a-d, a plurality of Set/Reset (SR) flip-flops 1030a-b that are clocked by the PIXEL_CLK signal, a plurality of two input multiplexers 1040a-d, a D-type flip-flop 1050, an output multiplexer 1060, and some associated logic gates 1035, 1045, 1047, 1055, and 1057. Each of the programmable comparators 1020a-d receives a 12 bit programmable value that is compared to the input of the comparator. For example, comparator 1020a receives a programmable LINE_START value which indicates the starting line of the display at which a first control signal is to be asserted, comparator 1020b receives a programmable LINE_END value which indicates the ending line of the display at which the first control signal is to be deasserted, comparator 1020c receives a programmable PIXEL_START value which indicates the starting pixel of the display at which a second control signal is to be asserted, and comparator 1020d receives a programmable PIXEL_END value which indicates the ending pixel of the display at which the second control signal is to be deasserted. An output control signal designated “output” in
During operation of the programmable timing control circuit 920, the output of the line counter 1010 (LINE_COUNT) is compared to the LINE_START and LINE_END values by the comparator 1020a and 1020b. When the output of the line counter 1010 (LINE_COUNT) is equal to the LINE_START value, SR flip-flop 1030a is set by the output of comparator 1020a, and when the output of the line counter 1010 (LINE_COUNT) is equal to the LINE_END value, SR flip-flop 1030a is reset or cleared by the output of comparator 1020b. Similarly, during operation, the output of the pixel counter 1012 (PIXEL_COUNT) is compared to the PIXEL_START and PIXEL_END values by the comparators 1020c and 1020d. When the output of the pixel counter 1012 (PIXEL_COUNT) is equal to the PIXEL_START value, SR flip-flop 1030b is set by the output of comparator 1020c. SR flip-flop 1030b may be reset or cleared based upon the output of comparator 1020d, or based upon the output of comparators 1020d and 1020b. For example, based upon a state of the MUX_CONTROL1 signal provided to multiplexer 1040c, one of the two inputs (designated 0 and 1 in
Multiplexer control signals MUX_CONTROL3 and MUX_CONTROL2 are used to select which of the outputs of the SR flip-flops 1030a and 1030b are provided to the output of the multiplexers 1040a, and 1040b, respectively. For example, when the input designated 0 of multiplexer 1040a is selected, the non-inverting output Q of the SR flip-flop 1030a is provided to the output of the multiplexer 1040a, and when the input designated 1 of multiplexer 1040a is selected, the inverting output
Multiplexer control signal MUX_CONTROL4 is used to select the type of logic function to be applied to the output signals provided by multiplexers 1040a and 1040b. For example, when the input designated 0 of multiplexer 1040d is selected, the output of the multiplexer 1040d reflects a logical AND of the output signals provided by multiplexers 1040a and 1040b based upon the presence of AND gate 1045, and when the input designated 1 of multiplexer 1040d is selected, the output of the multiplexer 1040d reflects the logical OR of the output signals provided by multiplexers 1040a and 1040b based upon the presence of OR gate 1047.
Multiplexer control signal MUX_CONTROL5 is a 2-bit control signal used to select one of the four inputs (designated inputs 0 through 3) of multiplexer 1060 to provide to the output of the multiplexer. In response to a first value of the control signal MUX_CONTROL5 that selects the input designated 0, the multiplexer 1060 simply provides the output of multiplexer 1040d to the output of multiplexer 1060, and in response to a second value of the control signal MUX_CONTROL5 that selects the input designated 1, the multiplexer 1060 provides the logical opposite of output of multiplexer 1040d to the output of multiplexer 1060, based upon the inversion performed by inverter 1055. In response to a third value of the control signal MUX_CONTROL5 that selects the input designated 2, the multiplexer 1060 provides the output of D-type flip-flop 1050 to the output of multiplexer 1060, and in response to a fourth value of the control signal MUX_CONTROL5 that selects the input designated 3, the multiplexer 1060 provides the logical opposite of the output of D-type flip-flop 1050 to the output of multiplexer 1060 based upon the inversion performed by inverter 1057. D-type flip-flop 1050 is used to control de-assertion of the control signal (e.g., RVS, STH1, CPV1, OE1) provided by the output of multiplexer 1060. Depending upon the state of the multiplexer control signals MUX_CONTROL1-MUX_CONTROL5, the assertion level of the control signal provided by the output of multiplexer 1060, the point in time at which the control signal provided by the output of multiplexer 1060 is asserted, and the width of the control signal provided by the output of multiplexer 1060 may be adjusted to the requirements of the particular model of display panel being used.
In some embodiments, the display system controller 410 or the integrated timing controller 540 may be configured to receive or store one or more parameters relating to the details of the panel 430 incorporated in the system 400. These parameters may be necessary to calculate the timing scheme for the panel 430, since panels having different dimensions or other characteristics may require the source drivers 440 and the gate drivers 450 of the panel 430 to delay different amounts of time in order to synchronize and transmit the pixel data that will be displayed on the panel 430. In some embodiments these parameters may describe the dimensions of the panel 430, for example, the number of rows and columns in which the panel 430 is capable of displaying pixel data. In other embodiments, these parameters may include actual timing values, for example, the number of clock cycles that the source drivers 540 and the gate drivers 550 should wait before causing some portion of the pixel data to be displayed on the panel 430.
In still other embodiments, the display system controller or the integrated timing controller 540 may store dimensions and/or timing values relating to several different known LCD display panel configurations. This data may be stored in a memory component known in the art, for example, ROM, RAM, or Flash memory. In these embodiments, the one or more parameters may identify which panel configuration should be used by the integrated timing controller 540 in calculating a timing scheme. In other embodiments where timing values relating to several different panel configurations are stored, the integrated timing controller 540 may be able to detect which panel configuration is to be used through communication with the panel 430 or another component of the display system.
The parameters and/or the stored panel configuration can then be used, along with the other timing/control data (such as VSYNC, HSYNC, DE, and the pixel clock signals) received by the integrated timing controller 540 to generate timing signals that can be transmitted to the source drivers 440 and the gate drivers 450. These timing signals may be generated for any of a number of transmission standards, for example, RSDS or mini-LVDS. In some embodiments, timing signals will not be generated if a transmission standard is selected that does not require the integrated timing controller 540 to generate timing signals. For example, if the LVDS transmission standard is selected, the transmitter 530 may send the pixel data and associated control and clock values (such as HSYNC, VSYNC, DE, and LVDS clock) directly to an external timing controller which will generate its own timing signals. In some embodiments, the integrated timing controller 540 will be inoperative where a transmission standard has been selected that makes it unnecessary. In other embodiments, the integrated timing controller 540 may generate timing signals which are ignored or not received by other components in the system.
Having now described some illustrative aspects of the invention, it should be apparent to those skilled in the art that the foregoing is merely illustrative and not limiting, having been presented by way of example only. Numerous modifications and other illustrative embodiments are within the scope of one of ordinary skill in the art and are contemplated as falling within the scope of the invention.
This application claims priority under 35 U.S.C. 119(e) to U.S. Provisional Application Ser. No. 61/096,623 entitled “Integration of Differential Signal Transmission Interfaces with a Panel Timing Controller in System on Chip (SOC) Applications” filed Sep. 12, 2008, which is incorporated herein by reference in its entirety.
Number | Name | Date | Kind |
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