Patent Application
20170228484
This disclosure relates generally to the field of semiconductor circuit designs, in particular to the simulation of semiconductor circuit layout.
Typically, semiconductor circuit layouts are tested and verified using various simulation techniques to detect and correct design errors prior to releasing the design into production. Electromagnetic (“EM”) simulators are generally used to capture inductive distributed effects of large scale networks. Most EM simulators partition (mesh) the circuit layout to define unit cells for a particular given solver algorithm. Deep submicron CMOS processes require complex layouts with many small scale features (e.g., via arrays, slots, metal fill, and the like) to meet design rules. Complete modeling of these features significantly increase the number of mesh elements, which makes simulations long and sometime it may not be possible to simulate certain layouts. Further, complete modeling of various features is sometime unnecessary and uses up resources because many of these features can be treated in aggregate or ignored.
Circuit layouts in advanced process nodes (e.g., deep submicron CMOS) are too complex to be efficiently simulated in an EM simulator therefore, certain simplifications in the designs layout are required before the simulation. The simplification allows circuit designers to incrementally adjust the parameters of circuit design during the design process. Some examples of simplifications include merging slots or stripes of the same net, merging vias, eliminating or approximating fill, smoothing edges, and the like.
For certain EM structures, such as transformer or inductor windings, desired connectivity can be incorporated in the layout using metal resistors and representing those in the layout; however, this representation does not work for ground planes. The EM layouts usually use additional pins in the circuit layouts to match the distributed ground that cannot be cleanly separated using automated tool. Automated simplifications within a tool cannot be checked as the simplified layouts are not typically exportable to a flow. Therefore, manual simulations of the output S-parameters are performed; however, manual simplifications are prone to errors including but not limited to accidentally causing a short or an open in the circuit layout. Manual simulations do not detect unintended open that is simplified to the desired short, which can result in catastrophic consequences during device operation.
In accordance with an embodiment an apparatus is disclosed. The apparatus includes a circuit design unit configured to generate a circuit design layout, a simplified representation of the circuit design layout, and a low frequency extraction module coupled to the circuit design unit and configured to generate S-parameter model of one or more of the circuit design layout, the simplified representation of the circuit design layout, and the metal shape representation; and a resistor net list generation module coupled to the low frequency extraction module and configured to generate resistor based netlist of the S-parameter mode.
In accordance with another embodiment, a method is disclosed. The method includes generating a S-parameter model of a circuit design layout, the circuit design layout comprising one or more circuit ports, determining admittance parameters for each one of the S-parameter for the one or more of the circuit ports, determining whether the admittance parameter for one or more of the circuit ports in the circuit design layout is greater than a predetermined threshold conductance, and generating a resistor netlist representing the circuit design layout if the admittance parameter for the one or more of the circuit port is greater than a predetermined threshold conductance.
In accordance with yet another embodiment, a system is disclosed. The system includes, a circuit design unit, a low frequency extraction module coupled to the circuit design unit, a resistor net list generation module coupled to the low frequency extraction module and configured to generate resistor based netlist of a S-parameter model of the circuit design layout, a connectivity check module coupled to the resistor netlist generation module and configured to compare the resistor based netlist with a design intent resistor netlist, and generate a representation of the circuit design layout identifying one or more of circuit open and circuit shorts in the circuit design layout.
The following description provides many different embodiments, or examples, for implementing different features of the subject matter. These descriptions are merely for illustrative purposes and do not limit the scope of the invention.
According to an embodiment, a system and method is disclosed for circuit extraction using resistor based netlist. Conventional circuit extraction methods generate S-parameters for electromagnetic simulation. Typically, S-parameter based circuit extractions cannot distinguish among various circuit elements for example, vias in the circuit can be considered as open circuit and similarly, manufacturing holes can be mistaken for vias. This can result in simulation method mistakenly shortening the open circuit and opening certain connections causing the malfunction of the circuit. According to an embodiment, resistor based netlist of circuit extractions allow comparison of pairwise terminal resistance with a simplified extraction generated by a simulation tool using the S-parameter and identify and fix errors caused by erroneous circuit shorts or circuit open.
According to another embodiment, an optional resistor string based schematic/netlist 140 can be provided to the connectivity equivalent check module 150. The resistor string based netlist 140 represents design intent of the original circuit layout, which provides a benchmark for the connectivity equivalent check module 150 to identify any deviations from the original design intent. The connectivity of all low frequency extraction are compared to each other and also compared to designer intent supplied resistor string. The connectivity may be simple pairwise connectivity with a reasonable value of resistance indicating a short.
At 315, the admittance parameter or Y-parameter, for each S-parameter is generated. Admittance parameter or Y-parameter describe the electrical behavior of linear electrical network of the circuit layout. For example, a system with n ports, it is an n x n matrix. The parameter Y(i,j) corresponds to the current seen on port i when port j is driven by a unity voltage source and all other ports are grounded. Y-parameters are calculated deterministically from the s-parameters using known methods. At 320, the process then determines the admittance of each port at each pin based on the calculated Y-parameter and at 325 compares it to a predetermined threshold resistance.
The predetermined threshold resistance (R)can be any impedance/resistance of each port. According to an embodiment, the predetermined threshold is selected higher than the largest expected resistance seen in a typically connected metal system for example, less than 100 ohms and lower than the resistance that can be present due to numerical limitations of EM simulators for example in the Giga-ohm range. If a given circuit layout does not include intentionally long metal line with high resistance, then a default value of 10 k-ohm can also be used; however, this value can be adjusted based on given circuit structures. In an embodiment, the admittance parameters (Y-parameters) can be converted to impedance values (Z=1/Y) before comparing the admittance parameters with the predetermined resistance R. In yet another embodiment, the admittance parameter can be compared with a predetermined conductance G to determine whether the admittance parameter is greater than the predetermined threshold conductance G, where G=1/R. If the admittance at the given pin is less than the predetermined threshold, then at 330, a schematic or netlist is created, which is another representation of the circuit that includes the resistors (e.g., 1 ohm resistor or the like). At 335 the process determines if the admittance of all the pins have been evaluated and if admittance of all the pins have not been evaluated, then the process continues at 320 until the admittance of all pins in the layout have been evaluated against the predetermined threshold. The process of evaluating admittance of each pin can be mathematically represented as:
At 340 when all pins in the circuit layout have been evaluated for admittance, the process determines the possibility of additional current flow through all the pins after adding resistors. If there is a possibility of additional current flow at node i, then the process at 350 connects the pin to ground and continues to check all the pins at 355 to make sure each pin has been evaluated for additional current. The process of evaluating additional current through each node/pin can be mathematically represented as:
[1/{Y(i,i)+Σj≠i Y(i,j)}]>Rthreshold; connect a resistor between pin i and the ground.
As illustrated in the equation above, 1/(Y(i,i)) is the current flowing into the pin. The sum of all Y(i,j) is the currents flowing out of the pin to all the other (non-ground) ports. Thus, when adding all together, the current going into port i, that does not end up at any other port j, can be determined. That current, if present, indicates that it is going to ground. Y(i,j) is the current that exits node i when node j is excited by a voltage, that means if current is present (the resistance is low), then these nodes are connected. If no current is present, Y(i,j)˜0, and 1/Y(i,j)>>Rthreshold, then these nodes are not connected. For Y(i,i), port i is driven by a voltage source and all other nodes are grounded. By summing Y(i,j) (for all j i) and Y(i,i), all of the current going to other nets is cancelled. If additional current flows into node i that is not exiting at nodes j, then there can be a connection between node i and ground. Once all connections for addition ports are made, the layout is represented by a resistor netlist, which can be analyzed and simulated without causing short (or open) as it is in the case of the layout simplification that causes the unintentional short or open. With resistor netlist process, the DC connectivity is maintained across manual and automatic layout simplifications, including correlation to designer intent, which eliminates catastrophic open/short failures as in the case of conventional S-parameter analysis and minimizes iterations through full EM simulation on incorrect layouts.
While individual units such as units 410, 420, and 430 are illustrated for exemplary purposes; however, one skilled in the art will appreciate that these modules and units can be integrated in a design tool unit 425 (shown in dashed lines). Each individual unit can exchange data with the other unit and use the output of the other unit to generate the desired simplification layout. The design tool unit 425 can also include each of these individual modules as separate hardware units such a microcontrollers, individual special purpose circuit boards, or the like or these modules can be implemented as software modules using various circuit design software languages or can be integrated in a hardware or software unit or combination thereof.
A DC/low frequency Extraction module 440 generates DC equivalents (direct DC or extrapolated) of each simplification step of the circuit design as explained hereinabove with reference to
The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand various aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of various embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Although the subject matter has been described in language specific to structural features or methodological acts, it is to be understood that the subject matter of the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing at least some of the claims. Various operations of embodiments are provided herein. The order in which some or all of the operations are described should not be construed to imply that these operations are necessarily order dependent. Alternative ordering will be appreciated having the benefit of this description. Further, it will be understood that not all operations are necessarily present in each embodiment provided herein. Also, it will be understood that not all operations are necessary in some embodiments.
Moreover, “exemplary” is used herein to mean serving as an example, instance, illustration, etc., and not necessarily as advantageous. Also, although the disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others of ordinary skill in the art based upon a reading and understanding of this specification and the annexed drawings. The disclosure comprises all such modifications and alterations and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components (e.g., elements, resources, etc.), the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure. In addition, while a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.
