System and method for managing execution of internal commands and host commands in a solid-state memory

Abstract

Embodiments of the invention are directed to enable simultaneous or nearly simultaneous execution of internal and host-issued commands in a non-volatile storage subsystem while maintaining data consistency. Embodiments maintain validity information on data residing at physical addresses as well as logical to physical address mappings in the solid-state storage subsystem. In one embodiment, a controller within the storage subsystem selectively cancels internal commands that it determines to be writing data that has been rendered invalid by another command. In one embodiment, the determination is made by consulting the validity information kept by the controller in an invalid page table.

Description

BACKGROUND

Solid-state storage subsystems execute many internal commands in the course of their normal operation. For example, garbage collection is frequently performed on memory blocks that may contain both valid and invalid data. When such a memory block is selected for garbage collection, the garbage collection operation copies valid data within the memory block to a new location in memory and then erases the entire memory block, making the entire block available for future data writes. In addition to garbage collection operations, solid-state storage subsystems also perform read and write operations as dictated by memory commands issued by host systems.

BRIEF DESCRIPTION OF THE DRAWINGS

Systems and methods which embody the various features of the invention will now be described with reference to the following drawings, in which:

FIG. 1 is a block diagram illustrating a storage subsystem according to one embodiment.

FIG. 2A shows an example of executing host-issued commands and internal commands according to one embodiment.

FIG. 2B shows an example risk of data consistency failure when host-issued commands are not synchronized with internal commands.

FIG. 2C illustrates an example of managing memory commands according to one embodiment.

FIG. 3A is a flow diagram illustrating a method for managing memory commands in a solid-state storage subsystem according to one embodiment.

FIG. 3B is a flow diagram illustrating a method for managing memory commands in a solid-state storage subsystem according to one embodiment.

FIG. 4 illustrates an example mapping table and invalid table according to one embodiment.

DETAILED DESCRIPTION

While certain embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Overview

Solid-state storage subsystems perform internal system operations such as garbage collection and wear leveling to improve performance and longevity. Embodiments of the invention are directed to managing the simultaneous or nearly simultaneous execution of internal system commands (e.g. garbage collection commands) and commands received from host systems. Executing garbage collection commands with host-issued commands improves the performance of the storage subsystem by preventing stalls that can occur as a result of the storage subsystem running out of free blocks and being forced to execute garbage collection commands to free up blocks for pending host-issued commands. However, one challenge of executing internal system commands with host system commands is maintaining data consistency while executing both types of commands. For example, a garbage collection command may be issued to read data from a certain logical location “A” that corresponds to a physical location “X” and write the data to a new physical location “Y.” While the read portion of the garbage collection command is completed and the write portion is awaiting execution, a host write command may cause new data to be written to the logical location “A,” thus rendering the data to be written by the pending garbage collection command outdated. If the pending garbage collection write is allowed to execute, it would write the outdated data and cause data consistency issues.

In one embodiment of the invention, a controller manages the simultaneous or nearly simultaneous execution of internal commands and host commands by maintaining validity information on data residing at physical addresses in the solid-state storage subsystem and selectively cancelling a pending internal command if it is determined that the internal command is attempting to write data that has been rendered invalid by another command (e.g. a host-issued write command or another internal command). As will be further described below, the maintenance of validity information and selective execution of internal commands help ensure data consistency while allowing for the simultaneous or nearly simultaneous execution of internal commands and host commands. Although the present disclosure illustrates various embodiments by using garbage collection command examples, the disclosure is not so limited and is applicable to managing the execution of any type of internal system commands (e.g. wear leveling commands) with host-issued commands.

System Overview

FIG. 1 is a block diagram illustrating a storage subsystem embodiment. As shown, a storage subsystem 140 includes a controller 150, which in turn includes a host command queue 142, an internal command queue 144, and an internal operation module 148. In one embodiment, the host command queue 142 receives memory commands from a driver 132 residing within a host system 130 and the internal command queue 144 receives commands from the internal operation module 148, which may manage various internal operations such as garbage collection and/or wear leveling. In other embodiments, the commands from the driver 132 and the internal operation module 148 are received into a single queue for execution. The memory commands from the driver 132 may include write and read commands issued by the host system 130, while memory commands from the internal operation module 148 may include commands used for garbage collection. As further shown in FIG. 1, in one embodiment, the controller 150 executes the commands in the host command queue 142 and the internal command queue 144 in one or more non-volatile solid-state memory arrays 160.

In one embodiment, the controller 150 also maintains several data structures to help ensure that commands from the host command queue 142 and the internal command queue 144 are executed in a manner as further described herein to maintain data consistency. The data structures include, in one embodiment, an invalid page table 152 and a mapping table 154. In one embodiment, the invalid page table 152 keeps track of the validity of data located at physical page addresses throughout the non-volatile solid-state memory arrays 160, while the mapping table 154 keeps track of the correspondence between logical block addresses (LBA) and physical addresses in the non-volatile solid-state memory arrays 160.

Command Execution Examples

FIG. 2A is a block diagram illustrating an example of managing execution of memory commands. Although two queues are shown, the same management method can be applied to embodiments where commands are stored in one queue. Other embodiments may include more than two queues and the command execution management processes disclosed herein are applicable to those embodiments as well. In one embodiment, commands from both queues are concurrently processed and may be executed in a different order than the order in which the commands were originally placed into the respective queues. FIG. 2A also illustrates two commands 180 and 182 that are directed to the same LBA location (LBA 3), and embodiments of the invention are directed to maintaining data consistency while executing these commands, as further described below.

FIG. 2B shows an example risk of data consistency failure when host-issued commands are not synchronized with internal commands. As shown in FIG. 2B, host commands and internal commands that are directed to the same memory location (e.g. commands 180 and 182 shown in FIG. 2A) may be executed in a simultaneous or nearly simultaneous fashion. Illustration 202A shows an internal command 212 (e.g. a garbage collection command) reading data from a LBA 0 to copy the data to a new location. The LBA 0 entry in the mapping table 154 points to a physical address 220 at which the data is located. Illustration 204A shows a host-issued write command 214 writing to the same LBA 0 from which the internal command 212 has read data in illustration 202A. Illustration 204A shows that the mapping table 154 is updated to point to a physical address 222 at which the new data from the host is written. In illustration 206A, the internal command 212 attempts to complete the copy operation for the originally read data by updating the mapping table entry for LBA 0 to point to a new physical address. However, the original data is now stale because of the host write shown in illustration 204A. Without any synchronization, the internal command 212 is allowed to complete and illustration 208A shows the entry for LBA 0 in the mapping table 154 pointing to stale data at a physical address 224.

FIG. 2C illustrates an example of managing memory commands according to one embodiment that eliminates the risk of failure illustrated in FIG. 2B by synchronizing host-issued write commands with internal commands such as garbage collection commands. Illustrations 202B and 204B in FIG. 2C are the same as their FIG. 2B counterparts 202A and 204, respectively. Illustration 206B shows that the command 212 is canceled as a result of the controller determining from the invalid page table 152 that the original data is no longer valid (stale) due to the host write in illustration 204B. In one embodiment, the invalid page table 152 indicates the validity status of data in the non-volatile memory arrays 160, and the controller is configured to cancel an internal command that attempts to write data indicated by the invalid page table as invalid. Illustration 208B shows that data consistency is preserved as a result of the cancellation, as the entry LBA 0 in the mapping table 154 continues to point to the new data written by the host.

Managing Write Locations

FIG. 3A is a flow diagram illustrating a method 300 for handling host-issued write commands in a solid-state storage subsystem according to one embodiment. In block 304, the controller 150 begins by looking up an original physical page address in the mapping table for a given LBA associated with a host-issued write command. Then in block 306, the controller 150 invalidates the original page address it obtained in block 304 in the invalid page table (e.g. by marking an entry with the original page address as invalid). Then in block 308, the controller updates the mapping table for the given LBA with the new physical page address at which the new data will be written at block 310. In block 310, the controller 150 executes the host write command on the new physical page address to write data there.

FIG. 3B is a flow diagram illustrating a method 350 for managing internal commands in a solid-state storage subsystem according to one embodiment. In one embodiment, the method 350 is performed by the controller 150 to determine whether a pending internal command should be executed. In block 354, the controller 150 checks the invalid page table to determine if the data at the physical page address from which the pending internal command is attempting to copy has been invalidated. For example, if an internal command is supposed to copy data located at a physical address “A” to a physical address “B,” the controller would check the invalid page table to determine if the data at “A” has been invalidated. If the page address was invalidated, the controller 150 would cancel the internal copy command in block 356. In one embodiment, as an internal copy command includes a read and a write command, the check is performed prior to executing the read or the write command. In one embodiment, the check is performed prior to executing the write command. This checking and cancellation method prevents the writing of stale data. It would be apparent to one of ordinary skill in the art that the steps in FIGS. 3A and 3B could be performed in any appropriate order.

FIG. 4 illustrates an example mapping table 402 and an example invalid page table 404 and the changes to both tables as a result of executing of a host-issued write command (a user data write command). The mapping table 402A shows the mapping table before the execution of the user data write command. As shown, each entry maps an LBA to a corresponding physical address. For example, LBA 2 is mapped to the address block 0, page 14. As previously shown in block 308 of FIG. 3A, the mapping table is updated prior to a host-issued (user) data write. Here in FIG. 4, after the user data write operation is completed, the mapping table 402B shows an entry has been updated to reflect the state of the memory after the user data write. In this particular example, LBA 1 has been updated from block 0, page 13, to block 1, page 12 (shown in bold).

FIG. 4 also shows changes to the invalid page table 404 as a result of executing the user data write command. The invalid page table 404A shows the table before the execution, with the entry for block 0, page 13 indicating the address as containing valid data. As previously shown in block 306 of FIG. 3A, the invalid page table is updated as the controller executes a user data write command. In the invalid page table 404B, the entry for block 0, page 13 is changed to invalid as a result of the user data write operation. This means that the data in block 0, page 13 is no longer valid, and any pending internal command for that address will be blocked from execution. This change in the invalid page table 404B is related to that shown in the mapping table 402B (LBA 0 now corresponding to block 1, page 12). Also, the entry for block 1, page 12, is changed from an un-initialized (or empty) value to valid.

In one embodiment, the validity value of a particular entry in the invalid page table can be “valid,” “invalid,” or an un-initialized value. In another embodiment, the validity value of a particular entry can be “valid” or “invalid.” In one embodiment, the invalid page table is implemented as a bitmask, and a bit is used to represent the validity of data at a page address. In one embodiment, the mapping table is implemented as an array of physical chunk addresses, and an index into the array is used to represent logical addresses associated with the physical chunk addresses. In one embodiment, one or both of the data structures employ atomic transactions so that pending changes to the data structures must complete before additional data access requests can be processed. This ensures that multiple controller processes (e.g. one handling host commands and another handling internal commands) that are accessing the data structures can read the most current data, thus preventing a process from executing a command that overwrites valid data with invalid data.

CONCLUSION

The features and attributes of the specific embodiments disclosed above may be combined in different ways to form additional embodiments, all of which fall within the scope of the present disclosure. Although the present disclosure provides certain preferred embodiments and applications, other embodiments that are apparent to those of ordinary skill in the art, including embodiments which do not provide all of the features and advantages set forth herein, are also within the scope of this disclosure. Accordingly, the scope of the present disclosure is intended to be defined only by reference to the appended claims.

Claims

1. A method of managing memory operations in solid-state memory, the method comprising: accessing an internal command and a host command scheduled to be executed at least partially in parallel; wherein the internal command is a multipart command comprising at least a first portion and a second portion capable of being executed separately from the first portion;executing the first portion of the internal command, wherein executing the first portion of the internal command comprises accessing a physical page address;executing the host command prior to execution of the second portion of the internal command, wherein executing the host command comprises accessing the physical page address;determining whether the host command has modified data stored at the physical page address; andresponsive to determining that the host command has modified the data stored at the physical page address, cancelling execution of the second portion of the internal command.

2. The method of claim 1, wherein the first portion of the internal command comprises a read command.

3. The method of claim 1, wherein the second portion of the internal command comprises a write command.

4. The method of claim 1, wherein determining whether the host command has modified the data stored at the physical page address comprises determining whether an invalid page table indicates that the data stored at the physical page address has been invalidated.

5. The method of claim 4, wherein the invalid page table is implemented as a bitmask.

6. The method of claim 1, wherein the host command and the internal command are stored in a single queue.

7. The method of claim 1, wherein the host command is stored in a first queue and the internal command is stored in a second queue.

8. The method of claim 7, wherein host commands stored in the first queue and internal commands stored in the second queue are at least partially executed concurrently.

9. A storage sub-system comprising: a non-volatile memory; anda controller configured to: access an internal command and a host command scheduled to be executed at least partially in parallel; wherein the internal command is a multi-part command comprising at least a first portion and a second portion capable of being executed separately from the first portion;execute the first portion of the internal command, wherein executing the first portion of the internal command comprises accessing a physical page address;execute the host command prior to execution of the second portion of the internal command, wherein executing the host command comprises accessing the physical page address;determine whether the host command has modified data stored at the physical page address; andresponsive to determining that the host command has modified the data stored at the physical page address, cancel execution of the second portion of the internal command.

10. The storage sub-system of claim 9, wherein the first portion of the internal command comprises a read command.

11. The storage sub-system of claim 9, wherein the second portion of the internal command comprises a write command.

12. The storage sub-system of claim 9, wherein the controller is further configured to determine whether the host command has modified the data stored at the physical page address by determining whether an invalid page table indicates that the data stored at the physical page address has been invalidated.

13. The storage sub-system of claim 12, wherein the invalid page table is implemented as a bitmask.

14. The storage sub-system of claim 9, further comprising a queue configured to store the host command and the internal command.

15. The storage sub-system of claim 14, wherein the queue is maintained by the controller.

16. The storage sub-system of claim 9, further comprising a first queue configured to store the host command and a second queue configured to store the internal command.

17. The storage sub-system of claim 16, wherein host commands stored in the first queue and internal commands stored in the second queue are at least partially executed concurrently.

18. The storage sub-system of claim 16, wherein the first queue and the second queue are maintained by the controller.

19. The storage sub-system of claim 9, wherein the non-volatile memory comprises a solid-state non-volatile memory.