The present disclosure relates generally to information handling systems, and, more particularly to a system and method for managing processor execution in a multiprocessor system.
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to these users is an information handling system. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may vary with respect to the type of information handled; the methods for handling the information; the methods for processing, storing or communicating the information; the amount of information processed, stored, or communicated; and the speed and efficiency with which the information is processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include or comprise a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systerns, data storage systems, and networking systems.
Information handling systems, including computer systems, may include multiple microprocessors, memory, and various input and output devices. The components of a computer system are communicatively coupled together using one or more interconnected buses. As an example, the architecture of a computer system may include a processor that is coupled to a processor bus or host bus. In the case of multiprocessor computer systems, two or more processors may be coupled to the processor bus. A memory controller bridge may be coupled between the processor bus and system memory. In addition, a PCI bridge may be coupled between the processor bus and the PCI bus of the computer system. In some computer systems, the memory controller bridge and the PCI bridge are incorporated into a single device, which is sometimes referred to as the north bridge of the computer system. An expansion bridge, sometimes referred to as a south bridge, couples the PCI bus to an expansion bus, such as the ISA bus. The south bridge also serves as a connection point for USB devices and an IDE bus. The south bridge may also include an interrupt controller.
A set of processors in a multiprocessor computer system typically include one processor that is identified as the bootstrap processor. The bootstrap processor executes the boot code of the computer system, including the power-on self-test (POST) code. The other processors of the computer system are referred to as application processors. Each processor may be logically subdivided into multiple logical processors. Each of the logical processors may execute in parallel different threads of one or more multi-threaded software applications. The logical processors may share some hardware resources of the processor. The logical processors of a processor may also share external resources, including the L3 cache of the computer system. When the computer system is initiated, each logical processor of each processor of the computer system may attempt to initialize or reset some resources that are common to all processors or common to all logical processors of the computer system. This circumstance will often result in a race condition in which each logical processor of the computer system attempts to access a semaphore and execute a task with respect to the common resource. Often, the resetting of each common resource by each processor or logical processor results in unnecessary processor contention and the waste of processor resources.
In accordance with the present disclosure, a multiprocessor information handling system and method for operation is disclosed in which each of the processors of the system executes a software program according to a controlled execution scheme. A bootstrap processor determines if a controlled execution mode is in effect and sets a bitmapped set of flags. Each processor checks the flags to determine if the processor must execute the software program in a controlled execution. If the processor must execute the software program in a controlled execution mode, each processor determines from a processor-specific flag in the set of flags if the processor is individually enabled to execute the software program. If the processor is enabled to execute the software program, the processor executes the software program and resets the processor-specific flag so that the software program will not be executed a second time by the processor or a logical processor of the processor.
The system and method disclosed herein is technically advantageous because it prevents contention by the processors for the execution of a software program. When the controlled execution mode is enabled, each processor of the information handling system cannot execute a designated software program until the processor gains control of a semaphore and unless the processor is individually enabled through a bitmapped flag to execute the software program. In this manner, each processor and the logical processor of each processor is prevented from repeatedly attempting to execute a designated software program. As a result, a software program that need only be executed once with respect to each processor of the computer system is not executed multiple times by each logical processor of the computer system.
Another technical advantage of the system and method disclosed herein is also advantageous in that it permits a bootstrap processor to govern the execution of some startup programs by the application processors of the computer system. Through a set of bitmapped flags, the bootstrap processor may enable certain processors to execute the startup program and may disable other processors from executing the startup program. The bootstrap program has control over those application processors of the computer system that will execute and will not execute a startup program. Other technical advantages will be apparent to those of ordinary skill in the art in view of the following specification, claims, and drawings.
A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:
For purposes of this disclosure, an information handling system may include any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, or other purposes. For example, an information handling system may be a personal computer, a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The information handling system may include random access memory (RAM), one or more processing resources such as a central processing unit (CPU) or hardware or software control logic, ROM, and/or other types of nonvolatile memory. Additional components of the information handling system may include one or more disk drives, one or more network ports for communication with external devices as well as various input and output (I/O) devices, such as a keyboard, a mouse, and a video display. The information handling system may also include one or more buses operable to transmit communications between the various hardware components.
One of the processors 12 is the bootstrap processor and will execute the boot code of the computer system, including the power-on self-test code. The remaining processors are application processors. In the present disclosure, the processors will be referred to as Processor No. 1 (processor 12a of
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If it is determined at step 54 that the execution of the software task does require execution control, the global execution control signal 32 of bitmap flag 30 is set at step 56. At step 58 it is determined if the bootstrap processor has executed the software task. In some cases, the bootstrap processor will have previously executed the task as part of the initiation of the bootstrap processor. If the bootstrap processor has not previously executed the software task, the bit of the bitmap flag associated with the bootstrap processor, which in this example of bit 34 , is set to a logical 0 at step 68 to indicate that the bootstrap processor should be included in the remainder of the execution control method. The steps of
If it is determined at step 54 that the bootstrap processor has previously executed the software task, bit 34 of the bitmap flag is set to a logical 1 at step 60 to exclude the bootstrap processor from subsequent execution of the software task. At step 62, the flags of the bitmap flag associated with each of the respective application processors are set to a logical 0 to include the application processors in the execution of the software task. Shown in
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The processor determines at step 76 if the global execution control signal at bit 32 of bitmap 30 is set. If the global execution control signal is not set, execution control is not enabled and the processor is free to execute the software task at 78 and release the semaphore at step 80. If the global execution control signal is set, it is determined at step 82 if the bit of the bitmap associated with the processor is set to include the processor in the execution of the software task. If the bit of the bit map is set to include the processor in the execution of the software task, the bit is reset at step 84 and the software task is executed by the processor, as indicated at step 78. The execution of the software task can be accomplished by one of the logical processors of the processors. The resetting of the bit of the bitmap at step 82 prevents multiple logical processors of a single from processors from repeatedly executing the software task. Thus, the method set out in
The bits of bitmap flag 30 or extended bitmap flag 42 could be set in a manner to control the order in which the processors of the logical processors of a computer system execute a certain software task. As an example, in the case of the bitmap flag 30 of
The method disclosed herein is sufficiently flexible that method can be to identify some processors for execution, while identifying other processors as not being eligible for prosecution. The flags of bitmap 30 can be set so that only a subset of the processors of the computer system execute the software task. In this manner, the technique disclosed herein may be used to selectively control the execution of certain software tasks by the processor of the computer system at startup of the computer system. Although the present disclosure has been described with respect to an information handling system, it should be recognized that the system and method disclosed herein has equal applicability to any information handling system that includes multiple processors. Although the present disclosure has been described in detail, it should be understood that various changes, substitutions, and alterations can be made hereto without departing from the spirit and the scope of the invention as defined by the appended claims.