Patent Application
20090295443
1. Technical Field
The present invention embodiments pertain to signal modification. In particular, the present invention embodiments pertain to modifying signal characteristics to produce resulting signals compatible for a desired application.
2. Discussion of Related Art
Various devices may require signals of specific characteristics (e.g., format, type, shape, etc.) in order to operate or perform desired actions. For example, phase change Random Access Memory (PCRAM) is an emerging technology with respect to non-volatile memories. This technology is based on a programmable resistor structure (e.g., including a phase change material), commonly referred to as a phase change element (PCE), that is utilized to form a memory cell. The phase transition of a phase change element (PCE) is based on an amorphous-crystalline phase transition of the phase change material. This material is typically a chalcogenide (or chalcogenide-free) compound material (e.g., germanium, antimony and tellurium (GeSbTe) or germanium and antimony (GeSb)), where bit states are assigned to different phase states of the phase change element (PCE). These phase states differ significantly in electrical resistivity, thereby enabling a bit value (e.g., logic zero or one) stored within a memory cell to be determined by examining the resistance of the corresponding phase change element (PCE) of that cell. The phase states of the phase change element (PCE) are produced by a heating and cooling process controlled electrically by passing current through the phase change element (PCE), thereby resulting in ohmic heating. The storage of bit values within these types of memory cells requires certain signal pulses. For example, in order to store a high bit or logic one value within a memory cell (e.g., perform a set operation for a memory cell or transform the corresponding phase change element (PCE) from an amorphous to a crystalline state), a substantially trapezoidal pulse (i.e., a twenty nanosecond to two microsecond pulse with an amplitude between 0.30 and 3.8 volts) is sent through a cell resistor, thereby heating the phase change (PC) material above a crystallization temperature and lowering the material resistance. In order to store a low bit or logic zero value within the cell (e.g., perform a reset operation for the memory cell), a substantially rectangular high pulse with a short falling edge (i.e., a two nanosecond to one-hundred nanosecond pulse with an amplitude between 0.5 and 4.0 volts) is applied to the memory cell. This causes the phase change material to melt and enter the amorphous state during subsequent quench cooling, thereby increasing the material resistance.
However, the specific pulse shapes required to control the state of a phase change element (PCE) memory cell limits the ability to concurrently test numerous phase change (PC) memory devices and corresponding phase change element (PCE) memory cells in production since test equipment produce incompatible signals for controlling set operations of these types of cells.
The present invention embodiments provide a system to modify signal characteristics to produce a desired signal. The system comprises a signal module to modify signal characteristics. The signal module includes at least one input to receive an input signal including a substantially rectangular signal and one or more control signals and an output to provide a substantially trapezoidal signal. A signal unit of the signal module adjusts characteristics of the substantially rectangular signal including leading and/or trailing edges of that signal in accordance with the one or more control signals to produce the substantially trapezoidal signal. The present invention embodiments further include a probe card and method to adjust signal characteristics as described above.
The above and still further features of the present invention will become apparent upon consideration of the following detailed description of example embodiments thereof, particularly when taken in conjunction with the accompanying drawings wherein like reference numerals in the various figures are utilized to designate like components.
The present invention embodiments pertain to adjustment of signal characteristics for compatibility with a particular application and/or device. A signal module according to an embodiment of the present invention is illustrated in
An example application for the signal module pertains to testing of phase change element (PCE) memory cells. An example test arrangement for testing phase change (PC) memory devices each with phase change element (PCE) memory cells on a wafer is illustrated in
Pulse generator 30 may be implemented by any conventional or other pulse generator (e.g., Agilent Model 81110, etc.) and provides the appropriate pulses to set and reset memory cells of memory devices 75. Parameter analyzer 40 may be implemented by any conventional or other device (e.g., Agilent Model 4156C, etc.) and measures direct current (DC) characteristics (e.g., the threshold voltage and the resistance after the set or reset pulses) of the phase change elements (PCEs) within memory devices 75. Switch matrix 50 may be implemented by any conventional or other switching device (e.g., Keithley Model 7173-50 or K707, etc.) and is coupled to the signal generator and parameter analyzer. The switching matrix multiplexes channels of the pulse generator and parameter analyzer to probe card 60 for transference of channel signals with phase change (PC) memory devices 75. Probe card 60 includes a series of contact sets 31 for interfacing memory devices 75 on the wafer (and the corresponding memory cells) via pads 27. The probe card may include any suitable quantity of contact sets and enables transfer of signals with the memory devices. The probe card may be implemented by any conventional or other module accessing the memory devices.
This testing arrangement provides a flexible pulse shape, thereby enabling a universal optimum pulse shape (e.g., a substantially trapezoidal pulse as described above) to be produced to set the memory cells of memory devices 75. However, the arrangement has long test times and is not compatible with automatic test equipment (ATE) since this equipment produces rectangular pulses incompatible to set the memory cells, thereby rendering the arrangement unusable for production testing.
The signal module of the present invention embodiments enables parallel testing of phase change (PC) memory devices with automatic test equipment for production testing. This reduces the test time dramatically compared to the test times for the test arrangement described above. The signal module receives rectangular pulses from the automatic test equipment and provides the proper set and reset waveforms for the phase change elements (PCEs) of the memory devices.
An example test arrangement for testing phase change (PC) memory devices on a wafer and employing a probe card with the signal module according to an embodiment of the present invention is illustrated in
Wafer test system 10 may be implemented by any conventional or other automatic test equipment (ATE) (e.g., Adventest Models T5365P, T5571P, T5375 or T5377, or equivalents thereof). The wafer test system provides signals to probe card 70 and performs direct current (DC) characterization (e.g., measures the threshold voltage and the resistance after the set or reset pulses). The wafer test system provides short test times since testing of memory devices 75 (and corresponding memory cells 80) may be performed in parallel. For example, wafer test system 10 may provide pulses concurrently on a maximum of 3,172 channels (e.g., for an Adventest Model T5377), thereby enabling this equipment to be used for production testing.
However, wafer test system 10 produces substantially rectangular pulses for directing set (e.g., a fifty nanosecond to one microsecond pulse with an amplitude between 0.30 and 3.8 volts) and reset (e.g., a two nanosecond to one-hundred nanosecond pulse with an amplitude between 0.5 and 4.0 volts) operations of the memory cells. Although these reset pulses are sufficient to enable storage of a low bit value in memory cells 80 (e.g., perform the reset operation), the memory cells are not responsive to the set pulses to store a high bit value (e.g., perform the set operation) due to the short duration (of the falling or trailing edge) of the set pulse.
Accordingly, signal module 20 is employed within the testing arrangement to provide the appropriate signals to memory devices 75 to perform set and reset operations on memory cells 80. In particular, probe card 70 is coupled to wafer test system 10, and includes contact sets 31 for interfacing memory devices 75 on the wafer (and corresponding pads 27 and memory cells 80 of those memory devices). The probe card may include any suitable quantity of contact sets and enables transfer of signals with the memory devices. The probe card is coupled to memory devices 75 via contacts 31 and pads 27 and receives signals from wafer test system 10. The probe card includes one or more signal modules 20 in order to process signals received from the wafer test system and provide appropriate signals to corresponding memory devices 75 (and associated pads 27 and memory cells 80) for set (e.g., storing a high bit value) and reset (e.g., storing a low bit value) operations.
Each signal module 20 is associated with a corresponding memory device 75 (and pad 27 and associated memory cells 80 coupled to that pad). In other words, signal module 20 adjusts characteristics of the set pulses received from wafer test system 10 for compatibility with memory cells 80 of a corresponding memory device 75 to enable the memory cells to perform a set operation. The reset pulses from the wafer system are forwarded to the corresponding memory device (and pad 27 and associated memory cells 80) in their received state (since these pulses are sufficient to enable the memory cells to perform the reset operation). The signal module enables the use of automatic test equipment (ATE) for testing of phase change element (PCE) memory cells, thereby providing short test times due to the ability to test phase change (PC) memory devices in parallel.
An example signal module according to an embodiment of the present invention is illustrated in
Signal module 20 includes transistors 24, 26 and a capacitor 28. The transistors may be implemented by n-channel type Field Effect Transistors (FET). However, any conventional or other transistors may be utilized. Capacitor 28 may similarly be implemented by any conventional or other capacitors or capacitive devices. Each transistor 24, 26 includes a gate G, a source S and a drain D. The gates of transistors 24, 26 are connected together and coupled to line 32 (Ch1) receiving signals from wafer test system 10. The source (S) of transistor 24 is coupled to line 34 (Ch2) receiving signals from the wafer test system, while the drain (D) of transistor 24 is coupled to the source (S) of transistor 26. The drain (D) of transistor 26 is coupled to a corresponding pad 27, and to wafer test system 10 via line 36 (Ch3). Capacitor 28 is disposed between a ground potential and the junction between the drain (D) of transistor 24 and the source (S) of transistor 26.
Referring to
Operation of the signal module of
At a time t1, wafer test system 10 provides a substantially rectangular pulse or reset signal (e.g., fifty nanosecond pulse with a rising edge at time t1 and a falling edge at time t2) on line 36 (Ch3), while lines 32 (Ch1) and 34 (Ch2) each further receive the logic zero or low value signals (e.g., at or near ground potential). The low value signals on lines 32 (Ch1) and 34 (Ch2) provide transistors 24, 26 in a high ohmic state (e.g., cutoff) as described above. In this case, transistor 26 effectively decouples capacitor 28, and the pulse on line 36 (Ch3) is provided to pad 27. Thus, the pulse or reset signal from wafer test system 10 to enable one or more corresponding memory cells 80 to perform a reset operation is basically directly transferred (unmodified) to memory device pad 27 (and subsequently to one or more memory cells 80).
Operation of the signal module of
At a time t1, wafer test system 10 provides a substantially rectangular pulse (e.g., with a rising edge at time t1 and a falling edge at time t6) on line 32 (Ch1), while line 34 (Ch2) further receives the logic zero or low value signal (e.g., at or near ground potential). The pulse on line 32 (Ch1) is provided to the gates (G) of transistors 24, 26 enabling the transistors to subsequently enter an active state. The resistance of the transistors may be controlled based on the amplitude of the voltage provided to the gates (G) of those transistors. The wafer test system further provides a substantially rectangular pulse or set signal (e.g., one microsecond pulse with a rising edge at time t2 and a falling edge at time t4) on line 34 (Ch2) at time t2, while line 32 (Ch1) maintains the received pulse.
The active or conducting transistors enable capacitor 28 to charge based on the pulse or set signal on line 34 (Ch2). The capacitor charges to the amplitude level of that pulse signal in accordance with a time constant derived from the resistance of transistor 24 and capacitance of capacitor 28. The delay for capacitor 28 to charge results in the upward ramp formed for the rising or leading edge of the resulting signal (e.g., between times t2 and t3) at pad 27. When the capacitor is fully charged, the resulting signal at the pad includes substantially the same amplitude as the pulse on line 34 (Ch2).
At time t4, the falling edge of the pulse on line 34 (Ch2) enables capacitor 28 to discharge. The capacitor discharges to a voltage at or near ground potential in accordance with a time constant derived from the resistance of transistor 24 and capacitance of capacitor 28. The delay for capacitor 28 to discharge results in the downward ramp formed for the falling or trailing edge of the resulting signal (e.g., between times t4 and t5) at pad 27. The pulse on line 32 (Ch1) includes a duration (e.g., from time t1 to time t6) sufficient to maintain the gate voltage of transistors 24, 26 during the time interval of the resulting signal at pad 27 (e.g., through the charging and discharging of capacitor 28 to form the resulting pulse at pad 27).
The resulting substantially trapezoidal signal at pad 27 includes non-linear leading and trailing edges based on the charging and discharging of capacitor 28 (in accordance with the time constant) as described above, and is suitable to enable one or more corresponding memory cells 80 to perform a set operation. Since the gates of transistors 24, 26 are connected together, capacitor 28 charges and discharges based on a common time constant (e.g., derived from the resistance of transistor 24 and the capacitance of capacitor 28) with the resulting signal including symmetrical leading and trailing edges. By way of example, transistor 24 may include a resistance of 1 Kilo Ohms in an active or on state, transistor 26 may include a resistance of 500 Ohms (or as low as possible) in an active or on state, and capacitor 28 may include a capacitance of 500 pico Farads, thereby providing a time constant of approximately 500 nanoseconds (for charging and discharging of capacitor 28). However, the transistors and capacitor may include any suitable characteristics (e.g., resistance, capacitance, etc.) to attain any desired shape or waveform for the resulting signal at pad 27.
An example signal module according to another embodiment of the present invention is illustrated in
Signal module 20 includes transistors 24, 26 and a capacitor 28, each substantially similar to those described above. The transistors may be implemented by n-channel type Field Effect Transistors (FET). However, any conventional or other transistors may be utilized. Capacitor 28 may similarly be implemented by any conventional or other capacitors or capacitive devices as described above. Each transistor 24, 26 includes a gate G, a source S and a drain D. The gate of transistor 24 is coupled to line 32 (Ch1), while the gate (G) of transistor 26 is coupled to line 38 (Ch4) with each of these lines receiving signals from wafer test system 10. The source (S) of transistor 24 is coupled to line 34 (Ch2) receiving signals from the wafer test system, while the drain (D) of transistor 24 is coupled to the source (S) of transistor 26 as described above. The drain (D) of transistor 26 is coupled to a corresponding pad 27, and to wafer test system 10 via line 36 (Ch3) as described above. Capacitor 28 is disposed between a ground potential and the junction between the drain (D) of transistor 24 and the source (S) of transistor 26.
Signal module 20 receives a substantially rectangular reset signal (e.g., a two nanosecond to one-hundred nanosecond pulse with an amplitude between 0.5 and 4.0 volts) on line 36 (Ch3) and forwards this signal to a corresponding memory device pad 27 (unmodified) to enable one or more memory cells 80 to perform a reset operation (e.g., store a low bit or logic zero value). With respect to a set operation, the signal module receives a substantially rectangular set signal (e.g., a fifty nanosecond to one microsecond pulse with an amplitude between 0.30 and 3.8 volts) on line 34 (Ch2) and produces a resulting substantially trapezoidal signal with modified (e.g., non-linear, ramping, etc.) leading and trailing edges for pad 27 sufficient to enable one or more memory cells 80 to perform a set operation (e.g., store a high bit or logic one value).
Operation of the signal module of
At a time t1, wafer test system 10 provides a substantially rectangular pulse or reset signal (e.g., fifty nanosecond pulse with a rising edge at time t1 and a falling edge at time t2) on line 36 (Ch3), while lines 32 (Ch1), 34 (Ch2) and 38 (Ch4) each further receive the low value signals (e.g., at or near ground potential). The low value signals on lines 32 (Ch1), 34 (Ch2) and 38 (Ch4) provide transistors 24, 26 in a high ohmic state (e.g., cutoff) as described above. In this case, transistor 26 effectively decouples capacitor 28, and the reset signal or pulse on line 36 (Ch3) is provided to corresponding memory device pad 27. Thus, the reset signal from wafer test system 10 to enable one or more memory cells 80 to perform a reset operation is basically directly transferred (unmodified) to pad 27 (and subsequently to one or more corresponding memory cells 80).
Operation of the signal module of
At a time t1, wafer test system 10 provides a substantially rectangular pulse (e.g., with a rising edge at time t1 and a falling edge at time t4) on line 32 (Ch1), and a substantially rectangular pulse (e.g., with a rising edge at time t1 and a falling edge at time t6) on line 38 (Ch4). Line 34 (Ch2) further receives the logic zero or low value signals (e.g., at or near ground potential). The pulses on lines 32 (Ch1) and 38 (Ch4) are provided to the gates (G) of transistors 24, 26 enabling the transistors to subsequently enter an active state. The resistance of the transistors may be controlled based on the amplitude of the voltages provided to the gates (G) of those transistors. The wafer test system further provides a substantially rectangular pulse or set signal (e.g., one microsecond pulse with a rising edge at time t2 and a falling edge at time t4) on line 34 (Ch2) at time t2, while lines 32 (Ch1) and 38 (Ch4) maintain the received pulses.
The active or conducting transistors enable capacitor 28 to charge based on the pulse or set signal on line 34 (Ch2). The capacitor charges to the amplitude level of that pulse in accordance with a time constant derived from the resistance of transistor 24 and capacitance of capacitor 28. The delay for capacitor 28 to charge results in the upward ramp formed for the rising or leading edge of the resulting signal (e.g., between times t2 and t3) at pad 27. When the capacitor is fully charged, the resulting signal at the pad includes substantially the same amplitude as the pulse on line 34 (Ch2). Since the gate voltage of transistor 24 may be controlled independently of the gate voltage of transistor 26, the upward ramp or leading edge of the resulting signal at pad 27 may be controlled (without affecting the trailing edge of that signal).
At a time t4, the trailing or falling edges of the pulses or signals on lines 32 (Ch1) and 34 (Ch2) enable capacitor 28 to discharge. The falling edge of the pulse on line 32 (Ch1) effectively disables transistor 24, and enables the capacitor to discharge based on transistor 26 that is still enabled by the pulse or gate voltage from line 38 (Ch4). The capacitor discharges to a voltage at or near ground potential in accordance with a time constant derived from the resistance of transistor 26, the resistance of the phase change elements (PCEs) of one or more memory cells 80 and the capacitance of capacitor 28. The delay for capacitor 28 to discharge results in the downward ramp formed for the falling or trailing edge of the resulting signal (e.g., between times t4 and time t5) at pad 27. The pulse on line 32 (Ch1) includes a duration (e.g., from time t1 to time t4) sufficient to maintain the gate voltage of transistor 24 during the time interval prior to the falling edge of the resulting signal at pad 27 (e.g., through the charging of capacitor 28), while the pulse on line 38 (Ch4) includes a duration (e.g., from time t1 to time t6) sufficient to maintain the gate voltage of transistor 26 during the time interval of the resulting signal at pad 27 (e.g., through the charging and discharging of capacitor 28 to form the resulting pulse at pad 27). Since the gate voltage of transistor 24 may be controlled independently of the gate voltage of transistor 26, the upward and downward ramps of the respective leading and trailing edges of the resulting signal at pad 27 may be controlled independently.
The resulting substantially trapezoidal signal at pad 27 includes non-linear leading and trailing edges based on the charging and discharging of capacitor 28 (in accordance with the time constants) as described above, and is suitable to enable one or more corresponding memory cells 80 to perform a set operation. Thus, the leading and trailing edges of the resulting signal at pad 27 may be individually controlled (e.g., may be asymmetrical, where the resistance of transistor 24 controls the leading edge of the resulting signal, while the resistance of transistor 26 (and the resistance of the corresponding phase change elements (PCEs) of memory cells 80) controls the trailing edge of the resulting signal). The transistors and capacitor may include any suitable characteristics (e.g., resistance, capacitance, etc.) to attain any desired shape or waveform for the resulting signal at pad 27.
This embodiment enables a reduced number of memory devices 75 to be tested in parallel relative to the embodiment described above (since an additional channel of wafer test system 10 is utilized for testing (e.g., Ch4)). However, the embodiment provides greater flexibility with respect to the shape of the resulting signal at pad 27, and a significant quantity of memory devices may be concurrently tested, thereby enabling the embodiment to be utilized for production testing.
Operation of the present invention embodiments is described with reference to
It will be appreciated that the embodiments described above and illustrated in the drawings represent only a few of the many ways of implementing a system and method for modifying signal characteristics.
The present invention embodiments may be utilized to adjust any characteristics (e.g., shape, pulsewidth, frequency, leading and/or trailing edges, etc.) of any types of signals (e.g., pulses, sinusoidal signals, etc.). The present invention embodiments may receive any types of signals of any shapes (e.g., rectangular or triangular pulses, etc.) and produce any suitable waveforms (e.g., rectangular, trapezoidal, triangular, an undulating, flat or pointed apex, etc.).
The signal module may be employed within any suitable existing device (e.g., test unit, probe card, memory or other end device, etc.) or external of that device. In the case where the signal module is employed within a device, the newly formed device forms an embodiment of the present invention (e.g., probe card, test unit, memory device, etc.). The signal module may be used for any operational applications (e.g., during normal or other operation of a device, testing, etc.) and to produce signals for any types of memories (e.g., phase change (PC), etc.) or other devices responsive to certain types of signals.
The signal module may receive any suitable input signal (e.g., an initial pulse or other signal for adjustment, etc.) and/or control signals (e.g., to indicate or control modification of signal characteristics) to generate a desired signal. These signals may be provided by any suitable devices (e.g., test unit, signal generator, oscillator, etc.). The signal module adjust characteristics of a provided signal, or generate a new signal with the desired characteristics.
Any quantity of signal modules may be utilized within a device (e.g., probe card, test unit, memory device, etc.). The signal module may produce signals for any quantity of devices (e.g., memory devices, etc.) or corresponding conductors (e.g., pad, etc.). The signal module may coupled to and utilize any suitable quantity of channels of a test system or other signal source. The test system may be implemented by any conventional or other testing system (e.g., ATE, etc.) for testing of any suitable memory or other devices, and may produce any types of pulses or signals. Alternatively, any quantity of signal modules may be employed by the test system at any desired locations (e.g., to form a new test system as an embodiment of the present invention).
The memory devices may be of any quantity or type, may be implemented by any conventional or other memory devices (e.g., PC memory devices, etc.), and may include any quantity of pads and memory cells at any desired locations. Alternatively, any quantity of signal modules may be employed by the memory devices at any desired locations (e.g., to form a new memory device as an embodiment of the present invention).
The probe card may include any quantity of any conventional or other probe card or interface components or devices (e.g., contact sets, conductors, etc.) to access the memory devices. Any quantity of signal modules may be disposed on the probe card at any desired locations (e.g., to form a new probe card as an embodiment of the present invention). The pads, contacts and lines may be of any quantity, size or shape, may be disposed in any suitable location or arrangement, and may be implemented by any conventional or other conductors. The wafer may include any quantity of memory or other devices at any suitable locations. The memory cells may employ any suitable phase change material with varying electrical or other properties to determine a logic state.
The signal module may be implemented by any quantity of any conventional or other circuitry, units or components (e.g., transistors, capacitors, digital signal processor, etc.). The transistors may be implemented by any quantity of any type of any conventional or other switching device (e.g., n or p channel transistors, MOSFET, BJT, etc.). The capacitor may be of any quantity, and may be implemented by any conventional or other devices with a capacitance characteristic (e.g., capacitor, etc.). The transistors and capacitor may include any suitable characteristic values (e.g., resistance, capacitance, etc.) to produce a desired signal. Further, additional circuit components may be utilized to provide desired characteristics (e.g., capacitors, resistors or other circuit components may be provided to attain a desired time constant, etc.). The relay may be implemented by any quantity of any conventional or other relay or switching device (e.g., electrical or mechanical relay or switch, etc.).
The transistors may be controlled collectively in any fashion to control signal characteristics (e.g., provide symmetrical characteristics). Alternatively, the transistors may be controlled individually in any fashion to control individual signal characteristics (e.g., provide symmetrical or asymmetrical signal characteristics, etc.).
The timing diagrams illustrated in the drawings represent example timings for the input and output signals. The signal module may provide any suitable timing to produce signals with any desired characteristics (e.g., leading and trailing edge ramps of any suitable duration, flat, undulating or pointed apex, etc.). The present invention embodiments may alternatively be implemented by any type of hardware and/or other processing circuitry. The processes described above and illustrated in the flow chart may be modified in any manner that accomplishes the functions described herein. In addition, the functions in the flow chart or description may be performed in any order that accomplishes a desired operation.
The present invention embodiments may be utilized for any suitable applications to provide desired signals where a signal source provides incompatible signals for an intended device (e.g., memory test and operation, communications, device or other interfaces, etc.). Further, the present invention embodiments may be utilized for testing of combinations of devices, where some of the devices are compatible with the signals from a signal source and others of the devices are not responsive to those types of signals (e.g., testing of combinations of phase change (PC) memory devices and other types of memory devices, etc.).
It is to be understood that the terms “leading”, “trailing”, “upward”, “downward”, “low”, “high” and the like are used herein merely to describe points of reference and do not limit the present invention to any particular configuration.
From the foregoing description, it will be appreciated that the invention makes available a novel system and method for modifying signal characteristics, wherein signal characteristics are modified to produce resulting signals compatible for a desired application.
Having described example embodiments of a new and improved system and method for modifying signal characteristics, it is believed that other modifications, variations and changes will be suggested to those skilled in the art in view of the teachings set forth herein. It is therefore to be understood that all such variations, modifications and changes are believed to fall within the scope of the present invention as defined by the appended claims.
