Patent Grant
11626062
The present invention relates to the design of a backplane useful to drive an array of pixels comprising emissive elements at each pixel and to an emissive array fabricated with such a backplane. More particularly, the present invention relates to a backplane designed such that it can modulate an array of emissive pixel elements in a manner that mitigates visual flashing and other human vision related artifacts that may be distracting to a human observer.
Emissive displays have proved useful for a variety of applications. For example, plasma display panels (PDPs) were at one time the leading flat panel display technology. More recently, applications that are not display oriented have been postulated, including use as a pixilated emissive device in an additive manufacturing device and use as a component within a vehicular illumination system, such as a headlamp, for automotive applications.
Most recently, emissive display system developers have demonstrated emissive displays based on backplanes driving small LEDs with a pitch between adjacent pixels of 17 micrometers (hereafter microns or m) or less. For applications requiring higher brightness and fewer individual light sources the small LEDs may be made larger although still small—on the order of 40 to 50 microns. The sizes stated are not limiting on this specification. These small LEDs are commonly termed microLEDs or LEDs. LEDs take advantage of the band gap characteristic of semiconductors in which use of a suitable voltage to drive the LED will cause electrons within the LED to combine with electron holes, resulting in the release of energy in the form of photons, a feature referred to as electroluminescence. Those of skill in the art will recognize that semiconductors suitable for LED components may include trace amounts of dopant material to facilitate the formation of electron holes. Organic light emitting diodes or OLEDs are another example of a class of emissive devices.
The choice of semiconductor materials to form an LED will vary by application. In some applications for visual displays one monochrome color may be desirable, resulting in the use of a single semiconductor material for the LEDs of all pixels. Some LEDs provide white light by using blue light to illuminate a phosphor material or quantum dot material suitable to provide green and red light, which, when combined with the blue light, is perceived as white in color. In other applications, a full range of colors may be required, which will result in a requirement for three or more semiconductor materials configured to radiate, for example, red, green and blue or combinations thereof. An illumination system based on LEDs may be applied to use in a variety of applications, including motor vehicle lights. The present application deals mainly with illumination applications for moving vehicles.
Human vision exhibits a variety of behaviors under various conditions that needs to be taken into account when designing an array of emissive pixels to provide illumination, such as a headlamp system. A dominant characteristic of human vision is the perception of flicker. The circumstances between illumination from a headlamp and a human observing the illumination are fundamentally uncontrollable. The human observer may be the driver of the vehicle with headlamp affixed thereto or may be in another vehicle.
Flicker also depends on the part of the retina of the human eye on which the illumination falls. Differences between flicker in the central vision (photopic flicker) and flicker in the peripheral vision (scotopic flicker) are well known in the art. Other differences arise from differences of age or sex, and often simply from the random nature of all human sensory perceptions across a broad sample of people.
Flicker is often thought of through the absence of perceived flicker, which occurs at or above the flicker fusion frequency. Flicker fusion frequency is commonly defined as the frequency at or above which an intermittent light source is perceived as a steady light source by an average human observer. The flicker fusion frequency is referred to by various other names, such a flicker fusion threshold, each of which clearly refers to the same aspect of human vision. Applicant refers interested parties to the Wikipedia article Flicker Fusion Threshold for further information.
Another feature of human vision is a reaction to spatial frequencies in the illumination beam. The illumination beam is formed by a rectilinear array of emissive devices that can, under circumstances, form a beam shaped as a grating similar to a Ronchi grating used for various applications in optics. The contrast between the dark and bright stripes of such a beam would be naturally higher at night.
Another artifact commonly seen in pulse width modulated display devices is called dynamic false contours. Dynamic false contours arise when an image or gray scale ramp moves across a display in a direction that, in the case of the ramp, aligns with the ramp. The perception is that in areas of nearly identical gray scale values, the time difference between the two gray scale areas appears to develop a line between the two areas. This arises out of human vision because human vision does not operate according to the time frame intervals specified for pulse width modulation and may integrate across multiple time intervals.
The use of optical homogenization may mitigate all of these effects to a degree, but there is no certitude that individual headlamp designs will homogenize the entire beam. Therefore, it is important to assume that the output will not be homogenized when projected.
Because of the unpredictable nature of the interaction between the illumination beam and a human observer for the reasons cited, it is a goal of the present invention to obviate unfavorable interactions by eliminating as many causes of the formation of the preceding vision artifacts as possible through careful selection of modulation patterns for the array of emissive pixels. All potential variations are included within the scope of the present invention.
The present invention pertains to a backplane comprising pixel drive circuits operative to deliver a modulated current to a plurality of emissive elements mounted thereon. More particularly, it pertains to a backplane suitable for use as part of a headlamp illumination system that provides selection mechanisms that mitigate the effects of pulse width modulation induced flashing that would otherwise affect human vision.
One aspect of the present invention is the use of one or more addressing means simultaneously that randomize to a degree the on and off states of adjacent pixels in an array of emissive pixel elements. The use of addressing means rather than the manipulation of on and off states of individual emitters offers advantages of simplicity. One goal of simplifications to permit the controller of the array of emissive pixels to be integrated directly into the backplane driving the array of emissive pixels without excessive computational overhead.
Wire bond pad block 102L receives emissive pixel state data and control signals and moves these signals to control block 103. Control block 103 receives the emissive pixel state data and routes the data to lower column data register array 104L for even columns and to upper column data register 104U for odd columns. In one embodiment an odd column data register and an even column data register are positioned on the same side of a pixel drive circuit array. Row address information is routed to odd row decoder left 105L, operative to select a row comprising pixel drive elements for odd numbered columns, and to even row decoder right 105R, operative to select a row comprising pixel drive elements for even numbered columns.
The use of the term row decoder is not used uniformly in the art. In this instance it means a collection of circuits—one circuit for each row associated with the collection—that receives a signal from a row-select originating circuit at the periphery of the backplane that designates which row is to actively receive data from the column drivers on the columns that are a part of that bank as defined herein. The circuit associated with the selected row releases a signal through a word line driver that pulls the word line high so that the memory cells controlled by the word line receive the data loaded on the column registers associated with the column on which the memory element is found. The exact form the circuits may take varies for a number of reasons, but all are considered to be encompassed within the scope of the word row decoder in this application.
Horizontal divisions are envisioned. A mixture of horizontal and vertical divisions is envisioned. In one example, pixel array 101 is divided horizontally near its midpoint top to bottom, as shown by line D1, and is divided vertically near its midpoint side to side, as shown by line D3. Row drivers are configured appropriately.
In one embodiment, the value of Op Code line 112 determines whether data received on parallel data signal lines 115 is address information indicating the row to which data is to be loaded or data to be loaded to a row. In one embodiment the row address information acts as header, appearing first in a time ordered sequence, to be followed by data for that row. In the context of the present application, the word “address” is most often a noun used to convey the location of the row to be written. The location may be conveyed as an offset from the location (address) of a baseline row or it may be an absolute location of the row to be written. This is similar to the manner in which a Random-Access Memory device, such as an SRAM, is written or read. The use of column addressing, also used in Random-Access Memory devices, may be envisioned, but other mechanisms, such as a shift register, are also envisioned. Use of a shift register to enable the writing of data to rows of the array is also envisioned.
In one embodiment, a separate test code may be asserted as an Op Code on a second line 112 which places the backplane in a test mode that may test the row identified over data signal lines 115. The duration of the test code is normally the duration of a least significant bit (sb), although other durations are feasible.
In the case where multiple row decoders operate separately from one another, using modulation sequences that differ to varying degrees, an additional Op Code signal to initiate a test mode for each separate row decoder circuit may be required. In some cases, the different row decoders may each control segments of the same set of rows.
Row decoder left 105L for odd numbered columns is configured to pull the word line high for pixel drive circuits positioned in odd numbered columns of the decoded row, and row decoder right 105R is configured to pull the word line high for pixel drive circuits positioned in even numbered columns of the decoded row. In the case of row decoder left 105L, pulling the word line high for a row will cause data stored in column register array 104U to be transferred to memory circuits (not shown) in the pixel drive circuits found in the odd numbered columns of that row. In the case of row decoder 105R, pulling the word line high for a row will cause data stored in column register array 104L to be transferred to memory circuits (not shown) in the pixel drive circuits found in the even numbered columns of the decoded row. The row to be decoded by row decoder 105L is completely independent of the row to be decoded by row decoder 105R.
This permits data loaded on the column registers to be loaded onto a first row selected by row decoder 105L for odd numbered columns and a second row selected by row decoder 105R for even numbered columns. The rows selected by row decoder 105L and by row decoder 105R are not constrained in implementation and may be randomly selected or selected to implement a specific modulation scheme based on different starting points on the display. One may be random and the other not random. The implemented modulation sequences may differ from each other as well.
The depiction of left and right side row decoder circuits and upper and lower wire bond pad circuits is purely for ease of reference and is not limiting upon the present invention. The depiction of separate column data register for even columns and odd columns is for ease of reference and is not limiting upon the present invention.
Static voltage section 155a provides a set of static voltages required to operate the array of pixel drive circuits, the voltages comprising VDDAR, VSS, upper drive voltage V_H and cathode return voltage V_L loaded onto static voltage distribution bus 156.
Static voltage distribution bus 156 distributes VDDAR, V_H, VSS and V_L to the pixel drive circuits of a first row over conductor 159a and to the pixel drive circuits of a second row over conductor 159b, wherein each of conductors 159a and 159b comprises at least one separate conductor for each supplied static voltage. In some designs, a static voltage conductor may be shared by two or more rows.
Signal voltage control section 155b delivers control signals required to operate the array of pixel drive circuits, such as word line (WLINE) high for the selected row, over bus 157a for odd numbered columns and over bus 157b for even numbered columns. Signal voltage control section 155b delivers signals to signal voltage distribution bus 157a, which in turn delivers the signals to the pixel drive circuits in odd numbered columns of a first row over WLINE 160a and to the pixel drive circuits in odd numbered columns of a second row over WLINE 160b. Signal voltage control section 155b delivers signals to signal voltage distribution bus 157b, which in turn delivers the signals to the pixel drive circuits in even number columns of a first row over WLINE 165a and to the pixel drive circuits in even number columns of a second row over WLINE 165b. Signal voltage distribution bus 157a and 157b each may comprise a plurality of conductors such that each control signal is delivered independently of other control signals. The row on which WLINE is to be held high is selected by row decoder circuits 167a and 167b for pixel drive circuits on odd numbered columns and 168a and 168b for pixel drive circuits on even numbered columns.
In one embodiment, voltage distribution busses 157a and 157b also distribute a global or semiglobal signal to each pixel drive circuit to control a non-data modulation FET (not shown) operative to act as a dimming control unit independent of the data state of the SRAM memory cell located within each pixel drive circuit.
Data memory and logic control section 155c performs several functions. It may, for example, process modulation data received in a standard 8-bit or 12-bit format into a form usable to pulse-width modulate a display. A first function is to determine a row for data to be written to and a second function is to load the data to be written onto that row. Data memory and logic control section 155c loads image data onto the column drivers (not shown) for each odd numbered column over bus 169 and for each even numbered column over bus 170. Conductors 161a and 161b represent a first pair of complementary bit lines for odd numbered columns and conductor 163a and 163b represent a second pair of complementary bit lines for odd numbered columns. Conductors 162a and 162b represent a first pair of complementary bit lines for even numbered columns and conductors 164a and 164b represent a second pair of complementary bit lines for odd numbered columns. Each of said pair of complementary bit lines are operative to transfer data from the column drivers (not shown) to the memory cell of each pixel driver circuit in either and even column or an odd column of the selected row, as appropriate. Data memory and logic control section 155c loads the selected address information for odd numbered columns onto address data bus 158a, which acts to select the correct row decoder circuit among row decoder circuits 167a and 167b both positioned on address data bus 158a. Data memory and logic control sections 155c loads the selected address information for even numbered columns onto address data bus 158b to select the correct row decoder circuit among row decoder circuits 168a and 168b, both positioned on address data bus 158b.
For clarity in this application, the term bank or bank of columns is used to describe an organized set of columns such the column formed by pixel drive circuits 151a and 151b and the column formed by pixel drive circuits 153a and 153b. The organizing point is that pixel drive circuit 151a and pixel drive circuit 153a both are operated by WLINE 160a and pixel drive circuit 151b and pixel drive circuit 153b are both operated by WLINE 160b. Pixel drive circuits on the same row in different columns that are operated by the same word line (WLINE) are in the same bank.
For a second point of clarity in this application, the term group refers to a contiguous block of columns that together form a pattern that is repeated across at least a division of the display if the array of emissive elements is divided into a plurality of divisions as previously explained. In the present example, the column formed by pixel drive circuits 151a and 151b together with the column formed by pixel drive circuits 152a and 152b form a pattern of two columns wherein the first member (pixel drive circuits 151a and 151b) are operated by WLINE 160a and WLINE 160b respectively and the second member (pixel drive circuits 152a and 152b) are operated by WLINE 165a and WLINE 165b respectively. This pattern is repeated across the group.
SRAM memory cell 201 is connected to word line (WLINE) 202 by conductors 227 and 228. Complementary data lines (BPOS) 203 and (BNEG) 202 connect to SRAM memory cell 201 by conductors 206 and 207 respectively. When WLINE 202 is pulled high, pass transistors in the memory cell allow new data to be stored in the memory cell. Data output SNEG of SRAM 201 is asserted over conductor 209 onto the gate of data modulation FET 230, also referred to as a data modulation element. Other configurations of a data modulation element are known. For example, if the dimming function of non-data modulation FET 225 is not required, then it could be repurposed as a data modulation FET and data modulation FET 230 could be eliminated. Operation of the 6T SRAM memory is explained in detail in
FETs 210, 215, 220, 225, and 230 form a circuit operative to deliver a pulse-width modulated current waveform to emissive device 235 driven by the pulse width modulated waveform at required voltage and current levels. Reference current FET 210 and bias FET 220 form a reference current circuit operative to provide a reference current to the gate of current source FET 215 at a required voltage. Reference current FET 210 sets the reference current IREF and bias FET 220 sets the voltage for the reference current on conductors 214 and 216. Bias FET 220 is a large L FET designed to operate as a variable resister based on a bias voltage VBIAS applied to its gate over conductor 218. In one embodiment, VBIAS is set externally and, in one embodiment, is supplied to all pixel circuits. In one embodiment the gate of bias FET 220 is connected to VSS. The source of bias FET 220 is connected to conductor 219 by conductor 217. Conductor 219 is connected to voltage VSS. In one embodiment, the stable reference current asserted onto conductor 214 is supplied to a plurality of pixel drive circuits. In one embodiment, the stable reference current is asserted onto the gate of its own current source FET 215 and onto the gates of current source FETs forming part of a block of pixels.
Current source FET 215 is operative to receive a stable reference current at its gate over conductor 214 and mirror that current. The source of current source FET 215 is connected over conductor 213 to conductor 211, which supplies voltage V_H. The drain of current source FET 215 asserts a stable current over conductor 221, wherein the stable current may differ from the reference current. To achieve the desired current at the drain of FET current source 215, current source FET 215 must be designed to deliver that current. Current source FET 215 is preferably designed so that the relationship between the length (L) and the width (W) is selected in order to achieve the desired current at its drain. The desired current asserted on the drain of current source FET 215 may differ from the reference current received on the gate of current source FET 215, depending on the design W/L ratio of current source FET 215. Different W/L designs may be required for pixels of different colors.
FET 225 acts as a non-data modulation element on the output of current source FET 215. The gate of non-data modulation FET 225 receives a signal l_off from an external modulation element. The source of non-data modulation FET 225 is connected to conductor 211 by conductor 233, which asserts V_H onto the source of non-data modulation FET 225. If l_off is low then non-data modulation FET 225 asserts V_H minus a small threshold voltage onto its drain, whereupon the substantially V_H voltage acts upon the gate of current source FET 215 to take current source FET 215 out of saturation mode. This results in current source FET 215 no longer mirroring the current asserted on its gate, This enables signal l_off to act as a form of non-data modulation control signal. The action of l_off is to raise or lower the overall duty cycle of the modulation output of pixel circuit 100, thereby raising or lowering its perceived intensity without regard for the data state of the SRAM cell.
Data modulation FET 230 comprises a data modulation section suitable to respond to pulse-width modulation waveforms used to create gray scale modulation. The need to perform this function is well known in the art. The output of the drain of current source FET 215 is asserted onto the source of data modulation FET 230 over conductor 221. The gate of data modulation FET 230 is connected to output SNEG of SRAM 201 over conductor 209. When the data state of SRAM 201 is on, then SNEG is low and acts on the gate of data modulation FET 230 to enable it to assert the current asserted onto its source over conductor 221 onto its drain over conductor 226.
The output of the drain of data modulation FET 230 is asserted onto conductor 226. The output comprises a pulse width modulated signal operative to create a gray scale modulation at a desired intensity. The output is connected over conductor 226 to the anode of emissive device 235. The cathode of emissive device 235 is connected by terminal 236 to V_L asserted onto conductor 237. The voltage level of V_L is lower than V_H and may be lower than VSS and may be a negative voltage. Emissive device 235 may be an LED, LED or OLED device or some other emissive device such as a laser diode.
In order to avoid aliasing caused by the operating rate of 1_off should create pulse intervals that is shorter than the shortest pulse duration imposed on S_neg by a substantial margin, perhaps a factor of 10 to 1 in order to avoid aliasing. In some non-display applications, the issue of aliasing may be less important. In that case the pulse interval of l_off may correspond to tens or more of Isb internals. In one embodiment operation of l_off is synchronized with operation of S_neg.
SRAM circuit 250 is connected to VDDAR by conductor 265 and to VSS by conductor 266. VDDAR denotes the VDD for the array. It is common practice to use lower voltage transistors for periphery circuits such as the I/O circuits and control logic of a backplane for a variety of reasons, including the reduction of EMI and the reduced circuit size that this makes possible.
The six-transistor SRAM cell is desired in CMOS type design and manufacturing since it involves the least amount of detailed circuit design and process knowledge and is the safest with respect to noise and other effects that may be hard to estimate before silicon is available. In addition, current processes are dense enough to allow large static RAM arrays. These types of storage elements are therefore desirable in the design and manufacture of liquid crystal on silicon display devices as described herein. However, other types of static RAM cells are contemplated by the present invention, such as a four transistor RAM cell using a NOR gate, as well as using dynamic RAM cells rather than static RAM cells.
The convention in looking at the outputs of an SRAM is to term the outputs as complementary signals SPOS and SNEG. The output of memory cell 250 connects the gate of transistors 263 and 261 over conductor 264 to circuitry (not shown) operative to receive the output of memory cell 250. By convention this side of the SRAM is normally referred as S_neg or SNEG. The gates of transistors 262 and 260 are normally referred to as SPOS. Either side can be used provided circuitry, such as an inverter, is added where necessary to ensure the proper function of the transistor receiving the output data state of the memory cell.
Source 323 of reference current FET 322 is connected to voltage V_H asserted on conductor 343, wherein V_H is an external global voltage that is separate from other external global voltages such as VDDAR and VSS. Reference current FET 322 is operated in diode mode wherein gate 347 and drain 324 are connected by electrical conductor 325 and conductor 346. Gate 347 and drain 324 of reference current FET 322 are connected to gate 321 of current source FET 326 as described herein. Conductor 325 and conductor 346 are electrically connected to gate 321 of current source FET 326 over conductor 352. Reference current FET 322 sets the reference current for the current mirror circuit.
N-channel bias FET 330 is a large L FET that acts as a variable resistor when operated in saturation. Drain 331 of bias FET 330 is connected to gate 347 and drain 324 of reference current FET 322, all of which are connected to gate 321 of current source FET 326 as described previously. Source 332 of large L n-channel bias FET 330 is connected to VSS over conductor 333. Gate 348 of bias FET 330 is connected to bias voltage VBIAS over conductor 329. Pixel drive circuits with different color emissive elements may have different VBIAS requirements so a plurality of different VBIAS voltages applied over independent circuits is conceived for pixels of different colors.
Together reference current FET 322 and bias FET 330 deliver a stable reference current at a fixed voltage to gate 321 of current source FET 326. The fixed voltage is determined by voltage VBIAS asserted on gate 348 of bias FET 330.
Source 327 of current source 326 is connected to conductor 343 which supplies voltage V_H. This places source 323 of reference current FET 322 and source 327 of current source FET 326 at the same potential and electrically connected through conductor 343. Drain 328 of current source FET 326 delivers a required voltage and current. The voltage and current output of drain 328 of current source FET 326 is delivered to source 335 of data modulation FET 334 over conductor 344.
As is well known in the art, current source FET 326 may be designed to deliver a stable current over drain 328 that is greater or lower than the reference current delivered to gate 321 of current source FET 326. Because current mirror FETs 322 and 330 are unaffected by the data state of the associated memory device (not shown), in one embodiment the output of the reference current FET of one pixel may act as the reference current FET for a nearby pixel provided the voltage of the reference current is also compatible with the emissive element on the nearby pixel. Because of the aforementioned statement regarding current source FET 326, it is clear that different currents may be derived from a single reference current. The nearby pixel sharing a current mirror may therefore receive a different current and have an associated emissive element of a different color type provided a compatible voltage is delivered. A mechanism for creating different current outputs is a change to the W/L aspect ratio of current source FET 326.
The use of current source circuits other than a current mirror circuit is conceived of. One such circuit is disclosed in
P-channel non-data modulation FET 338 is placed adjacent and electrically parallel to current source FET 326. When gate 350 of non-data modulation FET 338 is held low source 339 is connected to drain 340, effectively connecting V_H from conductor 343 onto conductor 352 minus a small threshold voltage. This places gate 321 of current source FET 326 at a voltage near voltage V_H on source 327, which takes current source FET 326 out of saturation and effectively shuts it off. This provides a modulation capability independent of the data state of the memory cell.
Non-data modulation FET 338 may be turned “on” or “off” by a number of different modulation requirements. In one embodiment, a relatively high frequency rectangular waveform of varying duty cycle may be used to lower the apparent intensity of an emissive element. In another embodiment, a waveform is imposed on non-data modulation FET 338 that serves to cause on state emissive elements to emit light for a time equivalent to a desired modulation duration. Other modulations are envisioned. Light is emitted by emissive element 355 only when data modulation FET 334 and non-data modulation FET 338 are both in an on state.
Data modulation FET 334 forms a data modulation section. Data modulation FET 334 is turned on or off in response to the data state stored in a memory cell such as memory cell 250 of
The output (voltage and current) of data modulation FET 334 onto drain 336 is connected to conductor 345. The output comprises pulse-width modulated current and voltage, suitable to be applied to anode 342 of emissive element 355. The cathode of emissive element 355 is connected to voltage supply V_L wherein V_L is lower than V_H and may be lower than VSS or may be a negative voltage. The level of V_L is selected so that the difference between the voltage asserted on the anode of emissive element 355 and the voltage asserted on the cathode of emissive element 355 is sufficient to cause emissive element 355 to discharge when circuit 300 is an on state.
A general overview of the modulation method, hereafter referred to as MegaMod, is that it relies on differing spacings between rows that receive data directed to those rows by write pointers to create differing modulation durations for those rows that are determined by the spacing between the rows.
As background, Applicant reviews the patented material of the referenced patents by example. In the example of
The direction and magnitude of motion for subsequent applications of the write pointer sequence formed by A1, A2, A3 and A4 is down the rows with an offset of one row from the row previously pointed to by the preceding instance of the write pointer sequence. For example, the first instance of A1 is found writing to row 1 during time unit 1, while the second instance of A1 is found writing to row 2 during time unit 5, and the third instance of A1 is found writing to row 3 during time unit 9, and the fourth instance of A1 is found writing to row 4 during time unit 13. Similar observations for time interval and row spacing can be made for write pointers A2, A3 and A4.
The creation of pulse width modulation occurs because a first write pointer directs data to a first row which receives data directed to it by a second write pointer that is different to the first write pointer. Because the second write pointer is located a number of rows away from the first write pointer at the time the row is written and all intervening rows must also be written in order by the second write pointer, the time that the row data is unchanged is proportional to the number of rows between the first write pointer and the second write pointer. As a first example, write pointer A2 directs data to row 2 during time unit 2. The next write pointer to direct data to row 2 is write pointer A1 during time unit 5. This effectively means that the interval during which the data on row 2 is presented is 3 time units in duration.
As a second example, write pointer A3 directs data to row 4 during time unit 3. The next write pointer to direct data to row 4 is write pointer A2 during time unit 10. This is equivalent to 7 time units.
Row 1 and row 2 are on adjacent rows while row 2 and row 4 have intervening row 3 to which nothing is written. The modulation duration for A2 and A1 is 3 time units while the modulation duration for A3 and A2 is 7 time units. The modulation duration for A4 and A3 is 15 time units. In a pure binary weighted sequence of the three lowest least significant bits, the relative weighting would be 1, 2 4. In this example using row spacings of 1 row displacement, 2 rows displacement and 4 rows displacement, the relative ratios become 1, 2⅓, 5. Stated differently they become 0.8, 1.86, 4 if the temporal weightings are based on the 4 row displacement being a binary weighting of 4 (22.)
The relationship between row spacing and pulse width duration can also be made more linear through the use of stall intervals (not shown) between temporally adjacent time intervals, wherein no data is written during stall intervals. Stall intervals may also be placed between individual write actions. This can be implemented through actions within control section 155b of
These numbers are sufficiently close to support building a pulse width modulation on this principle. Applicant has previously developed modulation sequences able to represent 2000 gray levels in liquid crystal devices using the basic techniques described here.
The even columns and odd columns may also be described as interleaved or interlaced. Interlaced is a term of art in cathode ray tube based displays, that signifies that the image being displayed is displayed in two parts, wherein the first part and the second part are both needed to have a complete image. The two images are offset so that the lines of the first image fall between the lines of the second image.
The write pointer pattern of Odd Columns beginning at row 1 in the first time interval is duplicated in Even Columns beginning at row 13. Because the height of the modulation sequence is approximately the same height as the rows of the display, the write pointer pattern will begin to wrap around to the top row of the array in subsequent time intervals once an individual write pointer has reached the last line of the array. The start points for write pointer A1 and write pointer B1 are approximately 180 degrees out of phase since the modulation height is substantially the same as the number of rows in the array.
In the second time interval each write pointer of the odd columns and of the even columns is displaced one row down the array. Write pointer A1 now directs data to row 2, write pointer A2 to row 3, write pointer A3 to row 5 and so forth. Write pointer B5 now directs data to row 5, write pointer B1 to row 14. Write pointer B3 to row 15 and so forth.
Write pointer A1 in the second time interval directs data to row 2 in odd columns, which previously received data in the first time interval directed to it by write pointer A2. In like manner, write pointer B1 directs data to row 14 in the second time interval which previously received data in the first time interval directed to it by write pointer B2. This established that the write pointer sequence A1-A5 operating on odd columns and the write pointer sequence B1-B5 operating on even columns provide pulse width modulation in the manner described for
The concept of interleaved columns can be expanded further.
In this example, the write pointer sequences are all identically defined but have different start points within the sequence. Considering the first time interval found in
Reviewing the second time interval found in
The write pointer sequence operates as previously described. Write pointer sequence A1-A5 and write pointer sequence B1-B5 maintain the same relative spacing while the sequence is successively applied by moving the sequence down the array by one row at each successive application in a new time interval. When a write pointer reaches the last row of the array, it advances to the first row of the array in which is the beginning of the time interval after the next time interval. For example, write pointer B4 directs data to row 24 during time interval 5 and then directs data to row 1 during time interval 7. The wrap around moves a write pointer from the last write pointer in a first time interval to the first write pointer in the time interval after the next immediate time interval (the second succeeding time interval).
The spacing between rows is determined as shown in the following table. The column for write pointer start is the write pointer that establishes a modulation state and the column for write pointer end is the write pointer that ends that modulation state by initiating another modulation state. The later modulation state may be the same as the earlier modulation state or may be different. If the write pointers propagate up the array rather than down the array, then the start and end write pointers are reversed.
The resulting time durations are not completely linear with respect to the row separations because the point in time within a time interval at which the second action occurs is not exactly at the same point in the time interval, as was previously discussed with regard to
In practice the results of this modulation method may be somewhat less linear than is obvious from the foregoing example. The number of time intervals cited does not account for the position each write pointer occupies within the time interval. The more write pointers there are in a modulation sequence the closer the time intervals for each row will be to an ideal time interval.
One issue that arises in developing a modulation is how to implement a modulation of a duration to create a least significant bit modulation in those instances where the available bandwidth for delivering modulation does not support that short a time interval. Defining based on the minimum duration LSB may result in visual artifacts due to unwanted increases in the duration of higher order bits.
In this example, the upper bits are divided into two instances, each of approximately half the needed duration for the upper bits. To implement this, data segment A2-A1 of four time intervals duration is paired with data segment A9-A8 of four time interval duration, thereby creating a total of 8 time intervals duration. Pairing for this example means that the data presented on the two member of the pair are the same, i.e., if the first segment is high then the second segment is high. Data segment A3-A2 of two time intervals duration is paired with data segment A10-A9, also of two time intervals duration, creating a total of four time segments duration. Data segment A4-A3 is paired with data segment A11-A10, again for a cumulative modulation duration of 8 time intervals. Data segment A5-A4 and data segment A12-A11 are paired for a cumulative modulation duration of 8 time intervals. Data segment A6-A5 is paired with data segment A13-A12 for a cumulative modulation duration of 2 time intervals. Data segment A7-A6 of four time intervals duration is paired with data segment A1-A13 of 4 time intervals duration, for a total modulation duration of 8 time intervals. Data segment A9-A7 of one time interval duration is not paired with another data segment, and therefore has a modulation duration of one time interval.
The use of four modulation durations of 8 time intervals allows implementation of a thermometer bit modulation scheme as disclosed in the MegaMod patents. The use of thermometer bits that are always populated in a specific order with respect to increasing brightness helps mitigate common pulse width modulation effects such as dynamic false contours. The lesser bits are binary weighted with durations 1, 2, and 4 represented. One of the segments with a duration of 8 may be considered binary weighted, but it is not necessary to choose a particular one in advance.
One issue in the modulation of an array of emissive elements using the techniques described is maintaining the accuracy of the gray scale modulation. The is particularly a problem when the number of rows on the array is relatively small. One approach to this is to operate the system controller for a larger number of rows than are physically present on the array. In order to keep the approach manageable, a number of the row write actions may be directed to phantom rows. At least two different implementations are envisioned.
In a first embodiment, the time required to write to the phantom row is simulated through the use of a no-op (no operation) of the same approximate duration as a row write action. Implementations that can achieve this delay through use of a time delay line have been previously proposed by applicant in U.S. patent application Ser. No. 10/413,649, now U.S. Pat. No. 7,443,374, in
In a second embodiment, at least one dummy row is designed into the array that does not control any emissive devices but that replicates the time required to write a fully functional row by replicating the circuitry of the active rows without the emissive elements. A plurality of dummy rows may be implemented. This dummy row or rows is addressed during the time where a no-op is desired. In FIGS. 7A-9D of the present application, the term no-op for the row to be written to indicates that the addressed row is handled as either a dummy row or as a time delay equivalent to a dummy row. In those instances where a range of virtual rows is associated with a no-op action, each of those rows is the subject of a separate no-op action as described in this paragraph.
The advantage of this approach is that each row write action is placed early in a sequence and is followed by a fixed number of no-op actions. Because the no-op actions change nothing, the time that the array stays in its current data state is determined by the number and duration of those no-op actions. In a simple case where the array is written top to bottom or bottom to top, this effectively extends the time required to write the entire array and thus the duration of the output of each emissive element placed in an on state, The virtual rows also represent the temporal order in which data is written to the actual rows and in which the no-op actions are executed when data is not written to an actual row.
One of the problems with linear row progression modulation schemes where the modulation comprises a single write pointer that progresses from the top row to the bottom row or from the bottom row to the top row is that any structure in the modulation data becomes readily apparent. This type of modulation has been used successfully in analog displays, such as flat panel displays that rely on analog modulation of a liquid crystal material. However, binary weighted modulation of liquid crystal materials or of emissive devices is another matter. Applicant's use of the modulation techniques described in the MegaMod patents has overcome this limitation but this approach is more complex to implement than other methods in that it requires the use of row addressing circuitry and also means in a controller circuit to take desired intensity levels for each emissive element and create a modulation file comprising multiple write pointers that implements that desired intensity level.
In
The nature of a random mapping is illustrated by
In comparing
Bandwidth limitations occur in several different manners. One limitation exists in the ability to transfer information from external sources to the microdisplay/controller system described in paragraphs 1A-1B. A second limitation exists in the speed with which the controller can receive the information and convert it to the needed format for further action. A third limitation exists in the speed with which the information in the desired format can be applied to the backplane forming part of the array of emissive devices. This application recognizes these requirements and addresses a set of them.
A top level inspection of the left hand columns under the header Bit Plane Table×1 Yielding 1024 bits (hereafter the ×1 columns) reveals a comprehensive modulation sequence that represents a 10 bit gray scale sequence is presented. The modulation sequence comprises 14 modulation steps that combine seven binary weighted bit planes lsb0-lsb5 with seven equally weighted thermometer bits thm0-thm6. The equally weighting thermometer bits are fully disclosed in the MegaMod patents, that are incorporated herein by reference. As noted earlier, the thermometer bits may be unequally weighted if needed to accomplish the desired modulation.
Accomplishing this in one sequence may be preferred in some instances, but it is also important to consider the overall bandwidth requirements to do so. The assumption is made that alternative modulation sequences may be used instead of those specifically disclosed below that otherwise comply with the principles of the modulation sequences disclosed herein.
The right hand columns under the header Bit Plane Table ×4 Yielding 1024 bits (hereafter the ×4 columns) disclose an alternative approach to the required resolution. The first consideration is that the left hand ×1 columns results at the required modulation at some bandwidth requirement. While it is possible to operate the sequence at 1× it is also understood that this may necessary to be implemented at multiples of the proposed values to eliminate all the visual artifacts.
The approach disclosed in the right hand ×4 columns reduces some of the bandwidth requirement by reducing the number of lsb segments from 6 to 4. The eliminated lsb segments are the lowest order bits representing 1 and 2 bit weightings, capable of representing 0 to 3 in integer terms. The key to recovery of the lost bit weightings is to repurpose the test bit during the intervals during which it is not needed in test mode. In the 4× example, only one test bit is needed during the four repetitions of the modulation sequence. Thus the other three instances of the test bit can be repurposed to convey image data. Three lsb instances can convey weightings of 0, 1, 2 or 3 as indicated in the table below.
Note that for a bit weighting of 1 or 2, the position in the four repetitions of the ×4 columns sequence may vary. During the test sequence, the data value of the test bit is always set to 0 and therefore does not affect the resulting gray scale sequence.
In an instance where a test bit is not required during operation of the array and is therefore not a part of the sequence, it would be possible to operate the array in a manner similar to the previously described manner with the state alternatives now ranging from 0 of 4 to 4 of 4. This will increase the bit depth by one bit.
Those of skill in the art will recognize that various combinations of the embodiments disclosed herein may be combined to provide an effective modulation scramble device. For example, the even and odd column structure of
This present application claims the benefits of U.S. Provisional Patent Application No. 62/977,897, filed on Feb. 18, 2020.
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| Number | Date | Country | |
|---|---|---|---|
| 20210256901 A1 | Aug 2021 | US |
| Number | Date | Country | |
|---|---|---|---|
| 62977897 | Feb 2020 | US |
