The high-density digital-versatile disc (HD-DVD) uses an eight to twelve modulation (ETM) technique. That is, 8-bit symbols (i.e., user bytes or data words) are converted into 12-bit code words that are stored on the disc.
Taking HD-DVD encoding for example, this modulation table requires 256 (8-bit)×3 (12-bit) entries.
The bit asterisk “*” in the code conversion table
The bit sharp “#” in the conversion table
For HD-DVD decoding, the demodulation table requires 355 (12-bit)×3 (8-bit) entries.
However, the modulation table shown in
One of the objectives of this disclosure is therefore to provide a method and apparatus for simplifying the modulation table and the demodulation table.
According to the claimed disclosure, a method for converting an input code into an output code includes: determining a plurality of input code subsets of the input code; converting the input code subsets into a plurality of output code subsets, respectively; and merging the output code subsets to generate the output code. Also, the step of converting the input code subsets may modulate the input code subsets into the output code subsets, or demodulates the input code subsets into the output code subsets.
According to the claimed disclosure, a system for converting an input code into an output code includes: a splitter, for determining a plurality of input code subsets of the input code; a mapper, coupled to the splitter, for converting the input code subsets into a plurality of output code subsets, respectively; and a merger, coupled to the mapper, for merging the output code subsets to generate the output code.
The mapper modulates the input code subsets into the output code subsets or demodulates the input code subsets into the output code subsets.
These and other objectives of the present disclosure will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
In other words, the method for modulating and demodulating according to the preferred embodiment of this disclosure may be shown according to
b) is another embodiment of
Also, in
When steps 601, 603, 605, and 607 fail to generate the output code sub sets, then step 609 directly modulates the input code into the output code using an exception rule. Additionally, step 611 is executed to reference a special rule to add a control bit (#) or a merging bit (*) to the output code according to at least one of the input code subsets and the output code subsets, wherein the control bit is utilized for controlling a DC value, and the merging bit is utilized for controlling merging of two output codes. Then, step 613 determines the next state according to at least one of an output code subset and an input code subset.
However, assuming that the same result is obtained, it should be noted that the order of steps 601 through 613 is not limited to that shown in
That is, the value of the output code depends on the input code, and the same output code is generated while the input code being converted utilizing steps 601 through 613, regardless of the order in which the steps 701 through 709 are performed.
In this embodiment, step 601 follows the rules as shown below:
In these rules, IC means input code, and CSx means the state to which the input code corresponds. For instance, CS0 represents a state equal to 0, CS1 represents a state equal to 1, and CS2 represents a state equal to 2. Therefore, the same leading input code subset is converted to different leading output code subset according to different states. For example, if the first four bits in binary format of the leading input code subset are “1111” and the state is 0, then the first six bits in binary format of the leading output code are “000001”. However, if the state is 0, the first six bits of the leading output code sub set are “001001.”
Step 603 follows the rule shown below:
Step 605 follows the rule shown below:
Step 607 follows the rules shown below:
Step 609 in this embodiment is applied to data words of values in hex format 34-35, 48, 49, 4A-4B, 4F, 75, CA, F5, and follows the rules shown below:
Step 611 is used to determine the merging-bit ‘i” and the DC control bit “#” following the rules shown below. It should be noted that, the following examples are used for determining the merging-bit ‘*” and the DC control bit “#” utilizing the input subsets, but it doesn't mean to limit the scope of the present invention. For example, the merging-bit ‘*” and the DC control bit “#” can also be determined according to the output code subsets or the mixing of the input code subsets and the output code subsets.
Step 613 follows the rules shown below to determine the next state. It should be noted that though the next state is determined according to the output code subsets in the following rules, but it doesn't mean to limit the scope of the present invention. The next state can also be determined according to the input code subsets or the mixing of the input code subsets and the output code subsets.
It should be noted that the input code and the output code comply with HD-DVD specification in this embodiment. That is, input code is an 8-bit code, output code is a 12-bit code, and the output code satisfies the bit string rule. The bit string rule dictates that the number of bits with logic value “0” positioned between two bits having a logic value “1” is limited to an amount from one to ten. Also, the input code itself may be converted from a raw data before the steps shown in
Utilizing steps 601 through 613, a simplified modulation table utilized for converting an 8-bit data word to a 12-bit code word is formed, thus the dimensions and complexity of the modulation table are decreased.
Besides, according to another embodiment, the steps 601, 603, 605, 607, 609 and 611 follows the different rules from the rules described above.
The step 601 and 603 follows the rules described below, wherein the value of the input code IC indicates the first four bits of the input code IC in hex format and the value of the output code OC indicates the first six bits of the output code OC in binary format:
Additionally, the step 605 and the step 607 follow the steps described as below, wherein the value of IC indicates the final four bits of a 8-bit code:
Furthermore, step 609 follows the rules described as below:
Additionally, the step 611 follows the rules described as below:
Also, step 709 determines if the input code has an error, that is, if the input code meets a case 3 Z rule, the output code corresponding to the third case is assigned by a symbol Z indicating demodulation error and doesn't care value.
Utilizing steps 701 through 709, the input code is converted to an output code corresponding to the third case (i.e., the case 3 OC shown in
In this embodiment, step 701 follows the rules shown below: The input is in binary format and the output is in hex format
Also, step 703 follows the rules shown below:
Furthermore, step 709 follows the rule shown below:
It should be noted that in the above case 3 Z rule, x could be “0” or “1”.
Step 801 demodulates the input code (i.e., the output code corresponding to the third case) if the input code meets a case 2 equivalence rule. Step 803 directly demodulates the input code that step 801 failed to demodulate to generate an output code by referencing a case 2 exception rule. Step 805 determines if the input code has an error, that is, if the input code meets a case 2 Z rule, the output code corresponding to the second case is assigned by a symbol Z indicating demodulation error and doesn't care value. Assuming the same result is obtained, it should be noted that the order in which steps 801 through 805 is not limited to that shown in
In this embodiment, the step 801 follows the rules shown below:
Step 803 follows the rules shown below:
Step 805 follows the rules shown below:
The step 901 follows the rules shown below:
Step 905 follows the rules shown below, wherein the symbol Z means that the input code has an error:
Step 1007 follows the rules shown below: input is in binary format and the output is in hex format
It should be noted that the input code and the output code comply with HD-DVD specification in this embodiment. That is, input code is a 12-bit code word, output code is an 8-bit data word, and the input code meets the aforementioned bit string rule. Also, the input code may be converted from raw data before the demodulation process starts.
Also, the splitter 1101 can further convert the input code (IC) to the input code N (ICN). The mapper 1103, which is coupled to the splitter, is used for converting the input code subsets into a plurality of output code subsets (OCS), respectively. The merger 1105, which is coupled to the mapper, is used for merging the output code subsets to generate the output code.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the disclosure. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
This application claims the benefit of U.S. Provisional Application No. 60/595,489, filed on Jul. 11, 2005, entitled “System and Method for Modulation and Demodulation Bit Sub-Set Conversion,” and incorporated herein by reference.
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Number | Date | Country | |
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20070008194 A1 | Jan 2007 | US |
Number | Date | Country | |
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60595489 | Jul 2005 | US |