Claims
- 1. A method for converting a program designed to be executed on a computer system employing a first predefined memory order to a program which is executable on a computer system employing a second predefined memory order different from said first predefined memory order, the method comprising the steps of:
- finding all instructions in the program which operate on bytes of data, each of said bytes of data having a byte address, each byte address having two least significant bits;
- operating on the two least significant bits of each byte address using a logic function to thereby generate two complementary bits for each byte address; and
- replacing the two least significant bits of the byte address with two complementary bits to thereby generate a new byte address for each of said bytes of data.
- 2. The method of claim 1 further comprising the step of detecting whether the program is designed to be executed on a computer system employing the first predefined memory order.
- 3. The method of claim 2 further comprising the step of detecting the two least significant bits of each byte address.
- 4. The method of claim 1 wherein the first predefined memory order comprises big endian order and the second predefined memory order comprises little endian order.
- 5. A computer system employing a first predefined memory order which converts and executes programs designed to be executed on computer systems employing a second predefined memory order different from said first predefined memory order, comprising:
- means for finding all instructions in the program which operate on bytes of data, each of said bytes of data having a byte address, each byte address having two least significant bits;
- means for operating on the least two significant bits of each byte address using a logic function to thereby generate two complementary bits for each byte address; and
- means for replacing the least two significant bits of each byte address with the two complementary bits to thereby generate a new byte address for each of said bytes of data.
- 6. The computer system of claim 5 further comprising:
- means for detecting whether the program is designed to be executed on a computer system employing the first predefined memory order; and
- means for detecting the two least significant bits of each byte address.
- 7. The computer system of claim 5 wherein the first predefined memory order comprises big endian order and the second predefined memory order comprises little endian order.
- 8. A computer program-product storage device readable by a computer system, tangibly embodying a computer program-product comprising instructions executable by the computer system to perform method steps for converting a program designed to be executed on a computer system employing a first predefined memory order to a program which is executable on a computer system employing a second predefined memory different from said first predefined memory order, the method comprising the steps of:
- finding all instructions in the program which operate on bytes of data, each of said bytes of data having a byte address, each byte address having two least significant bits;
- operating on the two least significant bits of each byte address using a logic function to thereby generate two complementary bits for each byte address; and
- replacing the two least significant bits of the byte address with two complementary bits to thereby generate a new byte address for each of said bytes of data.
- 9. The computer program-product storage device of claim 8, wherein said method further comprises the step of detecting whether the program is designed to be executed on a computer system employing the first predefined memory order.
- 10. The computer program-product storage device of claim 8, wherein said method further comprises the step of detecting the two least significant bits of each byte address.
- 11. The computer program-product storage device of claim 8, wherein the first predefined memory order comprises big endian order and the second predefined memory order comprises little endian order.
Parent Case Info
This is a continuation of application Ser. No. 08/127,105, filed Sep. 27, 1993, now U.S. Pat. No. 5,392,329; which is a continuation of application Ser. No. 07/564,923, filed Aug. 9, 1990, now abandoned.
US Referenced Citations (10)
Continuations (2)
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Number |
Date |
Country |
Parent |
127105 |
Sep 1993 |
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Parent |
564923 |
Aug 1990 |
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