System and method for optimizing phase locked loop damping coefficient

Abstract

An adjustable oscillator for dynamically optimizing a damping coefficient of a PLL circuit including a gain controlled oscillator circuit and a damping controller. The PLL circuit provides a loop control signal indicative of an error between first and second clock signals and generates a third clock signal which has a frequency which is a clock multiplier times the frequency of the second clock signal. The oscillator circuit has a control input receiving the loop control signal, a gain control input, and an output that provides the third clock signal. The damping controller has an input receiving the clock multiplier and an output providing a gain control signal to the gain control input of the oscillator circuit. The damping controller adjusts gain of the oscillator circuit in response to changes of the clock multiplier to minimize variation of the damping coefficient.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to phase locked loop circuits, and more particularly to a system and method for optimizing a phase locked loop (PLL) damping coefficient which improves spectral purity of a core clock generated by the PLL from a reference clock.

2. Description of the Related Art

Phase locked loop (PLL) circuits are typically used by electronic devices and the like to synchronize one or more clock signals for controlling the various operations of the device. Because operations within an integrated circuit can be performed much faster than operations between integrated circuits, PLL circuits are often used within an integrated circuit to generate an internal clock signal at some multiple of the external clock frequency. In many applications, the internal clock signal is derived from an external clock reference that is provided to the integrated circuit as well as to other components within a system so that inter-system operations are synchronized. For instance, an exemplary bus clock in a computer system operating at 300 megahertz (MHz) may be used to derive an internal microprocessor core clock signal operating at 3 gigahertz (GHz), which represents a tenfold increase in frequency. A clock multiplier N determines the ratio between the bus clock (or external clock) and core clock (or internal clock) frequencies. Some systems are static in which the clock multiplier N is fixed. Other systems are dynamic in which the clock multiplier is adjustable for various purposes, such as changing the mode of operation of the integrated circuit or electronic circuit (e.g., switching between various power modes, such as standby, low-power, hibernation, etc.).

One skilled in the art appreciates that the response characteristics of a conventional PLL are inversely proportional to the square of the clock multiplier N and proportional to the square of the oscillator gain KV. The damping coefficient θ for a PLL circuit is as shown in the following proportion (1): $\begin{array}{cc}\vartheta \propto \sqrt{\frac{1}{N}\times \mathrm{IC}\times \mathrm{KV}\times R^2\times C}& \left(1\right)\end{array}$ where N is the clock multiplier, IC is a charge pump current magnitude, KV is the oscillator gain, and R and C are the resistance and capacitance, respectively, of the RC loop filter components of the PLL. A typical loop filter for a PLL includes a series RC filter having a time constant in accordance with the desired properties of the PLL, which include maximizing locking speed and minimizing jitter. In some embodiments, a small capacitor is provided in parallel with the series RC components, in which case Proportion 1 is modified accordingly. The loop filter generates a loop control signal which is provided to a variable oscillator circuit to control the phase and/or frequency of the internal clock signal. In one specific configuration, the loop filter generates a loop voltage which is employed to modulate the amount of current that is supplied to oscillator cells within a current controlled oscillator (ICO). A greater amount of current results in a faster internal clock and a lesser amount of current results in a slower internal clock.

One skilled in the art also appreciates that to maximize spectral purity, the damping coefficient θ of the PLL should be relatively constant. It has been shown that the ideal damping coefficient value is approximately 0.707. As advances in integrated circuit fabrication techniques have enabled devices to be scaled to less than 100-nanometer channel lengths, it is not uncommon to find requirements for a PLL circuit that support clock multipliers ranging from 1 to 30 or more times a given reference frequency. And it is very common that the clock multiplier is dynamically modified during operation to adjust the operating mode. The damping coefficient of the conventional PLL, however, varies from under damped to over damped in response to changes of the clock multiplier to achieve the desired given operating range. In this manner, the conventional PLL does not provide the desired spectral purity.

One skilled in the art further appreciates that the spectral purity of the clock signals within an integrated circuit, particularly a pipelined device such as a microprocessor, directly impacts operating speed because the internal logic must be designed to operate under worst-case conditions. Accordingly, it is very desirable to improve the spectral purity of present day PLL circuits. For some applications that have a fixed reference clock frequency and a fixed clock multiplier N, a PLL can be configured which achieves an acceptable spectral quality. Conventional PLL circuits are not suitable, however, for applications that dynamically vary the reference frequency and/or the clock multiplier or ratio N since such conventional PLL circuits generate undesirable jitter when N varies which significantly reduces spectral quality. In particular, when jitter due to variation of the damping coefficient θ exists in a PLL, operational circuits must be designed to operate under worst-case conditions. At 2 GHz, for example, one percent jitter in a PLL reduces the amount of work that can be performed during a given clock cycle.

The spectral quality problems must be resolved to maximize efficiency and work performed as operating speed increases. It is desired to improve the spectral quality of PLL circuits employed in modern day circuits including integrated circuits and the like.

SUMMARY OF THE INVENTION

An adjustable oscillator for dynamically optimizing a damping coefficient of a phase locked loop (PLL) circuit according to an embodiment of the present invention includes a gain controlled oscillator circuit and a damping controller. The PLL circuit provides a loop control signal indicative of an error between first and second clock signals and generates a third clock signal which has a frequency which is a clock multiplier times the frequency of the second clock signal. The gain controlled oscillator circuit has a control input receiving the loop control signal, a gain control input, and an output that provides the third clock signal. The damping controller has an input for receiving the clock multiplier and an output providing a gain control signal to the gain control input of the gain controlled oscillator circuit. The damping controller adjusts gain of the gain controlled oscillator circuit in response to changes of the clock multiplier to minimize variation of the damping coefficient.

The gain controlled oscillator circuit may include a variable oscillator circuit and a gain control circuit. In this case, the variable oscillator circuit has a frequency control input and an output providing the third clock signal. The gain control circuit has a first input receiving the loop control signal, a second input receiving the gain control signal, and an output providing a frequency control signal to the frequency control input of the variable oscillator circuit. The gain control circuit varies the frequency control signal based on the loop control signal at a gain determined by the gain control signal. In a more specific embodiment, the variable oscillator circuit is a current controlled oscillator and the gain control circuit converts the loop control signal to a current signal. Furthermore, the damping controller may be configured to control the gain control signal to cause the current controlled oscillator to adjust the gain of the current signal to compensate for changes of the clock multiplier.

The damping controller may be implemented to provide one of several different values of the gain control signal for each of several clock multiplier values to minimize changes of the damping coefficient. As an example, a lookup table or the like may be used to convert each clock multiplier value to a corresponding gain control value provided to the oscillator. For typical PLL circuits, the damping coefficient is a function of the square-root of gain divided by the clock multiplier. In one embodiment, the damping controller controls the gain control signal to whatever value is needed to effectively multiply the gain of the oscillator by the clock multiplier in order to maintain the same damping coefficient for each frequency of the third clock.

A PLL circuit having a dynamically optimized damping coefficient according to an embodiment of the present invention includes a detector, a charge pump, a filter circuit, an oscillator circuit, a frequency divider and a damping controller. The detector compares a first clock signal with a second clock signal and provides an error signal indicative of a frequency and phase differential. The charge pump has an input receiving the error signal and an output providing a pulse signal indicative thereof. The filter circuit is coupled to the charge pump for converting the pulse signal to a loop control signal. The oscillator circuit has a first input receiving the loop control signal, a second input receiving a gain signal and an output providing a third clock signal, where the gain signal adjusts a gain of the oscillator circuit. The frequency divider has a first input receiving the third clock signal, a second input receiving a clock multiplier, and an output providing the second clock signal. The frequency of the second clock signal is based on a frequency of the third clock signal divided by the clock multiplier. The damping controller has an input receiving the clock multiplier and an output providing the gain signal, where the damping controller adjusts the gain of the oscillator circuit in response to changes of the clock multiplier.

The oscillator circuit may include a variable oscillator circuit providing the third clock signal and a gain circuit. The gain circuit has a first input receiving the loop control signal, a second input receiving the gain signal, and an output providing a frequency control signal to the variable oscillator circuit. In a more specific embodiment, the filter circuit provides the loop control signal as a voltage signal to the first input of the gain circuit, where the gain circuit is a voltage to current converter and where the oscillator is a current controlled oscillator. In one embodiment, the damping controller controls the gain signal to multiply the gain of the oscillator circuit by the clock multiplier to maintain the damping coefficient substantially constant over the variable N.

An integrated circuit according to an embodiment of the present invention includes a first pin receiving an external clock signal having a first frequency, a second pin for receiving a clock multiplier, and an integrated PLL circuit. The PLL circuit has a first input coupled to the first pin for receiving the external clock signal, a second input coupled to the second pin for receiving the clock multiplier, and an adjustable oscillator having an output providing a core clock signal having a second frequency approximately equal to the first frequency multiplied by the clock multiplier. The adjustable oscillator includes a damping controller and an oscillator circuit. The damping controller has an input receiving the clock multiplier and an output providing an adjust signal. The oscillator circuit has an input receiving the adjust signal and an output providing the core clock signal, where the adjust signal controls gain of the oscillator circuit to maintain a substantially constant damping coefficient for the PLL circuit.

A method of optimizing a damping coefficient of a PLL according to an embodiment of the present invention includes converting a clock multiple into a gain control value and adjusting the gain of an oscillator using the gain control value to minimize changes of the damping coefficient. The PLL controls the oscillator to provide a second clock signal having a frequency which is a multiple of a frequency of a first clock signal. The damping coefficient is a function of gain of the oscillator divided by the clock multiple.

The method may include adjusting current level provided to a current controlled oscillator. The method may include multiplying the oscillator gain by the multiple. The method may include comparing the first clock signal with a divided clock signal and providing a loop control signal indicative thereof, varying a frequency control signal based on the loop control signal, providing the frequency control signal to a variable oscillator circuit, and varying a rate of change of the frequency control signal based on the gain control value. The method may include converting the loop control signal to a current signal, varying the current signal based on the loop control signal, varying a rate of change of the current signal based on the gain control value, and providing the current signal to a current controlled oscillator. The method may include converting a loop control voltage to the current signal, converting, by the current controlled oscillator, the current signal to the second clock signal, and dividing the second clock signal by the multiple to provide the divided clock signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The benefits, features, and advantages of the present invention will become better understood with regard to the following description, and accompanying drawings where:

FIG. 1 is a simplified block diagram of a conventional PLL circuit implemented according to prior art;

FIG. 2 is a simplified block diagram of an exemplary PLL circuit implemented according to an embodiment of the present invention;

FIG. 3 is a more detailed schematic and block diagram of the loop filter, the oscillator circuit and the damping controller implemented according to a more specific embodiment of the PLL circuit of FIG. 2;

FIG. 4 is a graph diagram plotting simulation results of the frequency of the CORECLK signal versus the VLP signal for several discrete values of gain; and

FIG. 5 is a flowchart diagram illustrating a method for optimizing the damping coefficient of a PLL circuit according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION

The following description is presented to enable one of ordinary skill in the art to make and use the present invention as provided within the context of a particular application and its requirements. Various modifications to the preferred embodiment will, however, be apparent to one skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described herein, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

The inventors of the present application have recognized the need to solve the problems associated with the present art, particularly with respect to the limitations imposed on pipelined devices when conventional PLL circuits are employed. They have therefore developed a system and method for markedly improving the spectral purity of a core clock signal generated by a PLL circuit within an integrated circuit or used by an electronic device by dynamically optimizing the PLL damping coefficient based upon the value of a clock multiplier, as will be further described below with respect to FIGS. 1-5. When employed in a pipeline architecture, undesirable jitter is minimized so that pipelined devices can be designed to increase the amount of work performed between pipelined stages due to the increased spectral purity provided to a core clock signal.

FIG. 1 is a simplified block diagram of a conventional PLL circuit 100. A first clock signal BUSCLK is provided to a first input of a phase/frequency detector 101, which receives a second clock signal REFCLK at a second input. The phase/frequency detector 101 compares the frequency and/or phase between the REFCLK and BUSCLK signals and provides an up/down error signal UP/DN that indicates any differences in phase and/or frequency. A charge pump 103 has an input receiving the error signal UP/DN and generates a current pulse signal IC at its output, which is provided to a loop filter 105. Although the magnitude of the IC current pulse is typically static, the sign (positive pulse or negative pulse) of the IC signal generally indicates the direction to align REFCLK with BUSCLK and the duration of the IC current pulse typically indicates the amount of correction needed to align the BUSCLK and REFCLK clock signals with each other. The loop filter 105 converts the IC signal to a loop control signal LC, which is provided to a control input of a constant V/I converter 111 within an oscillator circuit 107. The constant V/I converter 111 converts the loop control signal LC to a current signal I, which is provided to the input of a current controlled oscillator 108. The constant V/I converter 111 converts the loop control signal LC according to a constant proportional relationship. The oscillator circuit 107 generates a core clock signal CORECLK, which is provided to one input of a divider circuit 109. The divider circuit 109 receives a frequency or clock multiplier N at a second input, and converts the CORECLK signal to the REFCLK signal which is provided to the phase/frequency detector 101. The clock multiplier N determines the frequency relationship between BUSCLK and CORECLK. The divider circuit 109 divides the frequency of CORECLK by the multiplier N to derive the frequency of REFCLK, which is provided back to the phase/frequency detector 101 to close the loop. In this manner, the PLL circuit 100 operates to multiply the frequency of BUSCLK by the multiplier N to achieve the frequency of CORECLK, and to synchronize CORECLK with BUSCLK.

The PLL circuit 100 may be implemented on an integrated circuit or the like, where the BUSCLK signal and multiplier N are received externally or off-chip and the CORECLK signal is used on-chip. The present invention, however, contemplates configurations other than integrated circuits and generally applies to PLL circuits used by any electronic device. The loop filter 105 filters the IC signal and generates the loop control signal LC, which is used to control the frequency of the CORECLK signal in standard feedback operation. The LC signal may be in the form of a current signal or a voltage signal, and the oscillator circuit 107 may be current or voltage controlled as known to those skilled in the art. The spectral quality of the PLL circuit 100 is acceptable as long as the BUSCLK signal and the clock multiplier N are static and do not change. As described previously, however, for applications in which it is desired to dynamically vary the frequency of BUSCLK or the value of the clock multiplier N, the spectral quality of the PLL circuit 100 is not acceptable since it generates undesirable jitter in response to such changes due to an increased of decreased current signal I in constant proportion to changes in the loop control signal LC. With reference to Proportion 1, the gain KV of the oscillator circuit 107 is generally fixed, so that changes in N result in undesirable changes in the damping coefficient θ causing jitter and reducing the spectral quality of the PLL circuit 100.

FIG. 2 is a simplified block diagram of an exemplary PLL circuit 200 implemented according to an embodiment of the present invention. The PLL circuits 100 and 200 include several similar components which are given identical reference numbers. In particular, the phase/frequency detector 101, the charge pump 103, the loop filter 105 and the divider circuit 109 are included in the PLL circuit 200 and operate in substantially the same manner. The divider 109 divides CORECLK by N to provide REFCLK to the phase/frequency detector 101, which generates the UP/DN error signal provided to the charge pump 103, which generates the IC signal to the loop filter 105, which generates the loop control signal LC. The oscillator circuit 107 of the PLL circuit 100 is replaced with a gain controlled oscillator circuit 201, which receives the loop control signal LC and which generates the CORECLK signal. The oscillator circuit 201 includes a variable V/I converter circuit 203 having a first input receiving the LC signal and an output providing a control signal I. The I signal is provided to a variable oscillator circuit 205, which provides the CORECLK signal at its output. A damping controller circuit 207 is added which receives the clock multiplier N and which provides a gain control signal GC to another input of the variable V/I converter circuit 203. In one embodiment, the variable oscillator circuit 205 is a current controlled oscillator (ICO) 205. An alternative embodiment is also contemplated where the variable oscillator circuit 205 is a voltage controlled oscillator (not shown).

The oscillator circuit 201 operates in a similar manner as the oscillator circuit 107, except that the gain of the oscillator circuit 201 is controlled or otherwise adjusted based on the GC signal. Gain KV is defined as the change in frequency (F) of the CORECLK signal, or ΔF, as a function of the change in the LC signal, or ΔLC, or KV=ΔF/ΔLC, where the forward slash “/” denotes division. For example, if the frequency is measured in GHz and the LC signal is a voltage signal measured in Volts (V), then the gain KV has units of Hz/V. For a given value of the clock multiplier N, say N1, the damping controller 207 asserts a corresponding value of the GC signal, say GC1, which causes the variable V/I converter circuit 203 to operate at a corresponding gain KV, or KV1. Thus, the variable V/I converter circuit 203 converts the LC signal to the I signal which is used to control the frequency of the CORECLK signal provided by the variable oscillator circuit 205 at the corresponding gain of KV1. For GC1, the gain KV1 determines the relationship between LC and CORECLK employed in the control loop.

When the multiple N is changed to a new value, say N2, the damping controller 207 changes the GC signal to a corresponding new value, say GC2, which causes the oscillator circuit 201 to operate at a corresponding new gain, say KV2. In order to optimize the spectral quality of the PLL circuit 200, the damping controller 207, the variable V/I converter circuit 203 and the ICO 205 are configured to minimize changes of the damping coefficient θ. As defined in Proportion 1, the damping coefficient θ is a function of the square-root of KV/N, so that for any change of N, the gain KV of the oscillator circuit 201 is modified by the same factor (e.g., N). In this manner, the change in N is effectively canceled by or compensated with the change in KV so that any change of the damping coefficient is minimized. For example, if N is doubled from 10 to 20, then the gain KV is also doubled so that the damping coefficient remains unchanged according to Proportion 1. Since changes of the damping coefficient are minimized in response to changes of the clock multiplier N by concomitantly changing the oscillator gain, the spectral quality of the PLL circuit 200 is improved relative to the spectral quality of the PLL circuit 100.

FIG. 3 is a more detailed schematic and block diagram of the loop filter 105, the oscillator circuit 201 and the damping controller 207 implemented according to a more specific embodiment of the PLL circuit 200. The IC signal is a current pulse applied via a node 301 to a resistor R and capacitor C coupled in series between node 301 and ground (GND). Node 301 develops a loop control voltage VLP, which is provided to the oscillator circuit 201. In this case, the VLP signal serves as the loop control signal LC (shown in parenthesis). The VLP signal is applied to a variable voltage to current (V/I) converter 303 within the oscillator circuit 201, which converts the VLP signal to a current signal I, which is provided to the input of a current controlled oscillator (ICO) 305. In the illustrated embodiment, the damping controller 207 receives the clock multiplier N and generates or decodes corresponding signals on a frequency strobe bus FSTR provided to a gain control input of the V/I converter 303. In this case, the FSTR bus serves as the gain control signal GC (shown in parenthesis). In one embodiment, the FSTR bus includes multiple digital signals to control or adjust gain between multiple discrete gain values, each corresponding to discrete values of the clock multiplier N. The signals of the FSTR bus direct the V/I converter 303 to increase/decrease current I to oscillator cells within the ICO 305 in order to stabilize the PLL damping coefficient θ as a function of N. Thus, the damping controller 207 directs the V/I converter 303 via the FSTR bus to increase or decrease the current I to control gain to maintain the damping coefficient of the PLL circuit 200 stable with respect to changes in the value of the clock multiplier N. With reference to Proportion 1 for the damping coefficient θ, N is the clock multiplier provided to the damping controller 207, IC is the current provided via node 301 to the loop filter 105, R and C are the resistance and capacitance values of the loop filter 105, and KV is the gain of the oscillator circuit 201 defined as the change in frequency of the CORECLK signal per change of voltage of the VLP signal, or KV=ΔF/ΔVLP. As previously noted, if a capacitor is placed in parallel with the series RC filter, Proportion 1 is modified accordingly; yet the principles of the present invention remain unchanged since changes of the damping coefficient are minimized in the same manner.

FIG. 4 is a graph diagram plotting simulation results of the frequency (F) of the CORECLK signal in GHz versus the VLP signal in Volts (V) for several discrete values of gain KV ranging from 1 to n, or KV1 to KVn, assuming that the PLL circuit 200 is designed to operate from 400 MHz to 4 GHz over a nominal loop filter voltage range of 0.25 V to 0.75 V. The discrete values of gain KV are determined by corresponding discrete values of the current I provided to the ICO 305. A conventional PLL, such as the PLL circuit 100, would be characterized by only one of the gain curves KVn:KV1 because gain of the oscillator circuit 107 is not modulated as a function of the clock multiplier N. Consequently, the slope of one particular KV curve would be the gain KV that would be used in Proportion 1 to determine the damping coefficient θ of the PLL circuit 100 for all values of N. As the clock multiplier N varies for the conventional PLL circuit 100, so varies the damping coefficient θ in accordance with Proportion 1 because KV, R, and C are fixed. But in contrast to the conventional PLL circuit 100, the PLL circuit 200 according to the present invention keeps the value of the damping coefficient θ relatively constant by directing the ICO 305 via bus FSTR to increase or decrease current I to the oscillator cells when the clock multiplier N changes. Changing the current I results in a change to the gain KV of the oscillator, which compensates for the change in the clock multiplier N, thus keeping the value of the damping coefficient θ relatively constant.

As an example and with reference to FIG. 4, assume that the oscillator circuit 107 of the conventional PLL circuit 100 has a gain curve 401 (i.e., KV8) and that the PLL circuit 100 is operating at a point 403 in which the frequency of CORECLK is about 2.08 GHz for a VLP voltage of about 0.5V. In this case, assume that the loop control signal LC for the PLL circuit 100 is the VLP voltage. If N changes to a new value to adjust the frequency of CORECLK to a new frequency of 2.75 GHz, then the PLL circuit 100 must adjust to a new operating point 405 along curve 401 associated with a VLP voltage of about 0.92V. With reference to the PLL circuit 100, the increase of N causes the divider 109 to reduce the frequency of REFCLK, and the phase/frequency detector 101 responds by asserting the UP/DN error signal to increase the frequency of REFCLK to once again equal the frequency of BUSCLK. The charge pump 103 and the loop filter 105 respond by increasing VLP towards 0.92V until the frequency of CORECLK eventually settles in to the new target frequency of 2.75 GHz. The entire control loop of the PLL circuit 100 must respond to reach and settle on the new frequency. And note that during this process, the damping coefficient θ is reduced since it is a function of the square-root of 1/N. The result is a significant amount of jitter, a change of the damping coefficient and reduced spectral purity. This in turn increases the time of response and reduces the amount of work that can be performed in the circuit employing the conventional PLL circuit 100.

In comparison, assume that the oscillator circuit 201 of the PLL circuit 200 includes all of the gain curves (i.e., KVn:KV1) and that the PLL circuit 200 is initially operating at the same point 403 of the gain curve 401 in which the frequency of CORECLK is about 2.08 GHz for a VLP voltage of about 0.5V. Also assume that the loop control signal LC for the PLL circuit 200 is the VLP voltage. It is desired to select a gain curve that maintains a mid-range level of VLP so that VLP remains relatively constant for changes of the clock multiplier N. In this case, when N changes to a new value to adjust the frequency of CORECLK to a new frequency of 2.75 GHz, the damping controller 207 adjusts the gain control signal GC (e.g., new value of FSTR), which adjusts the gain of the oscillator circuit 201 to a new gain curve 407 (i.e., shown as gain=KVn) to maintain the same mid-level value of VLP of approximately 0.5 V. Thus, the PLL circuit 200 adjusts to a new operating point 409 along the gain curve 407. With reference to the PLL circuit 200, the increase of N may initially cause the divider 109 to begin reducing the frequency of REFCLK. However, the change of the GC value causes the variable V/I converter circuit 203 to adjust the I signal to keep the damping coefficient at substantially the same value after the ICO 205 aligns the phase of the CORECLK to the new frequency of 2.75 GHz as it was prior to the change. In the embodiment of FIG. 3, the damping controller 207 adjusts the value of FSTR to switch the variable V/I converter 303 to assert a new value of source current I. Thus, The damping coefficient θ remains constant since the change of N is compensated by the change in gain KV. The result is a significantly reduced amount of jitter and a stable damping coefficient thereby resulting in relatively high spectral purity. This enables reduced time of response and a concomitant increase in the amount of work that can be performed in the integrated circuit or electronic device.

FIG. 5 is a flowchart diagram illustrating a method for optimizing the damping coefficient of a PLL circuit according to an exemplary embodiment of the present invention. Several blocks, including blocks 501, 503, 505 and 511 are similar to that of a conventional PLL. At a block 501, the frequency and phase of first and second clock signals are compared and a corresponding error signal is provided. In various embodiments as described above, the first signal is a bus clock or external clock or the like, the second clock is a feedback or reference clock fed back from a frequency divider in the control loop of the PLL, and the error signal is an up/down signal. At next block 503, the error signal is converted to a charge signal. PLL circuits typically employ a charge pump or the like to convert the error signal to a charge signal. At next block 505, the charge signal is filtered into a loop control signal. The loop control signal may have any suitable form, such as a current signal or a voltage signal as known to those skilled in the art. In one embodiment, for example, the charge signal is a current signal provided to a resistor-capacitor filter, which develops a loop control voltage or the like as known to those skilled in the art. Meanwhile at block 507, the clock multiplier N is converted to a gain control value suitable to minimize the change of the damping coefficient of the PLL in response to changes of the clock multiplier value. At next block 509, the loop control signal is converted into a third clock signal at a gain determined by the gain control value. The conversion between the loop control signal and the third clock signal may be performed by a variable oscillator circuit or the like, such as a current controlled oscillator or a voltage controlled oscillator. At last block 511, the frequency of the third clock signal is divided by the clock multiplier N to provide the second clock signal, and operation returns to blocks 501 and 507.

The function of block 507 may be performed concurrently with any one or more of the blocks 501-505 as shown, although this is not necessarily the case. In an integrated circuit embodiment, for example, a detector compares the frequency/phase of an input bus clock with a reference clock while coefficient logic converts an external clock multiplier to the gain control value. The conversion between the clock multiplier and gain control value depends on the characteristics and configuration of the variable oscillator circuit and the range and configuration of the loop control signal. The loop control signal represents a conversion between the error signal from the detector and the frequency of the third clock signal which is controlled to minimize the error. The gain of the oscillator controls the relative change of frequency of the third clock signal in response to changes of the loop control signal. In one embodiment, a nominal or mid-level value of the loop control signal is selected and the damping controller adjusts the gain control value to maintain about the same level of the loop control signal for each value of the clock multiplier. The gain control values may be determined experimentally and stored within the damping controller. The damping controller may be implemented in any suitable manner, such as a lookup table or the like.

Less complex embodiments of the present invention presume fixed values of charge pump current IC and the R and C components of the loop filter 105. Although these embodiments are less complex, it is noted that the present invention also comprehends embodiments that dynamically modulate one or more of these values IC, R, C as well as KV in order to maintain the stability of the damping coefficient θ. One embodiment of the present invention contemplates simulating n oscillator gain curves KVn:KV1 as a function of n values of the FSTR bus over a desired operating frequency range and as a function of a desired loop filter voltage range. In this case, the damping controller 207 is configured to generate a discrete value of FSTR for each value of N such that the associated gain KV of the oscillator circuit 201 results in a relatively constant value for the damping coefficient θ. One embodiment selects the values of FSTR such that θ is held approximately equal to 0.707, however the present invention contemplates alternative embodiments where the damping coefficient is held at values other than 0.707. A nominal loop filter voltage embodiment selects the aforementioned values of FSTR at a mid-range value of the loop filter voltage VLP (e.g., 0.5 V).

Several benefits and advantages are achieved with a system and method for optimizing phase locked loop damping according to embodiments of the present invention. One advantage is that undesirable jitter is minimized in a PLL implemented according to the present invention since variations of the damping coefficient of the PLL are minimized with corresponding changes of the clock multiplier between the core (output or internal) clock and the bus (input or external) clock. Another advantage is that pipelined devices can be designed to increase the amount of work performed between pipelined stages due to the increased spectral purity provided to the internal core clock signal.

Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions and variations are possible and contemplated. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for providing out the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. An adjustable oscillator for dynamically optimizing a damping coefficient of a phase locked loop (PLL) circuit, the PLL circuit providing a loop control signal indicative of an error between first and second clock signals for generating a third clock signal having a frequency which is a clock multiplier times the frequency of the second clock signal, said adjustable oscillator comprising: a gain controlled oscillator circuit having a control input receiving the loop control signal, a gain control input, and an output that provides the third clock signal; and a damping controller having an input for receiving the clock multiplier and an output providing a gain control signal to said gain control input of said gain controlled oscillator circuit, wherein said damping controller adjusts gain of said gain controlled oscillator circuit in response to changes of the clock multiplier.

2. The adjustable oscillator of claim 1, wherein said gain controlled oscillator circuit comprises: a variable oscillator circuit having a frequency control input and an output providing the third clock signal; and a gain control circuit having a first input receiving the loop control signal, a second input receiving said gain control signal, and an output providing a frequency control signal to said frequency control input of said variable oscillator circuit; wherein said gain control circuit varies said frequency control signal based on the loop control signal at a gain determined by said gain control signal.

3. The adjustable oscillator of claim 2, wherein said variable oscillator circuit comprises a current controlled oscillator and wherein said gain control circuit converts the loop control signal to a current signal.

4. The adjustable oscillator of claim 3, wherein said damping controller controls said gain control signal to cause said current controlled oscillator to adjust gain of said current signal to compensate for changes of the clock multiplier.

5. The adjustable oscillator of claim 1, wherein said damping controller provides one of a plurality of different values of said gain control signal for each of a plurality of clock multiplier values to minimize changes of the damping coefficient.

6. The adjustable oscillator of claim 5, wherein the damping coefficient is a function of said gain of said gain controlled oscillator circuit divided by the clock multiplier, and wherein said damping controller controls said gain control signal to multiply said gain of said oscillator by said clock multiplier.

7. A phase locked loop (PLL) circuit having a dynamically optimized damping coefficient, comprising: a detector which compares a first clock signal with a second clock signal and which provides an error signal indicative of a frequency and phase differential; a charge pump having an input receiving said error signal and an output providing a pulse signal indicative thereof; a filter circuit coupled to said charge pump for converting said pulse signal to a loop control signal; an oscillator circuit having a first input receiving said loop control signal, a second input receiving a gain signal and an output providing a third clock signal, wherein said gain signal adjusts a gain of said oscillator circuit; a frequency divider having a first input receiving said third clock signal, a second input receiving a clock multiplier, and an output providing said second clock signal having with a frequency that is based on a frequency of said third clock signal divided by said clock multiplier; and a damping controller having an input receiving said clock multiplier and an output providing said gain signal, wherein said damping controller adjusts said gain of said oscillator circuit in response to changes of said clock multiplier.

8. The PLL circuit of claim 7, wherein said oscillator circuit comprises: a variable oscillator circuit having a frequency control input and an output providing said third clock signal; and a gain circuit having a first input receiving said loop control signal, a second input receiving said gain signal, and an output providing a frequency control signal to said frequency control input of said variable oscillator circuit.

9. The PLL circuit of claim 8, wherein said filter circuit provides said loop control signal as a voltage signal to said first input of said gain circuit, wherein said gain circuit comprises a voltage to current converter, and wherein said variable oscillator circuit comprises a current controlled oscillator.

10. The PLL circuit of claim 7, wherein the damping coefficient is a function of said gain of said oscillator circuit divided by said clock multiplier, and wherein said damping controller controls said gain signal to multiply said gain of said oscillator circuit by said clock multiplier to maintain the damping coefficient substantially constant.

11. An integrated circuit, comprising: a first pin receiving an external clock signal having a first frequency; a second pin for receiving a clock multiplier; and an integrated phase locked loop (PLL) circuit having a first input coupled to said first pin for receiving said external clock signal, a second input coupled to said second pin for receiving said clock multiplier, and an adjustable oscillator having an output providing a core clock signal having a second frequency approximately equal to said first frequency multiplied by said clock multiplier, said adjustable oscillator comprising: a damping controller having an input receiving said clock multiplier and an output providing an adjust signal; and an oscillator circuit having an input receiving said adjust signal and an output providing said core clock signal; wherein said adjust signal controls gain of said oscillator circuit to maintain a constant damping coefficient for said PLL circuit.

12. The integrated circuit of claim 11, wherein said damping controller controls said adjust signal to cause said oscillator circuit to increase its gain by said clock multiplier.

13. The integrated circuit of claim 11, wherein said oscillator circuit comprises: a current generator having an input receiving said adjust signal and an output providing a current level based on said clock multiplier; and a current controlled oscillator having a current control input coupled to said output of said current generator and an output providing said core clock signal.

14. The integrated circuit of claim 11, wherein said PLL circuit comprises: a detector having a first input coupled to said first pin, a second input receiving a divided clock signal and an output providing an error signal indicative of a frequency difference between said external clock signal and said divided clock signal; a charge pump having an input receiving said error signal and an output providing a pulse signal; a loop filter that converts said pulse signal into a loop control signal; wherein said oscillator circuit adjusts frequency of said core clock signal based on said loop control signal at a gain determined by said adjust signal; and a frequency divider having a first input receiving said core clock signal, a second input receiving said clock multiplier, and an output providing said divided clock signal.

15. A method of optimizing a damping coefficient of a phase lock loop (PLL) which controls an oscillator to provide a second clock signal having a frequency which is a multiple of a frequency of a first clock signal, wherein the damping coefficient comprises a function of oscillator gain divided by the multiple, comprising: converting the multiple into a gain control value; and adjusting the gain of the oscillator using the gain control value to minimize changes of the damping coefficient.

16. The method of claim 15, wherein said adjusting the gain of the oscillator comprises adjusting current level provided to a current controlled oscillator.

17. The method of claim 15, wherein said adjusting the gain of the oscillator comprises multiplying the oscillator gain by the multiple.

18. The method of claim 15, further comprising: comparing the first clock signal with a divided clock signal and providing a loop control signal indicative thereof; varying a frequency control signal based on the loop control signal; providing the frequency control signal to a variable oscillator circuit; and varying a rate of change of the frequency control signal based on the gain control value.

19. The method of claim 18, further comprising: converting the loop control signal to a current signal; wherein said varying a frequency control signal comprises varying the current signal based on the loop control signal; wherein said varying a rate of change of the frequency control signal comprises varying a rate of change of the current signal based on the gain control value; and wherein said providing the frequency control signal to a variable oscillator circuit comprises providing the current signal to a current controlled oscillator.

20. The method of claim 19, further comprising: said converting the loop control signal to a current signal comprising converting a loop control voltage to the current signal; converting, by the current controlled oscillator, the current signal to the second clock signal; and dividing the second clock signal by the multiple to provide the divided clock signal.