"Rochester's Intelligent Gateway"; K.A. Lantz et al.; IEEE, vol. 15, No. 10, Oct. 1982; pp. 54-68. |
"An approach to the design of distributed real-time operating systems"; Cvijovic et al.; Microprocessors and Microsystems; vol. 16, No. 2; 1992; pp. 81-89. |
"A Second-Level Cache Controller for A Super-Scalar SPARC Procesor"; Chang et al.; 37th IEEE CompCon Conference; Feb. 24-28, 1992; pp. 142-151. |
"The SPARC Architecture Manual"; Version 9; SPARC International, Inc., Menlo Park, California; 1994; 8 Memory Models; pp. 117-129 & pp. 256-262. |
Gharachorloo, K., et al., "Programming for Different Memory Consistency Models", Journal of Parallel and Distributed Computing, vol. 15, No. 4, 1 Aug. 1991, Duluth, US, pp. 399-407. |