Patent Application
20160334575
The present invention relates to a system and method for photonics, and, in particular, to a system and method for photonic switching.
Data centers route massive quantities of data. Currently, data centers may have a throughput of 5-10 terabytes per second, which is expected to increase in the future. Data centers contain huge numbers of racks of servers, racks of storage devices, and other racks often with top-of-rack (TOR) switches, all of which are interconnected via massive centralized packet switching resources. In data centers, electrical packet switches are used to route all data packets, irrespective of packet properties, in these data centers. However, electrical packet switches have limited speeds and throughput capacities, which may utilize complex multi-layer core networks of such switches to implement large data centers. However, large photonic switches may provide a throughput capacity to produce a single layer data center core. Hence photonic switching may be desirable for packet switching in data centers.
An embodiment photonic device includes an optical macromodule substrate including optical interconnects and a first photonic integrated circuit (PIC) including a first photonic switch, where the first PIC is mechanically coupled to the optical macromodule substrate and optically coupled to the optical interconnect. The photonic device also includes a PIC controller electrically coupled to the first PIC.
An embodiment photonic switch includes an input stage including a first optical including a first photonic integrated circuit (PIC) switch and a second optical macromodule including a second PIC switch. The photonic switch also includes a center stage including a third optical macromodule including a third PIC switch, where the third optical macromodule is optically coupled to the first optical macromodule and the second optical macromodule and a fourth optical macromodule including a fourth PIC switch, where the fourth optical macromodule is optically coupled to the first optical macromodule and the second optical macromodule. Additionally, the photonic switch includes an output stage including a fifth optical macromodule including a fifth PIC switch, where the fifth optical macromodule is optically coupled to the third optical macromodule and the fourth optical macromodule and a sixth optical macromodule including a sixth PIC switch, where the sixth optical macromodule is optically coupled to the third optical macromodule and the fourth optical macromodule.
An embodiment method includes receiving an input optical stream and producing a first split optical stream having a first polarization and a second split optical stream having the first polarization from the input optical stream by a polarization splitter/rotator. The method also includes switching the first split optical stream to produce a first switched optical stream by a first optical switch and amplifying the first switched optical stream to produce a first amplified optical stream by a first amplifier. Additionally, the method includes switching the second optical stream to produce a second switched optical stream by a second optical switch and amplifying the second switched optical stream to produce a second amplified optical stream by a second amplifier. Also, the method includes combining the first amplified optical stream and the second amplified optical stream to produce a polarization agnostic optical stream by a polarization rotator/combiner.
The foregoing has outlined rather broadly the features of an embodiment of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of embodiments of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which:
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.
It should be understood at the outset that although an illustrative implementation of one or more embodiments are provided below, the disclosed systems and/or methods may be implemented using any number of techniques, whether currently known or in existence. The disclosure should in no way be limited to the illustrative implementations, drawings, and techniques illustrated below, including the exemplary designs and implementations illustrated and described herein, but may be modified within the scope of the appended claims along with their full scope of equivalents.
An embodiment photonic switching module has precision lithographically defined optical interconnect to form a skew-controlled optical switch with multiple photonic integrated circuits (PICs) per switching module referred to as a macromodule or an optical macromodule. Skew is a timing offset between two signals that originally were aligned to a common timing reference, the offset resulting from the signals having propagated along different physical paths with different physical delays. Optical macromodules may be polarization agnostic or polarization specific, depending on the functionality incorporated into them and the polarization-agnostic or polarization-specific nature of that functionality. An embodiment has a high per-module switching capacity with multiple switching PIC matrices in an array on the optical macromodule. These arrays of PIC switches are placed on a larger area, lower lithographic density, interconnect optical macromodule substrate with control circuits directly mounted on the PICs. Hybridized arrays of semiconductor optical amplifiers (SOAs) on the substrate, with SOA controllers associated with the SOAs, are used to compensate for optical loss, for example in the PICs and optical macromodule components. Pairs of sets of single polarization PICs and SOAs are placed between an input array of polarization splitters/rotators and an output array of polarization rotators/combiners for a polarization-agnostic photonic switching module.
A photonic switch may be composed of switching stage modules in parallel and/or in series, for example in a Clos switch.
Thus, it is desirable to combine PICs to create larger switch modules from which to fabricate the switch to increase the overall port count. Combining PICs may facilitate an increased number of ports in a photonic switching structure. An embodiment photonic switch includes an optical macromodule, which has a large area substrate with lithographically-defined optical interconnect which includes monolithic photonic structures, such as interconnection waveguides, polarization splitters and combiners. There is a coarser geometry for the structures on the optical macromodule than for the PICs. For example, the optical macromodules may contain silicon dioxide waveguides having a waveguide width of 5 microns, and the PICs may include silicon waveguides having a waveguide width of 0.5 microns. The optical macromodule substrate may be manufactured using a low resolution photolithographic process such as contact lithography to facilitate a large maximum substrate area, for example an area 20 cm by 20 cm. The PIC may be manufactured using a high resolution photolithographic process, such as stepper lithography, which has a relatively small area, for example an area 2 cm by 2 cm, which is much smaller than the area of the optical macromodule. Thus, multiple PICs can be combined in one optical macromodule.
A small array of PICs on an optical macromodule may be used for a large port count switch module, which may be used as part of a larger switch fabric. Both PICs and array structures may be square with the same number of inputs and outputs, or rectangular with different numbers of inputs and outputs. For example, a 2×2 array of N×2N switch PICs may yield a dilating switch stage of 2N×4N, and a 2×4 array of N×N switch PICs may also yield a dilating switch stage of 2N×4N.
Additionally, using a matrix of PICs on an optical macromodule, the input and output signals may be achieved using integrated power splitters and combiners in the optical macromodule substrate. Power splitters and combiners may be used to direct optical signals to multiple switching modules or PICs. The optical macromodule may also include semiconductor optical amplifiers (SOA) to amplify the optical signals and compensate for optical losses.
The incoming optical signal with an arbitrary polarization has a sum of two orthogonal polarizations. However, it is problematic to make a PIC that acts identically on both polarizations. Thus, the PICs may contain single-polarization switches and the PICs may be arranged as pairs of PICs, each handling one of the two orthogonal polarizations in a polarization diversity scheme. The light in each polarization encounters a different physical path, which may create skew between the light of the two polarizations. This skew may produce a large degradation in the optical signal quality. Thus, the pair of PICs may be arranged on a lithographically defined optical macromodule, which includes polarization splitter and polarization combiner components implemented monolithically with precision lithography on the optical macromodule substrate. The waveguides on the optical macromodule substrate may also control path lengths to minimize the skew between the light of the two polarizations. At bit rates of around 100 Gb/s, transmitted as 4×25 Gb/s signals, the symbol period is around 40 ps. The signal may tolerate a skew between the two polarizations of around 10% to 30% of the symbol period, which is around 4 ps to 12 ps. In glass, this corresponds to a distance of about 0.8 mm to 2.4 mm path length difference between the polarization diverse paths.
An embodiment macromodule based three stage Clos switch is illustrated by photonic switching structure 100 in
An optical macromodule is a limited area, highly dense, and accurately dimensioned optical substrate which provides both high density interconnectivity and high density optical coupling and interconnect. The substrate may be silicon, silicon on insulator, silica on silicon, or another substrate, or another optically active layer, which may be a silicon based substrate, with silicon nitride, or a non-silicon based substrate, for example with polymer-based active layers. When optical macromodules are used, active optical functions, such as arrays of switch matrix PICs are hybridized on the macromodule surface, along with other electronic, photonic, and/or electro-photonic functions leading to a complete component switching fabric.
Table 1 illustrates some characteristics of optical waveguides fabricated from silicon, silicon nitride, and silicon dioxide. The three optically active material layers have different properties. In addition, various structures may transition between layers or materials systems for mixing of these materials. Silicon or silicon nitride waveguides may use amplification, which may be hybridized SOAs, while silicon dioxide waveguides may use hybridized SOAs or erbium doped waveguide amplifiers (EDWAs), which are optically powered by pumping the amplifier, implemented by doping the silicon dioxide waveguide with erbium ions, pumped with 980 nm or 1480 nm light. EDWAs are polarization-insensitive, and may be used outside polarization-split paths, halving the number of amplifiers. Also, high electrical power burn, and consequent heat production is at the remotely located pump laser rather than on the optical macromodule at the amplifier sites.
An optical macromodule combines arrays of PICs, ASICs, and other functions, both monolithically integrated into an optical connection matrix of an optical macromodule substrate and hybridized on its surface.
A switch, such as photonic switch 660 or photonic switch 590 implemented in the form of a single PIC, may be used in an optical macromodule switching structure.
Mi*Ni inputs enter the optical macromodule and are received by power splitters 182, two 90:10 power splitters monolithically integrated on the substrate. 10% of the input optical power is tapped off and fed to a phase comparator, which compares the incoming signal phase with the local switch feeding frame, and clocks the incoming phase, which are fed back to correct the source timing. The remaining optical power is fed to power splitters 184. Power splitters 184 are Mi-way optical power splitters, for example two way monolithic splitters, which produce two nominally identical optical outputs, so that the same optical signal is driven into two paths. The split light is fed to polarization splitters/rotators 186, four polarization rotators and splitters which produce two optical outputs both with polarization in the plane that the PICs are optimized for.
The outputs are fed to photonic switches 188, eight Ni×No hybridized PIC photonic switches. The crosspoint driver map is fed to crosspoint map router 198, which operates on the most significant bits of the addresses. The map is routed to PIC crosspoint drivers 200, which drive the PICs. There is one PIC crosspoint driver per PIC. The PIC crosspoint drives are directly mounted on the PIC to facilitate electrical connections between the PIC and PIC controller.
The switched outputs are then combined by power combiners 190, four Mo-way optical power combiners, where Mo=2, and fed into SOAs 192 for amplification to compensate for losses, for example in the power splitter, polarization splitter, PIC, power combiner, and not yet reached polarization combiner, as well as other losses, for example from macromodule optical tracks. The SOAs are controlled by SOA controller block 194. The amplified signals are then combined with signals from the matching polarization by polarization rotators/combiners 196. Finally, Mo*No optical outputs are output. The polarization diverse paths extend from the input to the polarization rotator/splitter to the output of the polarization rotator/combiner, which is matched for each path pair. The optical macromodules may be combined in various switch topologies, including matrixed switches which use a large number of optical macromodules, but are directly addressed, and three stage Clos switches.
Silicon or silica on silicon may be used for the macromodule substrate. Silicon is conducive to integration of electronic functions, while silica is conducive to the integration of optical amplifiers, such as EDWA arrays. Both materials systems, as well as silicon nitride, support integrated passive components such as power splitters and combiners, polarization splitters and combiners, and mode expanders and compressors. Also, silica interfaces well to conventional fibers, because its waveguide propagation mode size is relatively well matched to that of fiber. With silicon waveguides, a mode expander may be used between the waveguide and the fiber. An optical path may go through both silica and silicon on the same substrate.
Large photonic switches may be fabricated from series and/or parallel arrays of switching crosspoint modules. Additional functionality, such as polarization splitting, polarization rotation, and polarization combining are used for pairs of single polarization switches. Also, amplification may be used to compensate for losses.
Polarization diversity may be used to combine two single polarization functions to produce a function in a polarization agnostic manner.
Polarization splitting and combining may be carried out on a per-switching stage basis to avoid balancing optical path lengths between fiber and polarization maintaining fibers and connectors. At 100 Gigasymbols/s (Gs/s), to maintain polarity phase alignment of 10% of a clock cycle, the path lengths for the two polarizations are balanced to within 0.2 mm. For 25 Gs/s (for example a 100 Gb/s signal sent on four parallel optical carriers) and 10% of a clock cycle, the two polarizations are balanced to within 0.8 mm. In other examples, the polarization paths are balanced within a distance determined by the acceptable level of inter-symbol overlap to control inter-symbol interference (5-30%) and symbol rate (10 Gs/s to 100 Gs/s). In some examples, the polarization paths are within 5 mm, 1 mm, 500 μm, 200 μm, 100 μm, 50 μm, or another distance.
A polarization splitter/combiner may be integrated on PIC chips or optical macromodules. It is desirable to have low optical losses, low impairments, low nonlinearity, and low noise. Also, it is desirable for accurate orthogonal splitting matching in the optimum polarization plane for the PIC and to rotate and split the polarization of the orthogonal component into this plane. This may be applied to each switching stage to avoid polarization maintaining interconnect between stages. The use of polarization splitting and rotation at the inputs to the first switching stage and polarization rotation and combining at the output stage reduces optical loss, doubles the amount of optical interconnect inside the switch, utilizes polarization maintaining connections and paths through the entire fabric, and demands tight differential path length control, for example less than or much less than 1 mm, over the paths through the switching path.
Multiple designs and methods for integrated polarization splitters may be used. One example silicon nitride on silicon-on-insulator (SOI) polarization splitter based on TM0-TE1 mode conversion, such as waveguide 860 illustrated in
In an optical macromodule, there may be a silicon or silica on silica optical interconnect structure, which in examples, may be between about 35 mm and about 118 mm per side. The substrate provides the optical interconnect into, out of, and between devices hybridized on the surface of the optical macromodule using a combination of waveguide technologies and topologies, including quasi-single mode waveguides between devices, which reduce losses. In one example, there is little or no mode conversion during the transit on longer macromodule optical paths. The optical macromodule substrate may provide some monolithic photonic functionality within the substrate, for example waveguide based optical power splitters and combiners and polarization splitters and combiners. The waveguides in the substrate may be coupled optically into hybridized devices and into incoming and outgoing optical connections. Hybridized devices may be coupled into using close waveguide couplers, diffraction grating couplers, angled micro-mirror couplers, or other couplers. Evanescent waveguide-to-waveguide vertical couplers, diffraction grating couplers, micro-mirror couplers, edge couplers, or other couplers may be used to connect to incoming or outgoing fibers. Also, beam mode expanders and compressors may be used to match to outgoing and incoming optical signals.
Hybridized photonic devices use electrical power, which may be provided by direct device or macromodule substrate electrical conductor contacts, or by wire bonding between the hybridized device and the macromodule electrical tracks and pads. For some photonic devices, such as PIC switches, the electronic control ASIC is bonded to the optically active surface of the PIC.
A large photonic switch may be composed of a matrix array of smaller photonic switches.
With a space-space-space three stage switch, the control system for photonic switching structure 100 may be similar to that in U.S. patent application Ser. No. 14/455,034. However, the control system also includes a center stage controller (CSC), which collects the input stage outputs selected for the paths and the output stage inputs for the same paths and maps them to the center stage input to output mapping for each center stage switching module.
A substrate material for an optical macromodule may be silicon or silica on silicon. Silicon or silica may be amenable to the fabrication by lithographic means of high density optical waveguide traces with low loss and low crosstalk at waveguide crossings.
The macromodule substrate supports a very dense set of optical interconnects with low loss and facilitate waveguide crossings with low loss. There is also coupling both into and out of the substrate both to hybridized devices and external connectors. The on substrate optical interconnect includes very dense single mode waveguides with large numbers of inputs and outputs for the hybridized PICs to be connected to the photonic signal sources and destinations within the optical macromodule and with optical coupling between the substrate waveguides and the hybridized components, and between the waveguides and external optical connections. There may be closely spaced single mode waveguides with relatively low loss on the longest paths. Waveguides cross other individual waveguides and large groups of other waveguides without significant loss or crosstalk. The waveguides terminate by coupling out of the substrate or into it or into or out of hybridized components with large number of connections and/or one or two optical connections. The optical signals are connected to and from the substrate from optical connectors. Mode expanders and compressors may be used to convert between the tightly confined modes of the on substrate waveguides and the broader modes of a fiber system.
On substrate electrical interconnect may be provided using aluminum or copper tracking. Electrical connects cross each other, which may use a two layer metallization scheme with an insulating material such as SiO2, Al2O3, a polymer, or another insulating material between the tracks. Electrical signals and power may be wire bonded on the substrate electrical tracks using pads.
There may be a variety of hybridized components on the optical macromodule, including PICs, such as optical switches, with large numbers of optical inputs and outputs, and SOAs.
The hybridized components are mounted with physical, optical, and electrical coupling to the macromodule substrate. Physical mounting and bonding may be used at the surface of the optical macromodule, for example by electrical connections such as solder bumps, or by glue bonding. Optical connections may be by arrays of couplers between the optical macromodule and the hybridized components, such as evanescent waveguide-to-waveguide vertical coupling, grating coupling, and/or micro-mirrors, which may be established in a fixed spatial relationship, so the hybridized components are aligned.
Two or four additional couplers and a path through the hybridized components between the pairs of couplers may be used for optical signals to be passed from the optical macromodule through the hybridized component and back to the optical macromodule for active alignment of the hybridized components to the optical macromodule. Electrical connections may be direct solid connections, such as solder bumps or indirect methods, such as wire bonding. The hybridized components are aligned for optical coupling between the optical macromodule optical interconnect and the hybridized optical components via optical couplers with matched closely coupled waveguide stubs, with one waveguide per stub in the substrate and the other stub on the hybridized components, which are mounted in close proximity.
Optical connections into and out of the optical macromodule may use edge coupled connectors or waveguides/fibers, waveguide mode expanders and expanded beam connectors, for example graded refractive index (GRIN) lenses.
A variety of monolithic functions and components are integrated in the macromodule substrate. Some monolithic functions include waveguides and arrays of waveguides with low loss. Other monolithic components include couplers into and out of waveguides at the hybridized components, mode expanders and compressors between the waveguides and fibers or external connectors, and waveguides or waveguide arrays which cross other waveguides or waveguide arrays.
The PIC chips are associated with per-cell switch controllers for cell optimization to maximize the contrast between on and off states and/or cross and bar states. The control may be intimately connected to the PIC, for example by mounting it over the PIC with the surface of the controller picking up on the surface of the PIC to control the individual cells. A hole or cut out may be placed in the optical macromodule under the PIC so the control chip is mounted on the hole with its active surface picking up on the PIC chip it controls. The control chip may be tracked out electrically for power, ground, inputs, and outputs by electrical tracks. The controller may also be thermally connected to the mounting plate under the optical macromodule.
Thermal management, such as heat sinking, may be used, especially with SOAs. SOAs may burn up to 0.5 W of electrical power when continuously operated at the gain, so an array of 64 SOAs on the surface of an optical macromodule may burn up to 32 W. This creates a cooling challenge in the optical macromodule. However, because the SOAs are associated with specific PIC output ports, and may be powered up in ˜500 picoseconds, each SOA of a SOA array may only be powered when its associated PIC output port is being used. This may be facilitated by coupling the SOA controller to the PIC controller, so the PIC controller provides frame-by-frame information on which output ports will be used. In a dilating switch stage, this reduces the peak power by a factor of two, even when all inputs to the PIC are 100% occupied all the time. At the packet switch overload point where momentary loads reach 100%, the average load is around 30%, resulting in a further factor of 3.3 saving because the thermal time-constant of the SOA plus cooling system mass is multiple orders of magnitude longer than the frame time, and therefore thermally integrate the effects of the frame-by-frame power burn. For a non-dilated switch, the number of SOAs is halved, and approximately 3.3:1 average power saving is achieved. At normal operating loads in a data center, with an average traffic level of around 10% (peak around 30-40%), where the packet switching delay starts to rise from the level of packet collisions triggering retransmission, the power saving is around 10:1. Also, SOAs are thermally sensitive, and perform better when cool. In another example, EDWAs are used, where electrical power is consumed by an external pump laser, which may be cooled externally, avoiding injecting waste heat into the optical macromodule system.
PICs may have fine tolerances in small areas, while larger geometry devices have wider tolerances. Local registration features and capabilities may be used for precisely placing the PICs. Also, placement-tolerant coupling may be used at the PIC macromodule interfaces.
In addition to inter-symbol interference caused by skew between the polarization-separated path length differences, a second skew problem exists across the overall switch: frame skew. This frame skew problem arises from the extremely short frame times used. The output data streams from each output port contain packet containers or packets with a short frame time and a very short inter-container or inter-packet gap, which may be about a nanosecond or two. The output stream contains containers or packets from multiple inputs, depending on the frame-by-frame switch cross-connection map, where each container or packet is selected by the switching process. Control loops back to the container or packet source peripherals facilitate that the containers or packets are accurately time-aligned to the switch frame at the switch inputs. Thus, if all the switch paths from all inputs to any output had zero propagation delay, the output container or packet stream would include containers or packets with the correct inter-container or inter-packet gaps, and would be aligned to the switch input frame. A fixed common amount of delay on the switch paths would cause the output to be offset in timing from the input, but the inter-container gap or inter-packet gap would not change, because the paths would have the same delay. However, if the individual path lengths through the switch are different, these path length differences lead to modulation of the inter-container gap or inter-packet gap, which may result in a reduction of the inter-container gap or inter-packet gap to the point where the destination TOR cannot distinguish the individual containers or packets or two adjacent containers or packets partially overlap each other. The tolerances may be a few centimeters across all paths within the switch, and are generated by the total path length across the switch, including the inter-macromodule interconnect. The optical macromodule may lithographically control its path lengths and to be approximately matched. However, the inter-macromodule interconnect is outside the optical macromodule. A low skew packaging and interconnect approach at the fabric level reduces skew for a fast frame time. Additional details on a packaging and interconnect scheme are further discussed in Patent Application Docket Number HW 91029929 filed on May 12, 2015, and entitled “System and Method for Photonic Structure and Switch,” which this application incorporates hereby by reference.
Table 2 shows an overview of several example photonic switch fabrics with optical macromodules. The 4096×4096 polarization-agnostic switch of
An input stage contains power splitter 734, 16 90:10 power splitters, which provide a low level of about 10 dB to about 12 dB below the input signal to the phase detector, while most of the optical power (1 dB to 1.5 dB power reduction) is passed to polarization splitter/rotator 736, 16 monolithic polarization splitters. The phase detector detects the alignment of the incoming containers to be switched with reference to the timing of the internal fabric framing clock, and generates a correction signal based on that misalignment, which is fed back to the source TOR output circuits to correct their timing, so the container received at the switch are aligned to the switch frame. The component of light passed to polarization splitter/rotator 736 is separated into two polarization planes, one of which is aligned to the PIC, and the other component orthogonal to this polarization. The orthogonal component is then rotated 90 degrees into the same plane as the first portion, leading to two optical streams with the polarization for the accurate operation of the PICs. These two optical streams are switched by silicon crosspoint switches 738, 16×32 crosspoint switches, which are controlled by PIC controllers 740. Because the switches are rectangular, they introduce 1:2 dilation. The signals are then amplified by SOAs 74, 64 SOAs, which are controlled by SOA controller 743. The SOA controllers may be fed port usage information from the PIC controllers so for real time switching of the SOAs and power consumption control and optical gain control. The amplified streams are then combined by polarization rotators/combiners 744, 32 polarization rotators and combiners. One stream is rotated ninety degrees, and then the two streams are combined, for a composite polarization agnostic output. The macromodule trace lengths may be equalized in pairs to reduce polarization skew. The macromodule trace lengths may also be more approximately globally equalized to contribute to controlling switch output port inter-container skew. Power splitters 734, polarization splitters/rotators 736, PICs 738, SOAs 742, and polarization rotators/combiners 744 are in an optical macromodule 735, along with PIC controllers 740 and SOA controller 743.
The PIC connectivity map is uploaded every frame from source matrix controller (SMC), which configures the PICs. With a directly addressable PIC, this involves controlling ever cell. On the other hand, in an indirectly addressable PIC, this involves converting the input connection map from the SMC into a cell-to-cell connection map for the PIC and applying that map to every cell in the switch. In both cases, the PIC controller is intimately connected with the PIC chip it is controller. For example, the PIC chip controller may be mounted face-to-face with the PIC chip it controls, so the optically active face of the PIC chip is bonded electrically to the active connection surface of the PIC controller chip. A well may be created in the optical macromodule substrate to accommodate the PIC controller while providing for electrical connections between the optical macromodule and the PIC controller via the PIC chip being controlled.
An SOA controller may be used to regulate the SOA current to vary the SOA gain, for example to adjust the gain to produce a specific average loss across the optical macromodule. The SOAs may be in an array or multiple smaller arrays rather than as discrete chips. These arrays draw a lot of power and produce heat, and may be cooled. SOAs may be rapidly turned on and off, for example in 500 ps, which may be less than the inter-packet gap (IPG) or inter-container gap. Because the switching path address is known, and the output ports in use are known for each switched container, only SOAs on the paths connected to active PIC output ports need to be on. Thus, the SOA controller may switch the SOAs on when they have data, and off when they do not. When a dilated switch is operating at 100% capacity, only 50% of the SOAs need to be on, and when the switch is operating at peak average traffic (30% capacity) only 15% of the SOAs are on. This reduces the power by 6:1.
The input stages 732 are coupled to center stages 752 by interconnect 748, an orthogonal optical interconnect which may be a fiber shuffle or another arrangement. A fiber shuffle introduces high path skew, and hence high output skew, which limits the size of the inter-container gap or inter-packet gap, and hence the frame speed. A low skew overall packaging approach removes this source of output skew to achieve the best performance. Additional details on a low skew packaging approach are discussed in Patent Application Docket Number 91029229US01. Each input stage is connected to each center stage. The center states contain orthogonal mapper functional block 750.
A center stage module contains polarization splitters/rotators 754, which create two optical streams at the desired polarization per input optical stream. These split streams are then switched by PIC 756, 16×16 crosspoint switches, which are controlled by PIC controllers 758. The PIC controllers use the output of center stage controller (CSC) 766 to control the PICs. The outputs are amplified by SOAs 760, which are controlled by SOA controller 764. Finally, the two sets of output streams are controlled by polarization rotators/splitters/combiners 762 to produce a composite polarization diverse output. Optical macromodule 765 contains polarization splitters/rotators 754, PICs 756, SOAs 760, and polarization rotators/combiners 762, along with PIC controllers 758 and SOA controller 764.
The outputs from center stages 752 are orthogonally coupled to output stages 768 via optical interconnect 784, which may be via a fiber shuffle or another configuration.
An output stage module contains photonic module 781 and group fan-in controller (GFC) 782, which is used to control the PICs. Optical inputs are received by polarization splitters/rotators 770, 32 monolithic polarization splitters/rotators which output two streams of the desired polarization per input stream. These streams are switched by PICs 772, two 32×16 crosspoint switches controlled by PIC controllers 774, which apply inverse dilation. The switched packet streams are amplified by SOAs 760, 32 SOAs which are controlled by SOA controller 780. Finally, the amplified switched packet streams are combined by polarization rotators/combiners 778, 16 monolithic polarization rotators/combiners to produce the final switched polarization agnostic output.
Table 3 displays an example link budget for a 256×256 polarization agnostic fast switch.
Input stage modules 1222 include optical macromodule 1224 and SMC 1242. The optical inputs are split by power splitters 1226, 32 90:10 power splitters which tap of a small portion of the optical power for phase detection, while the rest of the optical power is directed towards polarization splitters/rotators 1228. Polarization splitters/rotators 1228, 32 monolithic polarization splitters, separates the optical stream into two optical streams with orthogonal polarizations, and rotates the polarization of one of the optical streams by ninety degrees to output two optical streams with the same polarization. These optical streams are then split by power splitters 1230, 64 50:50 power splitters. The four optical streams are switched by PICs 1232, four 32×32 optical crosspoint switches controlled by PIC controllers 1234. The paths through the PIC chips are similar for low polarization skew. The macromodule trace path lengths are also matched. Because the PICs are square, the use of a 1×2 matrix within the macromodule structure with optically split inputs leads to dilation. After being switched, the optical signals are amplified by SOAs 1236, 128 polarization specific SOAs in SOA arrays controlled by SOA controller 1240. The amplified signals are combined by polarization rotators/combiners 1238, 64 monolithic polarization rotators to form polarization agnostic output optical streams.
The PIC connectivity map is uploaded every frame from the SMC to the PIC controller, which configures ever cell in the PIC switches. This may involve controlling every cell or converting the input connection map from the SMC into a cell-to-cell connection map for the PIC and applying that map to the cells in the switch. The PIC controller is mounted face-to-face with the PIC chip it controls so the optically active face of the PIC chip is electrically bonded directly to the active connections surface of the PIC controller chip. A well may be placed in the macromodule to accommodate the PIC controller and for electrical connections between the macromodule and the PIC controller to be via the PIC chip.
Input stages 1222 are orthogonally connected to center stage modules 1248 and orthogonal mapper module 1246 via optical interconnect 1244, an orthogonal interconnect, for example an optical fiber shuffle.
Center stage module 1248 includes optical macromodule 1224 and SMC 1242. The optical signals are input by polarization splitters/rotators 1252, 32 monolithic polarizations splitters/rotators which output two optical streams with the same polarization per input optical streams. These optical streams are switched by PICs 1254, 32×32 optical crosspoint switches which are controlled by PIC controllers 1256. The switched optical streams are then amplified by SOAs 1258, 64 polarization specific SOAs controlled by SOA controller 1262. Finally, the optical streams are combined by polarization rotators/combiners 1260, 32 monolithic polarization rotators/combiners. There is no dilation or macromodule capacity gain in the center stage.
The center stage modules and orthogonal mapper are orthogonally connected to output stage modules 1266 by optical interconnect 1268, which may be an orthogonal optical shuffle or another alternative providing low output skew.
The output stage modules include optical macromodule 1278 and GFC 1286. The optical signals are split and rotated by polarization splitters/rotators 1270, 64 monolithic polarization splitters/rotators, which output two optical streams with the same polarization per input optical stream. These streams are switched by PICs 1272, four 32×32 optical crosspoint switches controlled by PIC controllers 1274. The switched optical signals are combined by power combiners 1276, 64 power combiners. Then, the optical signals are amplified by SOAs 1280, 64 polarization specific SOAs controlled by SOA controllers 1284. Finally, the optical signals are combined by polarization rotators/combiners 1282, 32 monolithic polarization rotators/combiners, to output a polarization agnostic optical signal. Inverse dilation is performed in the output stage.
Table 4, below, illustrates an example link budget for an example 1024×1024 polarization agnostic photonic switch.
There are 64 input stages 1732 with optical macromodule 1734 and SMC 1752. In the input stage there is a 4×1 or 2×2 macromodule array for a 2:1 capacity gain and 1:2 dilation. Portions of the input optical signals are tapped off for phase detection by power splitters 1736, 64 90:10 optical power splitters. The optical signals are polarization split and rotated by polarization splitters/rotators 1738, 128 monolithic polarization splitters/rotators which output two optical streams having the same polarization. These optical streams are further split by power splitters 1740, 128 four way power splitters. The optical signals are switched by PICs 1742, eight 64×32 crosspoint optical switches controlled by PIC controllers 1744. The signals are then amplified by SOAs 1746, 256 single polarization SOAs controlled by SOA controller 1750. Next, the optical signals are combined by polarization rotator/combiners 1748, 128 monolithically integrated polarization rotators/combiners.
The input stage modules are orthogonally connected to center stage modules 1758, 128 center stage modules, and to orthogonal mapper 1756 by optical interconnect 1754, for example a fiber shuffle.
The center stage modules include optical macromodule 1760 and CSC 1776. No dilation is applied in the center stage modules. The input optical signals are polarization split and rotated by polarization splitters/rotators 1762, 64 monolithic devices, to produce two optical streams with the same polarization. These optical streams are further split by power splitters 1764, 128 50:50 power splitters. Then, the optical streams are switched by PICs 1766, eight 32×32 optical crosspoint switches organized as a pair of 2×2 arrays controlled by PIC controllers 1768. The optical signals are combined by power combiners 1772 and by polarization rotators/combiners 1774. The switched optical signals are then amplified by SOAs 1770, 128 single polarization SOAs controlled by SOA controller 1761.
The 128 center stage modules and the orthogonal mapper are orthogonally connected to output stages 1780, 64 output stage modules, by optical interconnect 1778, for example a fiber shuffle or a low skew solution.
In an output stage module, with GFC 1796 and optical macromodule 1782, receives the optical signals output by the center stage modules. Inverse dilation is performed by the output stage modules. The optical inputs are polarization split and rotated by polarization splitters/rotators 1784 which output two optical streams with the same polarization. The optical streams are switched by PICs 1786, eight 32×64 PICs controlled by PIC controllers 1788. The optical signals are combined by power combiners 1790, 128 four way power combiners. Then, the optical signals are amplified by SOAs 1792, 128 SOAs, which are controlled by SOA controller 1798. Finally, the polarization agnostic optical streams are output by polarization rotators/combiners 1794 which combine the polarization streams.
Table 5 illustrates an example link budget for a 4096×4096 polarization agnostic photonic switch.
Another implementation of a 4096×4096 polarization-agnostic photonic switch fabric uses 32×32 PICs and doubles the number of PICs on the input stage and output stage macromodules. However, the PIC count on the macromodule is high, which may use a high yield for the precision production PIC mounting approach.
Table 6 displays some characteristics of input stage modules, Table 7 displays some characteristics of center stage modules, Table 8 displays some characteristics of output stage modules, and Table 9 displays some loss characteristic for large photonic switches. Substrate monolithic optical component include power splitters and combiners and polarization splitters and components. Hybridized optical components include PICs and SOA, listed as single SOAs. However, SOAs may be in arrays, for example of 8 or 16 SOAs per array, substantially reducing the number of hybridized optical components. Hybridized electronic components include SOA controllers and PIC controllers.
Delays in separate polarization paths are designed to be similar, for example within 200 μm to 400 μm for 100 Gb/s or 800 μm to 1.6 mm at 25 Gb/s. In some examples, power splitting occurs before polarization splitting to reduce the polarization skew. In another example, polarization splitting occurs on the PIC to further reduce the polarization delay. However, placing two switching matrices on a single PIC along with polarization splitters, combiners, and rotators more than doubles the die size or halves the PIC port count for the same die size.
Table 10 discusses the estimated die size for single polarization PIC switching matrices with HDBE and EAS topology. Using EAS increases the die size. Using two switches plus polarization splitters, rotators, and combiners increases the die size. Table 17 shows the die sizes for polarization agnostic HDBE switching matrices. Table 18 shows a comparison of PIC counts for macromodules with various PICs and different switching port counts.
Table 11 shows that HDBE PICs may be designed in silicon up to 64×64 port parts before reaching 25×32 mm. However, directly addressable and totally non-blocking EAS parts are limited to 32×32 before reaching 25×32 mm.
Table 12 shows that the size of a polarization agnostic chip is approaching that of a single polarization part of twice the port count.
Hence, for any given die size limit the capacity of a polarization-agnostic part is one half of that of a single polarization part, requiring four parts in a 2×2 array to match the capacity of a PIC in a single polarization implementation. However, two of those single polarization PICs plus external macromodule polarization components can yield the same size of polarization agnostic switch. Thus, placing the polarization components on the macromodule reduces the PIC count by a factor of 2.
Table 13 shows estimated component footprint allocations for hybridized and monolithic components used in macromodules, which includes an overhead interconnect allocation for each device.
Table 14 shows the area for input stage macromodules for 1024×1024 and 4096×4096 switches, Table 15 shows a the area for the center stage macromodules for 1024×1024 and 4096×4096 switches, and Table 16 shows a the area for the output stage macromodules for 1024×1024 and 4096×4096 switches. The photonically functional active areas, including interconnect, ranges from about 602 square mm to about 11,692 square mm, corresponding to about 25 mm per side up to 108 mm per side. These sizes are compatible with large area silica on silicon substrate processing, such as complex silica based high port count array waveguide grating (AWG) fabrication.
PICs may be assembled into an N×M array on the macromodule. A 2×2 matrix has two rows of PICs and two columns of PICs with the PICs in a row having inputs connected to the same source as the same inputs on the other PIC(s) in the row using an optical power splitter, while the PICs in each column have each of their outputs connected to the same output of the other PICs in the column using an optical combiner. This creates a directly addressable non-blocking switching module having the same addressing characteristics as the constituent PICs. The capacity of the switching core is N times the input port count of the individual PIC and M times the output port capacity of the individual PICs. Table 24 shows the macromodule core switching capacity as a function of core configuration.
In step 274, one of the optical streams is switched, for example by a PIC, for example a semiconductor crosspoint switch.
Then, this switched optical stream is amplified in step 276, for example by an SOA or EDWA.
Next, in step 279, the polarization of the amplified optical stream is rotated, for example by ninety degrees.
In step 277, the polarization of the other optical stream is rotated, for example by ninety degrees.
In step 278, the other optical stream is switched. Next, in step 280, this switched optical stream is amplified.
Finally, in step 282, these two switched and amplified optical streams are polarization rotated and combined. One of the optical streams is polarization rotated by ninety degrees, and the streams are combined to form an output optical stream.
An embodiment photonic device includes an optical macromodule substrate including optical interconnects and a first photonic integrated circuit (PIC) including a first photonic switch, where the first PIC is mechanically coupled to the optical macromodule substrate and optically coupled to the optical interconnect. The photonic device also includes a PIC controller electrically coupled to the first PIC.
The embodiment also includes a second PIC comprising a second photonic switch, where the second PIC is mechanically coupled to the optical macromodule substrate and optically coupled to the optical interconnect. In one example, the optical macromodule substrate further includes an optical polarization splitter/rotator, where the optical polarization splitter/rotator is optically coupled to the first PIC and the second PIC. In another example, the optical macromodule substrate further includes an optical polarization rotator/combiner, where the optical polarization rotator/combiner is optically coupled to the first PIC and the second PIC. An additional embodiment includes a square array or a non-square array of PICs, including the first PIC and the second PIC. For example, if the square array comprises the first PIC and the second PIC, the macromodule has M inputs, where the first PIC has a port count of P, where M=N*P, and where the square array of PICs is an N×N array of PICs.
In an embodiment, the optical macromodule substrate further includes an optical power splitter, where the optical power splitter is optically coupled to the first PIC and an optical power combiner, where the optical power combiner is optically coupled to the first PIC.
A further embodiment includes a semiconductor optical amplifier (SOA) mechanically and optically coupled to the macromodule substrate and an SOA controller mechanically and electrically coupled to the SOA. For example, the SOA controller is configured to turn the SOA off when the SOA is not transmitting an optical packet. In another example, the SOA controller is configured to receive output port utilization information from the PIC controller.
In an additional embodiment, the first PIC has an active surface, where the PIC controller has an active surface, and where the active surface of the PIC controller is disposed on the active surface of the first PIC.
In another embodiment, the optical macromodule substrate has a well or aperture, where the PIC controller is in the well, and where a first surface of the PIC controller is level with a top of the optical macromodule substrate.
In an embodiment, the optical macromodule further includes an optical coupler, where the optical coupler is configured to optically couple the optical macromodule to an external optical device.
An embodiment photonic switch includes an input stage including a first optical including a first photonic integrated circuit (PIC) switch and a second optical macromodule including a second PIC switch. The photonic switch also includes a center stage including a third optical macromodule including a third PIC switch, where the third optical macromodule is optically coupled to the first optical macromodule and the second optical macromodule and a fourth optical macromodule including a fourth PIC switch, where the fourth optical macromodule is optically coupled to the first optical macromodule and the second optical macromodule. Additionally, the photonic switch includes an output stage including a fifth optical macromodule including a fifth PIC switch, where the fifth optical macromodule is optically coupled to the third optical macromodule and the fourth optical macromodule and a sixth optical macromodule including a sixth PIC switch, where the sixth optical macromodule is optically coupled to the third optical macromodule and the fourth optical macromodule.
In a further embodiment, the first optical macromodule further includes a seventh PIC, where the second optical macromodule further includes an eighth PIC, where the third optical macromodule further includes a ninth PIC, where the fourth optical macromodule further includes a tenth PIC, where the fifth PIC further includes an eleventh PIC, and where the sixth PIC further includes a twelfth PIC.
In an embodiment, the first macromodule further includes a first polarization splitter optically coupled to the first PIC and to the seventh PIC and a first polarization combiner optically coupled to the first PIC and to the seventh PIC, and where the second macromodule further includes a second polarization splitter optically coupled to the second PIC and to the eighth PIC and a second polarization combiner optically coupled to the second PIC and to the eighth PIC. Also, in this embodiment a semiconductor optical amplifier (SOA) is coupled between the first polarization splitter and the polarization combiner.
In an additional embodiment, the center stage further includes a center stage controller electrically coupled to the third optical macromodule.
In another embodiment, the photonic switch is a three stage Clos photonic switch.
An embodiment method includes receiving an input optical stream and producing a first split optical stream having a first polarization and a second split optical stream having the first polarization from the input optical stream by a polarization splitter/rotator. The method also includes switching the first split optical stream to produce a first switched optical stream by a first optical switch and amplifying the first switched optical stream to produce a first amplified optical stream by a first amplifier. Additionally, the method includes switching the second optical stream to produce a second switched optical stream by a second optical switch and amplifying the second switched optical stream to produce a second amplified optical stream by a second amplifier. Also, the method includes combining the first amplified optical stream and the second amplified optical stream to produce a polarization agnostic optical stream by a polarization rotator/combiner.
In an embodiment, a first path from the polarization splitter/rotator through the first optical switch and the first optical amplifier to the polarization rotator has a first distance, where a second path from the polarization splitter/rotator through the second optical switch and the second optical amplifier to the polarization rotator has a second distance, and where the first distance is within 2 mm of the second distance.
While several embodiments have been provided in the present disclosure, it should be understood that the disclosed systems and methods might be embodied in many other specific forms without departing from the spirit or scope of the present disclosure. The present examples are to be considered as illustrative and not restrictive, and the intention is not to be limited to the details given herein. For example, the various elements or components may be combined or integrated in another system or certain features may be omitted, or not implemented.
In addition, techniques, systems, subsystems, and methods described and illustrated in the various embodiments as discrete or separate may be combined or integrated with other systems, modules, techniques, or methods without departing from the scope of the present disclosure. Other items shown or discussed as coupled or directly coupled or communicating with each other may be indirectly coupled or communicating through some interface, device, or intermediate component whether electrically, mechanically, or otherwise. Other examples of changes, substitutions, and alterations are ascertainable by one skilled in the art and could be made without departing from the spirit and scope disclosed herein.
