Patent Application
20050223118
1. Field of the Invention
This invention relates to network interfaces and more particularly to the direct placement of RDMA payload into processor memory.
2. Discussion of Related Art
Implementation of multi-tiered architectures, distributed Internet-based applications, and the growing use of clustering and grid computing is driving an explosive demand for more network and system performance, putting considerable pressure on enterprise data centers.
With continuing advancements in network technology, particularly 1 Gbit and 10 Gbit Ethernet, connection speeds are growing faster than the memory bandwidth of the servers that handle the network traffic. Combined with the added problem of ever-increasing amounts of data that need to be transmitted, data centers are now facing an “I/O bottleneck”. This bottleneck has resulted in reduced scalability of applications and systems, as well as, lower overall systems performance.
There are a number of approaches on the market today that try to address these issues. Two of these are leveraging TCP/IP offload on Ethernet networks and deploying specialized networks. A TCP/IP Offload Engine (TOE) offloads the processing of the TCP/IP stack to a network coprocessor, thus reducing the load on the CPU. However, a TOE does not completely reduce data copying, nor does it reduce user-kernel context switching—it merely moves these to the coprocessor. TOEs also queue messages to reduce interrupts, and this can add to latency.
Another approach is to implement specialized solutions, such as InfiniBand, which typically offer high performance and low latency, but at relatively high cost and complexity. A major disadvantage of InfiniBand and other such solutions is that they require customers to add another interconnect network to an infrastructure that already includes Ethernet and, oftentimes, Fibre Channel for storage area networks. Additionally, since the cluster fabric is not backwards compatible with Ethernet, an entire new network build-out is required.
One approach to increasing memory and I/O bandwidth while reducing latency is the development of Remote Direct Memory Access (RDMA), a set of protocols that enable the movement of data from the memory of one computer directly into the memory of another computer without involving the operating system of either system. By bypassing the kernel, RDMA eliminates copying operations and reduces host CPU usage. This provides a significant component of the solution to the ongoing latency and memory bandwidth problem.
Once a connection has been established, RDMA enables the movement of data from the memory of one computer directly into the memory of another computer without involving the operating system of either node. RDMA supports “zerocopy” networking by enabling the network adapter to transfer data directly to or from application memory, eliminating the need to copy data between application memory and the data buffers in the operating system. When an application performs an RDMA Read or Write request, the application data is delivered directly to the network, hence latency is reduced and applications can transfer messages faster (see
RDMA reduces demand on the host CPU by enabling applications to directly issue commands to the adapter without having to execute a kernel call (referred to as “kernel bypass”). The RDMA request is issued from an application running on one server to the local adapter and then carried over the network to the remote adapter without requiring operating system involvement at either end. Since all of the information pertaining to the remote virtual memory address is contained in the RDMA message itself, and host and remote memory protection issues were checked during connection establishment, the remote operating system does not need to be involved in each message. The RDMA-enabled network adapter implements all of the required RDMA operations, as well as, the processing of the TCP/IP protocol stack, thus reducing demand on the CPU and providing a significant advantage over standard adapters (see
Several different APIs and mechanisms have been proposed to utilize RDMA, including the Direct Access Provider Layer (DAPL), the Message Passing Interface (MPI), the Sockets Direct Protocol (SDP), iSCSI extensions for RDMA (iSER), and the Direct Access File System (DAFS). In addition, the RDMA Consortium proposes relevant specifications including the SDP and iSER protocols and the Verbs specification (more below). The Direct Access Transport (DAT) Collaborative is also defining APIs to exploit RDMA. (These APIs and specifications are extensive and readers are referred to the relevant organizational bodies for full specifications. This description discusses only select, relevant features to the extent necessary to understand the invention.)
In the exemplary arrangement, the direct data placement protocol (DDP) layer is responsible for direct data placement. Typically, this layer places data into a tagged buffer or untagged buffer, depending on the model chosen. In the tagged buffer model, the location to place the data is identified via a steering tag (STag) and a target offset (TO), each of which is described in the relevant specifications, and only discussed here to the extent necessary to understand the invention.
Other layers such as RDMAP extend the functionality and provide for things like RDMA read operations and several types of writing tagged and untagged data.
The behavior of the RNIC (i.e., the manner in which uppers layers can interact with the RNIC) is a consequence of the Verbs specification. The Verbs layer describes things like (1) how to establish a connection, (2) the send queue/receive queue (Queue Pair or QP), (3) completion queues, (4) memory registration and access rights, and (5) work request processing and ordering rules.
A QP includes a Send Queue and a Receive Queue, each sometimes called a work queue. A Verbs consumer (e.g., upper layer software) establishes communication with a remote process by connecting the QP to a QP owned by the remote process. A given process may have many QPs, one for each remote process with which it communicates.
Sends, RDMA Reads, and RDMA Writes are posted to a Send Queue. Receives are posted to a Receive Queue (i.e., receive buffers with data that are the target for incoming Send messages). Another queue called a Completion Queue is used to signal a Verbs consumer when a Send Queue WQE completes, when such notification function is chosen. A Completion Queue may be associated with one or more work queues. Completion may be detected, for example, by polling a Completion Queue for new entries or via a Completion Queue event handler.
The Verbs consumer interacts with these queues by posting a Work Queue Element (WQE) to the queues. Each WQE is a descriptor for an operation. Among other things, it contains (1) a work request identifier, (2) operation type, (3) scatter or gather lists as appropriate for the operation, (4) information indicating whether completion should be signaled or unsignalled, and (5) the relevant STags for the operation, e.g., RDMA Write.
Logically, a STag is a network-wide memory pointer. STags are used in two ways: by remote peers in a Tagged DDP message to write data to a particular memory location in the local host, and by the host to identify a contiguous region of virtual memory into which Untagged DDP data may be placed.
There are two types of memory access under the RDMA model of memory management: memory regions and memory windows. Memory regions are page aligned buffers, and applications may register a memory region for remote access. A region is mapped to a set of (not necessarily contiguous) physical pages. Specified Verbs (e.g., Register Shared Memory Region) are used to manage regions. Memory windows may be created within established memory regions to subdivide that region to give different nodes specific access permissions to different areas.
The Verbs specification is agnostic to the underlying implementation of the queuing model.
The invention provides a system and method for placement of sharing physical buffer lists in RDMA communication.
According to one aspect of the invention, a network adapter system for use in a computer system includes a host processor and host memory and is capable for use in network communication in accordance with a direct data placement (DDP) protocol. The DDP protocol specifies tagged and untagged data movement into a connection-specific application buffer in a contiguous region of virtual memory space of a corresponding endpoint computer application executing on said host processor. The DDP protocol specifies the permissibility of memory regions in host memory and specifies the permissibility of at least one memory window within a memory region. The memory regions and memory windows have independently definable application access rights, the network adapter system includes adapter memory and a plurality of physical buffer lists in the adapter memory. Each physical buffer list specifies physical address locations of host memory corresponding to one of said memory regions. A plurality of steering tag records are in the adapter memory, each steering tag record corresponding to a steering tag. Each steering tag record specifies memory locations and access permissions for one of a memory region and a memory window. Each physical buffer list is capable of having a one to many correspondence with steering tag records such that many memory windows may share a single physical buffer list.
According to another aspect of the invention, each steering tag record includes a pointer to a corresponding physical buffer list.
In the Drawing,
Preferred embodiments of the invention provide a method and system that efficiently places the payload of RDMA communications into an application buffer. The application buffer is contiguous in the application's virtual address space, but is not necessarily contiguous in the processor's physical address space. The placement of such data is direct and avoids the need for intervening bufferings. The approach minimizes overall system buffering requirements and reduces latency for the data reception.
For purposes of understanding this invention, further detail about the message queue subsystem 406 is not needed. However, this subsystem is described in co-pending U.S. patent application Ser. Nos. <to be determined>, filed on even date herewith, entitled SYSTEM AND METHOD FOR WORK REQUEST QUEUING FOR INTELLIGENT ADAPTER and SYSTEM AND METHOD FOR PLACEMENT OF RDMA PAYLOAD INTO APPLICATION MEMORY OF A PROCESSOR SYSTEM, which are incorporated herein by reference in their entirety.
The processors are partitioned as a host processor 504 and network processor 508. The host processor 504 is used to handle host interface functions and the network processor 508 is used to handle network processing. Processor partitioning is also reflected in the attachment of on-chip peripherals to processors. The host processor 504 has interfaces to the host 400 through memory-mapped message queues 502 and PCI interrupt facilities while the network processor 508 is connected to the network processing hardware 512 through on-chip memory descriptor queues 510.
The host processor 504 acts as command and control agent. It accepts work requests from the host and turns these commands into data transfer requests to the network processor 508.
For data transfer, there are three work request queues, the Send Queue (SQ), Receive Queue (RQ), and Completion Queue (CQ). The SQ and RQ contain work queue elements (WQE) that represent send and receive data transfer operations (DTO). The CQ contains completion queue entries (CQE) that represent the completion of a WQE. The submission of a WQE to an SQ or RQ and the receipt of a completion indication in the CQ (CQE) are asynchronous.
The host processor 504 is responsible for the interface to host. The interface to the host consists of a number of hardware and software queues. These queues are used by the host to submit work requests (WR) to the adapter 402 and by the host processor 504 to post WR completion events to the host.
The host processor 504 interfaces with the network processor 508 through the inter-processor queue (IPCQ) 506. The principle purpose of this queue is to allow the host processor 504 to forward data transfer requests (DTO) to the network processor 508 and for the network processor 508 to indicate the completion of these requests to the host processor 504.
The network processor 508 is responsible for managing network I/O. DTO work requests (WRs) are submitted to the network processor 508 by the host processor 504. These WRs are converted into descriptors that control hardware transmit (TXP) and receive (RXP) processors. Completed data transfer operations are reaped from the descriptor queues by the network processor 508, processed, and if necessary DTO completion events are posted to the IPCQ for processing by the host processor 504.
Under a preferred embodiment, the bus 404 is a PCI interface. The adapter 404 has its Base Address Registers (BARs) programmed to reserve a memory address space for a virtual message queue section.
Preferred embodiments of the invention provide a message queue subsystem that manages the work request queues (host→adapter) and completion queues (adapter→host) that implement the kernel bypass interface to the adapter. Preferred message queue subsystems:
With reference to
Support for standard sockets applications is provided through the native stack. To accomplish this, the adapter looks look like two Ethernet ports to the host. One virtual port (and MAC address) is used for RDMA/TOE data and another virtual port (and MAC address) is used for compatibility mode data. Ethernet frames that arrive at the RDMA/TOE MAC address are delivered via an RNIC Verbs like interface, while frames that arrive at the other MAC address are delivered via a network-adapter like interface.
Network packets are delivered to the native or RDMA interface per the following rules:
Compatibility mode places network data through a standard dumb-Ethernet interface to the host. The interface is a circular queue of descriptors that point to buffers in host memory. The format of this queue is identical to the queue used to place protocol headers and local data for RDMA mode packets. The difference is only the buffer addresses specified in the descriptor. The compatibility-mode receive queue (HRXDQ) descriptors point to host memory, while the RDMA mode queue (RXDQ) descriptors point to adapter memory.
RDMA/TOE Mode data is provided to the host through an RNIC Verbs-like interface. This interface is implemented in a host device driver.
The NetPPC processor manages the mapping of device driver verbs to RXP hardware commands. This description is principally concerned with the definition of the RXP hardware interface to the NetPPC.
The RXDQ BRAM 602 interface provides the control and status information for reception of fast-path data traffic. Through this interface, the RXP reads the valid RXD entries formulated by the NetPPC and updates the status after receiving each data packet in fast-path mode.
HRXDQ BRAM interface 604 provides the control and status information for reception of host-compatible data traffic. Through this interface, the RXP reads the valid HRXD entries formulated by the NetPPC and updates the status after receiving each data packet in host-compatible mode.
The hash interface 606 is used in connection with identifying a placement record from a corresponding collection of such. Under certain embodiments a fixed size index is created with each index entry corresponding to a hash bucket. Each hash bucket in turn corresponds to a list of placement records. A hashing algorithm creates an index identification by hashing the 4-tuple of network ip addresses and port identifications for the sender and recipient. The bucket is then traversed to identify a placement record having the corresponding, matching addresses and port identifications. In this fashion, network addresses and ports may be used to time and space efficiently locate a corresponding placement record. The placement records (as will be described below) are used to directly store message payload in host application buffers.
The GMAC core interface 608 receives data 8 bits at a time from the network.
The PCI/PLB interface 610 provides the channel to store received data into host memory and/or local data memory as one or multiple data segments.
The RcvFIFO write process module 612 controls the address and write enable to the RcvFIFO 614. It stores data 8 bits at a time into the RcvFIFO from the network. If the received packet is aborted due to CRC or any other network errors, this module aborts the current packet reception, flushes the aborted packet from RcvFIFO, and resets all receive pointers for next incoming packet. Once a packet is loaded into the data buffer, it updates a packet valid flag to the RcvFIFO read process module
The RcvFIFO 614 is 40 Kbytes deep, and this circular ring buffer is efficient to store maximum number of packets. The 40 Kbytes is needed to store enough maximum packets in case that lossless traffic and flow control are required. This data buffer is 8 bits wide on the write port and 64 bit wide on the read port. The packet length and other control information for each packet are stored in the corresponding entries in the control FIFO. Flow control and discard policy are implemented to avoid FIFO overflow.
The CtrlFIFO write process module 616 controls the address and write enable to the CtrlFIFO 618. It stores the appropriate header fields into CtrlFIFO and processes each header to identify the packet type. This module decodes the Ethernet MAC address to determine the fast-path or host-compatible data packets. It also identifies multicast and broadcast packets. It checks the IP/TCP header and validates MPA CRCs. Once a header is loaded into the control FIFO, it updates the appropriate valid flags to the CtrlFIFO. This module controls a 8 bit date interface to the control FIFO.
The CtrlFIFO 618 is 4 Kbytes deep. Each entry is 64 bytes and contains header information for each corresponding packet stored in the RcvFIFO. This data buffer is 8 bits wide on the write port and 64 bit wide on the read port. Flow control and discard policy are implemented to avoid FIFO overflow.
The Checksum Process module 619 is used to accumulate both IP and TCP checksums. It compares the checksum results to detect any IP or TCP errors. If errors are found, the packet is aborted and all FIFO control pointers are adjusted to the next packet.
The RcvPause process module 620 is used to send flow control packets to avoid FIFO overflows and achieve lossless traffic performance. It follows the 802.3 flow control standards with software controls to enable or disable this function.
The RcvFIFO read process module 622 reads 64 bit data words from RcvFIFO 614, and sends the data stream to PCI or PLB interface 610. This module processes data packets stored in the RcvFIFO 614 in a circular ring to keep the received data packet in order. If the packet is aborted due to network errors, it flushes the packet and updates all control pointers to next packet. After a packet is received and stored in host or local memory, it frees up the data buffer by sends the completion indication to RcvFIFO write process module.
The CtrlFIFO read process module 624 reads 64 bit control words from the CtrlFIFO 618, and examines the control information for each packet to determine its appropriate data path and its packet type. This module processes header information stored in the CtrlFIFO and it reads one entry at a time to keep the received packet in order. If the packet is aborted due to network errors, it updates the control fields of the packet and adjusts pointers to next header entry. After a packet is received and stored in host or local memory, it goes to the next header entry in the control FIFO and repeats the process.
The RXP Main process module 626 takes the control and data information from both RcvFIFO read proc 622 and CtrlFIFO read proc 624, and starts the header and payload transfers to PLB and/or PCI interface 610. It also monitors the readiness of RXDQ and HRXDQ entries for each packet transfer, and updates the completion to RXD and HRXD based on the mode of operation. This module initiates the DMA requests to PLB or PCI for single or multiple data transfers for each received packet. It performs all tables and record lookups to determine the type of operation required for each packet, and operations include hash table search, placement record read, UTRXD lookup, stag information retrieval, PCI address lookup and calculation.
The RXDQ process module 628 is responsible for requesting RXD entry for each incoming packet in fast-path, multicast and broadcast modes. At the end of the packet reception, it updates the flag and status fields in the RXD entry.
The HRXDQ process module 630 is responsible for requesting HRXD entry for each incoming packet in host compatible and broadcast modes. At the end of the packet reception, it updates the flag and status fields in the HRXD entry.
There are two RDMA data placement modes: local mode, and direct mode. In local mode, network packets are placed entirely in the buffer provided by an RXD. In direct mode, protocol headers are placed in the buffer provided by an RXD, but the payload is placed in host memory through a per-connection table as described blow.
In direct mode, there are two classes of data placement: untagged, and tagged. Untagged placement is used for RDMA Send, Send and Invalidate, Send with Solicited Event and Send and Invalidate with Solicited Event messages. Tagged placement is used to place RDMA Read Request, and RDMA Write messages.
The different modes define which tables are consulted by the RXP when placing incoming data.
The block arrows illustrate the functionality supported by the data structures to which they point. The HostCPU 702, for example uses the HRXDQ 630 to receive compatibility mode data from the interface. The fine arrows in the figure indicate memory pointers. The data structures in the figure are contained in either SDRAM or block RAM depending on their size and the type and number of hardware elements that require access to the tables.
At the top of the diagram are the Host CPU 702, NetPPC 508, and HostPPC 504. The Host CPU is responsible for scrubbing the HRXDQ 630 that contains descriptors pointing to host memory locations where receive data has been placed for the compatibility interface.
The NetPPC 508 is responsible for protocol processing, connection management and Receive DTO WQE processing. Protocol processing involves scrubbing the RXDQ 628 that contains descriptors pointing to local memory where packet headers and local mode payload have been placed.
Connection Management involves creating Placement Records 704 and adding them to the Placement Record Hash Table 706 that allows the RXP 512 to efficiently locate per-session connection data and per-session descriptor queues. Receive DTO WQE processing involves creating UTRXDQ descriptors 708 (Untagged Receive Descriptor Queue) for untagged data placement, and completing RQ WQE when the last DDP message is processed from the RXDQ.
The HostPPC 504 is responsible for the bulk of Verbs processing to include Memory Registration. Memory Registration involves the creation of STag 710, STag Records 712 and Physical Buffer Lists (PBLs) 714. The STag is returned to the host client when the memory registration verbs are completed and are submitted to the adapter in subsequent Send and Receive DTO requests.
The hardware client of these data structures is the RXP 512. The principle purpose of these data structures, in fact, is to guide the RXP in the processing of incoming network data. Packets arriving with the Compatibility Mode MAC address are placed in host memory using descriptors obtained from the HRXDQ. These descriptors are marked as “used” by setting bits in a Flags field in the descriptor.
Any packet that arrives at the RDMA MAC address will consume some memory in the adapter. The RXDQ 628 contains descriptors that point to local memory. One RXD from the RXDQ will be consumed for every packet that arrives at the RDMA MAC interface. The protocol header, the payload, or both are placed in local memory.
The RXP 512 performs protocol processing to the extent necessary to perform data placement. This protocol processing requires keeping per-connection protocol state, and data placement tables. The Placement Record Hash Table 706, Placement Record 704 and UTRXDQ 708 keep this state. The Placement Record Hash Table provides a fast method for the RXP 512 to locate the Placement Record for a given connection. The Placement Record itself keeps the connection information necessary to correctly interpret incoming packets.
Untagged Data Placement is the process of placing Untagged DDP Message payload in host memory. These memory locations are specified per-connection by the application and kept in the UTRXDQ. An Untagged Receive Descriptor contains a scatter gather list of host memory buffers that are available to place an incoming Untagged DDP message.
Finally, the RXP is responsible for Tagged Mode data placement. In this mode, an STag is present in the protocol header. This STag 710 points to an STag Record 712 and PBL 714 that are used to place the payload for these messages in host memory. The RXP 512 ensures that the STag is valid in part by comparing fields in the STag Record 712 to fields in the Placement Record 704.
The table below provides a detailed description of each of the tables in the diagram.
The Host Receive Descriptor Queue 630 is a circular queue of host receive descriptors (HRXD). The base address of the queue is 0xFB00—0000 and the length is 0x1000 bytes.
A Host 702 populates the queue with HRXD 802 that specify host memory buffers 804 to receive network data. Each buffer specified by an HRXD must be large enough to hold the largest packet. That is, each buffer must be at least as large as the maximum transfer unit size (MTU).
When the RXP 512 has finished placing the network frame in a buffer, it updates the appropriate fields in the HRXD 802 to indicate byte counts 806 and status information 808, updates the FLAGS field 810 of the HRXD to indicate the completion status, and interrupts the Host to indicate that data is available.
More specifically, under preferred embodiments, the format of an HRXD 802 is as follows:
Coordination between the Host 702 and the RXP 512 is achieved with the RXD_READY and RXD_DONE bits in the Flags field 810. The Host and the RXP each keep a head index into the HRXDQ. To initialize the system, the Host sets the ADDR 812 and LEN fields 814 to point to buffers 804 in host memory 801 as shown in
The Host keeps a “head” index into the HRXDQ 630. When the FLAGS field 810 of the HRXD at the head index is RXD_DONE, the Host 702 processes the network data as appropriate, and when finished marks the descriptor as available by setting the RXD_READY bit. The Host increments the head index (wrapping as needed) and starts the process again.
Similarly, the RXP 512 keeps a head index into the HRXDQ 630. If the FLAGS field 810 of the HRXD at the head index is not RXD_READY, the RXP waits, accumulating data in the receive FIFO 614. Data arriving after the FIFO has filled will be dropped.
When the RXD_READY bit is set, the RXP 512 places the next arriving frame into the address at ADDR 812 (up to the length specified by LEN 814 ). When finished, the RXP sets the RXD_DONE bit and increments its head index (wrapping as needed). The RXP interrupts the host if
The Receive Descriptor Queue 628 is a circular queue of receive descriptors (RXD). The address of the queue is 0xFC00_E000 and the queue is 0x800 bytes deep.
The NetPPC 508 populates the receive descriptor queue 628 with RXD 902 that specify buffers 904 in local adapter memory 906 to receive network data. Each buffer 904 specified by an RXD 902 must be large enough to hold the largest packet. That is, each buffer must be at least as large as the MTU.
When the RXP 512 has finished placing the network frame, it updates the appropriate fields in the RXD to indicate byte counts 908 and status information 910 and then updates the Flags field 912 of the RXD to indicate the completion status.
More specifically, under preferred embodiments, the format of an RXD-Receive Descriptor, is as follows:
Coordination between the NetPPC 508 and the RXP 512 is achieved with the RXD_READY and RXD_DONE bits in the Flags field 912. The NetPPC and the RXP keep a head index into the RXDQ. To initialize the system, the NetPPC sets the Addr 914 and Len fields 916 to point to buffers in PLB SDRAM 906 as shown in
The NetPPC 508 keeps a “head” index into the RXDQ 628. When the Flags field 912 of the RXD at the head index is RXD_DONE, the NetPPC processes the network data as appropriate, and when finished marks the descriptor as available by setting the RXD_READY bit. The NetPPC increments the head index (wrapping as needed) and starts the process again.
Similarly, the RXP 512 keeps a head index into the RXDQ 628. If the Flags field 912 of the RXD 902 at the head index is not RXD_READY, the RXP drops all arriving packets until the bit is set. When the RXD_READY bit is set, the RXP places the next arriving frame into the address at Addr 914 (up to the length specified by Len 916 ) as described in a later section. When finished, the RXP sets the RXD_DONE bit, increments its head index (wrapping as needed) and continues with the next packet.
Untagged and tagged data placement use connection specific application buffers to contain network payload. The adapter copies network payload directly into application buffers in host memory. These buffers are described in tables attached to a Placement Record 704 located in a Hash Table (HT) 706 as shown in
The HT 706 is an array of pointers 707 to lists of placement records. Under certain embodiments, the hash index is computed as follows:
The algorithm for locating the data placement record follows:
The contents of a Placement Record 704 are as follows:
The UTRXDQ 708 is an array of UTRXD used for the placement of Untagged DDP messages. This table is only used if the RDMA_MODE bit is set in the Placement Record 704. An untagged data receive descriptor (UTRXD) contains a Scatter Gather List (SGL) that refers to one or more host memory buffers. (Thus, though the host memory is virtually contiguous, it need not be physically contiguous and the SGL supports non-contiguous placement in physical memory.) Network data is placed in these buffers in order from first to last until the payload for the DDP message has been placed.
The NetPPC 508 populates the UTRXDQ 708 when the connection is established and the Placement Record 704 is built. The number of elements in the UTRXDQ varies for each connection based on parameters specified by the host 702 and messages exchanged with the remote RDMAP peer. The UTRXDQ 708 and the UTRXD are allocated by the NetPPC 508. The base address of the UTRXDQ is specified in the placement record. If there are no UTRXD remaining in the queue 708 when a network packet arrives for the connection, the packet is placed locally in adapter memory.
The table below illustrates a preferred organization for an untagged receive data descriptor (UTRXD).
The table below illustrates a preferred organization for an entry in the scatter gather list (SGE).
Connection setup and tear down is handled by software. After the connection is established, the firmware creates a Placement Record 704 and adds the Placement Record to the Hash Table 706. Immediately following connection setup, the protocol sends an MPA Start Key and expects an MPA Start Key from the remote peer. The MPA Start Key has the following format:
Following MPA (Marker PDU Architecture) protocol initialization, the RDMAP protocol expects a single MPA PDU containing connection private data. If no private data is specified at connection initialization, a zero length MPA PDU is sent. The RDMAP protocol passes this data to the DAT client as connection data.
Given the connection data, the client configures the queue pairs QP and binds the QP to a TCP endpoint. At this point, the firmware transitions the Placement Record to RDMA Mode by setting the RDMA_ENABLE bit in the Placement Record.
When the firmware inserts a Placement Record 704 into the Hash Table 706 it must first set the NextPtr field 716 of the new Placement Record to the value in the Hash Table bucket, and then set the Hash Table bucket pointer to point to the new Placement Record. A race occurs between the time the NextPtr field is set in the new Placement Record and before the Hash Table bucket head has been updated. If the arriving packet is for the new connection, the artifact of the race is that the RXP will not find the newly created Placement Record and place the data locally. Since this is the intended behavior for a new Placement Record, this race is benign. If the arriving packet is for another connection, the RXP will find the Placement Record for that connection because the Hash Table head has not yet been updated and the list following the new Placement Record is intact. This race is also benign.
The removal of a placement record 704 should be initiated after the connection has been completely shut down. This is done by locating the previous Placement Record or Hash Table bucket and setting it to point to the Placement Record NextPtr field.
The Placement Record should not be reused or modified until at least one additional frame has arrived at the interface to ensure that the Placement Record is not currently being used by the RXP.
The Marker PDU Architecture (MPA) provides a mechanism to place message oriented upper layer protocol (ULP) PDU on top of TCP.
MPA 1106 enables the reliable location of record boundaries in a TCP stream if markers, the CRC, or both are present. If neither the CRC nor markers are present, MPA is ineffective at recovering lost record boundaries resulting from dropped or out of order data. For this reason, the variant 1108 with neither CRC nor markers isn't considered a practical configuration.
For receive, the RXP 512 supports only the second variant 1110, i.e. CRC without markers. When sending the MPA Start Key, the RXP will specify M:0 and CRC:1 which will force the sender to honor this variant.
The RXP 512 will recognize complete MPA PDU, and is able to resynchronize lost record boundaries in the presence of dropped and out of order arrival of data. The RXP does not support IP fragments. If the FRAG bit is set in the IP header 1112, the RXP will deliver the data locally.
The algorithm supported by the RXP for recognizing a complete MPA PDU is to first assume that the packet is a complete MPA PDU. If this is the case, then do the following:
Under preferred embodiments, if either of these assertions is false, the packet is placed locally.
As depicted in
It should be noted, in this case, that placing the third segment out of order is of questionable value because it will be retransmitted by the remote peer and directly placed a second time. In order to take advantage of the receipt and placement of the third segment, we will need to support selective acknowledgement.
The Queue Number, Message Number, and Message Offset are used to determine whether the data is placed locally or directly into host memory.
If the Queue Number in the DDP header is 1 or 2, the packet is placed locally. These queue numbers are used to send RDMA Read Requests and Terminate Messages respectively. Since these messages are processed by the RDMAP protocol in firmware, they are placed in local memory.
If the Queue Number in the DDP header is 0, the packet is a RDMA Send, RDMA Send and Invalidate, RDMA Send with Solicited Event, or RDMA Send and Invalidate with Solicited Event. In all of these cases, the payload portion of these messages is placed directly into host memory.
A single UTRXD is used to place the payload for a single Untagged DDP message. A single Untagged DDP message may span many network packets. The first packet in the message contains a Message Offset of zero. The last packet in the message has the Last Bit set to ‘1’. All frames that comprise the message are placed using a single UTRXD. The payload is placed in the SGL without gaps.
The hardware uses the Message Number in the DDP header to select which of the UTRXD in the UTRXDQ is used for this message. The Message Offset in conjunction with the SGL in the selected UTRXD is used to place the data in host memory. The Message Number MODULO the UTRXDQ Depth is the index in the UTRXDQ for the UTRXD. The SGL consists of an array of SGE. An SGE in turn contains an STag, Target Offset (TO), and Length.
The protocol headers in each of the packets that comprise the message are placed in local RNIC memory. Each packet consumes an RXD from the RXDQ. The NetPPC 508 will therefore “see” every packet of an Untagged DDP message.
The RXP 512 updates the RXD 902 as follows:
The UTRXD 708 is used for data placement as follows:
The Message Offset is used to locate the SGE
The contents of the UTRXD 708 are updated as follows:
To complete processing, the RXP 512 sets the RXD_DONE bit and resets the RXD_DONE bit in the RXD 902.
If the SGL in the UTRXD is exhausted before all data in the DDP message is placed, an error descriptor (ERD) is posted to the RXDQ 628 to indicate this error.
An STag is a 32-bit value that consists of a 24-bit STag Index 710 and an 8-bit STag Key. The STag Index is specified by the adapter and logically points to an STag Record. The STag Key is specified by the host and is ignored by the hardware.
Logically, an STag is a network-wide memory pointer. STags are used in two ways: by remote peers in a Tagged DDP message to write data to a particular memory location in the local host, and by the host to identify a virtually contiguous region of memory into which Untagged DDP data may be placed. STags are provided to the adapter in a scatter gather list (SGL).
In order to conserve memory in the adapter, an STag Index is not used directly to point to an STag Record. An Stag Index is “twizzled” as follows to arrive at an STag Record Pointer as follows:
STag Record Ptr=(STag Index>>3)|0xE0000000;
The Physical Buffer List 1504 defines the set of pages that are mapped to the virtually contiguous host memory region. These pages may not themselves be either contiguous or even in address order.
A PBL 1504 can be quite large for large virtual mappings. The PBL that represents a 16 MB memory region, for example, would contain 4096 8-byte PCI addresses. The PBL would require 12+8*4096=32,780 bytes of memory.
An STag logically identifies a virtually contiguous region of memory in the host. The mapping between the STag and a PCI address is implemented with the Physical Buffer List 1504 pointed to by the PBL pointer 1506 in the STag Record 1502.
The mapping of an STag and target offset (TO) to a PCI address is accomplished as follows:
Note that after determining the PCI address, the data transfer must be broken up into separate transfers for each page in the PBL. Larger transfers will consist of partial page transfers for the first and last pages and full page size transfers for intermediate pages.
Tagged mode placement is used for RDMA Read Response and RDMA Write messages. In this case, the protocol header identifies the local adapter memory into which the payload should be placed.
The RXP 512 validates the STag 1502 as follows:
The RXP 512 places the payload into the memory 1602 described by the PBL 1504 associated with the STag 1502. The payload is placed by converting the TO 1604 (Target Offset) specified in the DDP protocol header to an offset into the PBL as described above and then copying the payload into the appropriate pages 1602.
The RXP 512 places the protocol header for the Tagged DDP message in an RXD 902 as follows:
To complete processing, the RXP 512 sets the RXD_DONE bit and resets the RXD_DONE bit in the RXD 902.
Persons skilled in the art may appreciate that several public domain TCP/IP stack implementations (e.g., BSD 4.4) provided operating system networking software that utilized a hashing algorithm to locate protocol state information given a source IP address, destination IP address, source port, destination port and protocol identifier. Those approaches however were not used locate information identifying where to place network payload (directly or indirectly), and were operating system based code.
The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of the equivalency of the claims are therefore intended to be embraced therein.
This application claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 60/559557, filed on Apr. 5, 2004, entitled SYSTEM AND METHOD FOR REMOTE DIRECT MEMORY ACCESS, which is expressly incorporated herein by reference in its entirety. This application is related to U.S. patent application Ser. Nos. <to be determined>, filed on even date herewith, entitled SYSTEM AND METHOD FOR WORK REQUEST QUEUING FOR INTELLIGENT ADAPTER and SYSTEM AND METHOD FOR PLACEMENT OF RDMA PAYLOAD INTO APPLICATION MEMORY OF A PROCESSOR SYSTEM, which are incorporated herein by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| 60559557 | Apr 2004 | US |
