This disclosure relates to displaying content on a display.
Displaying visual content such as text, graphics, images, and video to a user includes various phases, including a rendering phase. The rendering phase draws content to be displayed onto a display device, for example, a display panel. The rendering phase may be computationally taxing, especially for high-resolution and complex content. For example, a command mode display panel may incorporate an internal frame buffer memory configured to store data for a single high-resolution frame. Furthermore, the command mode display panel may support display scaling. This allows the display panel to up-scale a low-resolution frame into a high resolution for display. Lower resolution mode reduces rendering, composition, and bandwidth resource demands, thereby reducing power consumption.
In one example embodiment, a method of displaying content is discussed. The method includes rendering a set of frames at a first resolution by a host processor. The method includes transmitting the set of frames at the first resolution to a panel memory, wherein each frame at the first resolution is associated with a memory offset indicative of where the frame at the first resolution is stored in the panel memory. The method includes triggering a low-power mode of the host processor. The method includes upscaling the set frames at the first resolution to a set of full-resolution frames by a display processor, wherein the first resolution is lower than a full-resolution. The method includes displaying the set of full-resolution frames. The method includes transmitting a draw command from the host processor to the display processor, triggering a display of a subsequent frame in the set of full-resolution frames. The method includes transmitting a refresh period from the host processor to the display processor, wherein the display processor triggers a display of a subsequent frame in the set of full-resolution frames once the refresh period has elapsed. Each frame at the first resolution may be associated with a refresh period time offset. The method includes waking the host processor from the low-power mode. The method includes rendering a set of subsequent frames at the first resolution by the host processor. The method includes transmitting the set of subsequent frames to the panel memory, wherein each subsequent frame is associated with a memory offset indicative of where the subsequent frame is stored in the panel memory. The method includes computing a quantity of frames at the first resolution that can be stored in the panel memory, wherein the set of frames at the first resolution consists of the quantity of frames at the first resolution. The method includes, responsive to user input, waking the host processor from the low-power mode. The full-resolution frames may be displayed in sequence as a video playback suitable for batch rendering without user interaction.
In another example embodiment, an apparatus for displaying content is discussed. The apparatus includes a panel memory. The apparatus includes a host processor. The host processor may be configured to render a set of frames at a first resolution. The host processor may be configured to transmit the set of frames at the first resolution to the panel memory, wherein each frame at the first resolution is associated with a memory offset indicative of where the frame at the first resolution is stored in the panel memory. The host processor may be configured to trigger a low-power mode of the host processor. The apparatus includes a display processor. The display processor may be configured to upscale the set frames at the first resolution to a set of full-resolution frames, wherein the first resolution is lower than a full-resolution. The display processor may be configured to display the set of full-resolution frames. The host processor may be configured to transmit a draw command to the display processor, triggering a display of a subsequent frame in the set of full-resolution frames. The host processor may be configured to transmit a refresh period to the display processor, wherein the display processor triggers a display of a subsequent frame in the set of full-resolution frames once the refresh period has elapsed. Each frame at the first resolution may be associated with a refresh period time offset. The host processor may be configured to wake from the low-power mode. The host processor may be configured to render a set of subsequent frames at the first resolution. The host processor may be configured to transmit the set of subsequent frames to the panel memory, wherein each subsequent frame is associated with a memory offset indicative of where the subsequent frame is stored in the panel memory. The host processor may be configured to compute a quantity of frames at the first resolution that can be stored in the panel memory, wherein the set of frames at the first resolution consists of the quantity of frames at the first resolution. The host processor may be configured to, responsive to user input, waking from the low-power mode. The full-resolution frames may be displayed in sequence as a video playback suitable for batch rendering without user interaction.
In another example embodiment, an apparatus for displaying content may be discussed. The apparatus includes a panel memory means. The apparatus includes a host processor means. The host processor means may be configured to render a set of frames at a first resolution. The host processor means may be configured to transmit the set of frames at the first resolution to the panel memory, wherein each frame at the first resolution is associated with a memory offset indicative of where the frame at the first resolution is stored in the panel memory. The host processor means may be configured to trigger a low-power mode of the host processor. The apparatus includes a display processor means. The display processor means may be configured to upscale the set frames at the first resolution to a set of full-resolution frames, wherein the first resolution is lower than a full-resolution. The display processor means may be configured to display the set of full-resolution frames. The host processor means may be configured to transmit a draw command to the display processor means, triggering a display of a subsequent frame in the set of full-resolution frames. The host processor means may be configured to transmit a refresh period to the display processor means, wherein the display processor means triggers a display of a subsequent frame in the set of full-resolution frames once the refresh period has elapsed. Each frame at the first resolution may be associated with a refresh period time offset. The host processor means may be configured to wake from the low-power mode. The host processor means may be configured to render a set of subsequent frames at the first resolution. The host processor may be configured to transmit the set of subsequent frames to the panel memory, wherein each subsequent frame is associated with a memory offset indicative of where the subsequent frame is stored in the panel memory means. The host processor means may be configured to compute a quantity of frames at the first resolution that can be stored in the panel memory means, wherein the set of frames at the first resolution consists of the quantity of frames at the first resolution. The host processor means may be configured to, responsive to user input, waking from the low-power mode. The full-resolution frames may be displayed in sequence as a video playback suitable for batch rendering without user interaction.
In another example embodiment, a non-transitory computer-readable storage medium is discussed. The computer-readable storage medium, having stored thereon instructions that, when executed, cause a host processor to render a set of frames at a first resolution, transmit the set of frames at the first resolution to a panel memory, wherein each frame at the first resolution is associated with a memory offset indicative of where the frame at the first resolution is stored in the panel memory, and trigger a low-power mode of the host processor. The instructions further cause a display processor to upscale the set frames at the first resolution to a set of full-resolution frames, wherein the first resolution is lower than a full-resolution, and display the set of full-resolution frames. The host processor may be further configured to transmit a draw command to the display processor, triggering a display of a subsequent frame in the set of full-resolution frames. The host processor may be further configured to transmit a refresh period to the display processor, wherein the display processor triggers a display of a subsequent frame in the set of full-resolution frames once the refresh period has elapsed, wherein each frame at the first resolution is associated with a refresh period time offset. The host processor may be further configured to wake from the low-power mode, render a set of subsequent frames at the first resolution, and transmit the set of subsequent frames to the panel memory, wherein each subsequent frame is associated with a memory offset indicative of where the subsequent frame is stored in the panel memory. The host processor may be further configured to compute a quantity of frames at the first resolution that can be stored in the panel memory, wherein the set of frames at the first resolution consists of the quantity of frames at the first resolution. The host processor may be further configured to responsive to user input, waking from the low-power mode, wherein the full-resolution frames are displayed in sequence as a video playback suitable for batch rendering without user interaction.
The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description, drawings, and claims.
In many applications, low-resolution frame data can be rendered with fewer resources by a host processor and scaled-up for display with minimal impact on perceived visual image quality. This leaves a large portion of available panel memory unused, as low-resolution frame data requires less memory than full-resolution frame data. An opportunity exists to store future frames in the unused memory. This feature can be exploited by burst mode display processing, where multiple frames are composed and rendered at a first resolution, for example, a lower resolution, and transferred to panel memory in a single cycle. The host processor may enter a power-saving mode and minimize power consumption while the frames are being displayed. The frames are upscaled from the first resolution to a full resolution before display.
In a first approach, a host processor retains enough power and functionality to drive frame switches at the display in a low power mode. In this approach, the host processor continues to send regular draw commands to the display panel, triggering a switch to a next frame for display. In a second approach, a panel controller includes functionality to advance to a next frame after a specified time period, while the host processor remains in a power-saving mode and provides no further instructions.
In the example of
Examples of processor 12, GPU 14, and display processor 18 include, but are not limited to, one or more digital signal processors (DSPs), general purpose microprocessors, application specific integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Processor 12 may be the central processing unit (CPU) of device 10. In some examples, GPU 14 may be specialized hardware that includes integrated and/or discrete logic circuitry that provides GPU 14 with massive parallel processing capabilities suitable for graphics processing. In some instances, GPU 14 may also include general purpose processing capabilities, and may be referred to as a general purpose GPU (“GPGPU”) when implementing general purpose processing tasks (i.e., non-graphics related tasks). Display processor 18 may also be specialized integrated circuit hardware that is designed to retrieve image content from system memory 16, compose the image content into an image frame, and output the image frame to display 19.
Processor 12 may execute various types of applications. Examples of the applications include web browsers, e-mail applications, spreadsheets, video games, or other applications that generate viewable objects for display. System memory 16 may store instructions for execution of the one or more applications. The execution of an application on processor 12 causes processor 12 to produce graphics data for image content that is to be displayed. Processor 12 may transmit graphics data of the image content to GPU 14 for further processing based on and instructions or commands that processor 12 transmits to GPU 14.
Processor 12 may communicate with GPU 14 in accordance with a particular application processing interface (API). Examples of such APIs include the DirectX® API by Microsoft®, the OpenGL® or OpenGL ES® by the Khronos group, and the OpenCL™; however, aspects of this disclosure are not limited to the DirectX, the OpenGL, or the OpenCL APIs, and may be extended to other types of APIs. Moreover, the techniques described in this disclosure are not required to function in accordance with an API, and processor 12 and GPU 14 may utilize any technique for communication or transmission.
System memory 16 may be the memory for device 10. System memory 16 may comprise one or more computer-readable storage media. Examples of system memory 16 include, but are not limited to, a random access memory (RAM), an electrically erasable programmable read-only memory (EEPROM), flash memory, or other medium that can be used to carry or store desired program code in the form of instructions and/or data structures and that can be accessed by a computer or a processor.
In some aspects, system memory 16 may include instructions that cause processor 12, GPU 14, and/or display processor 18 to perform the functions ascribed in this disclosure to processor 12, GPU 14, and/or display processor 18. Accordingly, system memory 16 may be a computer-readable storage medium having instructions stored thereon that, when executed, cause one or more processors (e.g., processor 12, GPU 14, and/or display processor 18) to perform various functions.
System memory 16 is a non-transitory storage medium. The term “non-transitory” indicates that the storage medium is not embodied in a carrier wave or a propagated signal. However, the term “non-transitory” should not be interpreted to mean that system memory 16 is non-movable or that its contents are static. As one example, system memory 16 may be removed from device 10, and moved to another device. As another example, memory, substantially similar to system memory 16, may be inserted into device 10. In certain examples, a non-transitory storage medium may store data that can, over time, change (e.g., in RAM).
As noted above, display processor 18 may perform composition of layers to form a frame for display by a display unit (e.g., shown in the example of
Each of the different hardware pipelines of the display processor may fetch a single layer from memory and perform various operations, such as rotation, clipping, mirroring, blurring, or other editing operations with respect to the layer. Each of the different hardware pipelines may concurrently fetch a different layer, perform these various editing operations, outputting the processed layers to mixers that mix one or more of the different layers to form a frame.
For example, devices such as mobile devices are performing increasingly more tasks. These include, for example, transmission of frames wirelessly for display via display units not integrated within the mobile device (such as television sets). Thus, devices have begun to provide additional multitasking functionality, for example, by presenting multiple windows alongside one another. These windows may also be accompanied by various alerts, notifications, and other on-screen items.
To accommodate the additional layers that result from the increased number of layers, the display processor may offer more hardware pipelines to allow for an increased number of layers to be processed. Adding additional hardware pipelines may however result in increased die area for the SoC, potentially increasing power utilization and adding significant cost.
In the techniques described in this disclosure, a single hardware image fetcher pipeline of hardware image fetcher pipelines 24 (“image fetchers 24”) in display processor 18 may independently process two or more layers. Rather than process a single layer (or multiple dependent layers where any operation performed to one of the multiple dependent layers is also performed with respect to the other dependent layers), the techniques may allow a single one of image fetchers 24 of display processor 18 to individually process one of the multiple independent layers separate from the other ones of the multiple layers. Unlike dependent layers, for independent layers any operation performed to one of the independent layers need not necessarily be performed with respect to the other dependent layers. The example techniques are described with respect to independent layers, but may be applicable to dependent layers as well.
In operation, each individual one of image fetchers 24 of display processor 18 may concurrently (e.g., in parallel or at the same time) retrieve or, in other words, “fetch” two or more layers. Each of image fetchers 24 may next individually process the two or more layers. For example, one of image fetchers 24 may apply a first operation with respect a first one of the layers and apply a second, different operation with respect to the second one of the layers. Example operations include a vertical flip, a horizontal flip, clipping, rotation, etc.
After individually processing the multiple layers, each of the image fetchers 24 may individually output the multiple processed layers to layer mixing units that may mix the multiple processed layers to form a frame. In some examples, a single first processed layer of the multiple layers processed by a first one of image fetchers 24 may be mixed with a single second processed layer of the multiple layers processed by a second one of image fetchers 24 where the remaining layers of the multiple layers processed by the first and second ones of image fetchers 24 may be mixed separate from the single first and second layers. As such, each of the image fetchers 24 has multiple outputs to a crossbar connecting the hardware pipelines to the layer mixing units, as described below in more detail with respect to
In this respect, the techniques may allow each of image fetchers 24 to independently process two or more layers, thereby increasing the number of layers display processor 18 is able to concurrently retrieve, and potentially without increasing the number of image fetchers 24. As such, the techniques may improve layer throughput without, in some examples, adding additional image fetchers to image fetchers 24, which may avoid an increase in boardspace, or chip area (which may also be referred to as “chip die area”) for a system on a chip design, cost, etc.
As further shown in the example of
Each of image fetchers 24 may execute according to a clock cycle to fetch a pixel from each of the two or more of layers 27. In this respect, the discussion of fetching layers 27 should be understood to refer to fetching of a pixel from each of layers 27. Each of image fetchers 24 may therefore fetch two or more of layers 27 by fetching a pixel from each of the two or more layers 27. Image fetchers 24 may be configured to perform a direct memory access (DMA), which refers to a process whereby images fetchers 24 may directly access system memory 16 independently from processor 12, or in other words, without requesting that processor 12 manage the memory access.
As shown in the example of
Image fetchers 24 may fetch two or more individual, distinct (or, in other words, independent) ones of layers 27 rather than fetch a single individual, distinct layer or a layer having two or more dependent sub-layers (as in the case of video data in which a luminance sub-layer and a chrominance sub-layer are dependent in that any operation performed with respect to one of the sub-layers is also performed with respect to the other sub-layer). Image fetchers 24 may each be configured to perform a different operation with respect to each of the two or more fetched ones of layers 27. The various operations are described in more detail with respect to
In this sense, each of image fetchers 24 may support multi-layer (or, for rectangular images, multi-rectangle) fetching when configured in DMA mode. Each of the fetched layers 27 may have a different color or tile format (given that each layer is independent and not dependent from one another), and a different horizontal/vertical flip setting (again, because each of the two of more fetched ones of layer 27 is independent form one another). Each of image fetchers 24 may also support, as described in more detail below, overlapping of the two or more fetched ones of layers 27, as well as, support source splitting.
Crossbar 28 may represent a hardware unit configured to route or otherwise switch anyone of processed layers 29 to any one of mixers 30. Crossbar 28 may include a number of stages, each stage having nodes equal to half of a number of inputs to crossbar 28. For example, assuming crossbar 28 includes 16 inputs, each stage of crossbar 28 may include eight nodes. The eight nodes of each stage may be interconnected to eight nodes of a successive stage in various combinations. One example combination may resemble what is referred to as a “non-blocking switch network” or “non-blocking network switch.” Crossbar 28 may operate with respect to the clock cycle, transitioning processed layers from each stage to each successive stage per clock cycle, outputting processed layers 29 to one of mixers 30. Crossbar 28 is described in more detail below with respect to the example of
Mixers 30 each represent a hardware unit configured to perform layer mixing to obtain composite layers 31A-31N (“composite layers 31”). Composite layers 31 may each include the two or more independent processed layers 29 combined in various ways as described in more detail below with respect to the examples of
DSPs 32 may represent a hardware unit configured to perform various digital signal processing operations. In some examples, DSPs 32 may represent a dedicated hardware unit that perform the various operations. In these and other examples, DSPs 32 may be configured to execute microcode or instructions that configure DSPs 32 to perform the operations. Example operations for which DSPs 32 may be configured to perform include picture adjustment, inverse gamma correction (IGC) using a lookup table (LUT), gamut mapping, polynomial color correction, panel correction using a LUT, and dithering. DSPs 32 may be configured to perform the operations to generate processed composite layers 33, outputting processed composite layers 33 to DSC 34.
DSC 34 may represent a unit configured to perform display stream compression. Display stream compression may refer to a process whereby processed composite layers 33 and composite layers 31N are losslessly or lossy compressed through application of predictive differential pulse-code modulation (DPCM) and/or color space conversion to the luminance (Y), chrominance green (Cg), and chrominance orange (Co) color space (which may also be referred to as YCgCo color model). DSC 34 may output compressed layers 35A-35N (“compressed layers 35,” which may refer to compressed versions of both processed composite layers 33 and non-processed layers 31) to crossbar 38.
Crossbar 38 may be substantially similar to crossbar 28, routing or otherwise switching compressed layers 35 to various different display interfaces 40. Display interfaces 40 may represent one or more different interfaces by which to display compressed layers 35. DSC 34 may compress each of compressed layers 35 in different ways based on the type of display interface 40 to which compressed layers 35 are each is destined. Examples of different types of display interfaces 40 may include DisplayPort, video graphics array (VGA), digital visual interface (DVI), high definition multimedia interface (HDMI™), and the like. Display interfaces 40 may be configured to output each of the compressed layers 35 to one or more display, such as display 19, by writing the compressed layers 35 to a frame buffer or other memory structure, neither of which are shown for ease of illustration purposes.
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Display processor 18 may, in the example of
Burst buffer 72 of address generator 70 may support horizontal flip burst alignment on both P0 and P1 plane (which refers to the streams, or planes, of pixels from each of the two different ones of independent layers 27). Formatter 74 may support include separate P0 and P1 interface to the de-tile buffer. De-tile buffer 76 may support burst level horizontal flip operations, while unpacker 76 may handle horizontal flip operators within each access unit (which may refer to 16-bytes of pixel data). The video pipeline for image fetchers 24, while not explicitly shown in
The internal architecture of crossbar 28 shown in the example of
Crossbar 28, as shown in
It will be appreciated that command mode display panels may refresh the panel independent of a host processor by using internal framebuffer memory. In some embodiments, the host processor transfers framebuffer data to a panel's internal memory for each frame and update. The panel's internal memory may be single buffered and capable of storing one frame data.
Some command mode panels support scaling on the panel-side. In such examples, the host processor can compose and transfer data in a lower resolution which is scaled to panel size when displaying. Lower resolution frames reduce rendering, composition, and data transfer costs thereby reducing power consumption.
It will be appreciated that many applications exhibit comparable image quality when rendered and composed at lower resolution and scaled up before displaying. Lower resolution frames may be appropriate for non-complex texture graphics content, low-resolution video playback, etc., where the upscaling of a low-resolution frame has limited impact on user perceived visual quality. In some examples, video playback content without user interactions may be particularly suitable for such batch processing.
Furthermore, when a lower resolution framebuffer data is transferred to panel's memory, a large portion of panel memory may remain unused. For example, 5/9th of a panel memory is unused when a 720p composed framebuffer is stored and upscaled for display on a 1080p panel. The unused memory can be used to store future frame data and optimize waking of the host processor by composing and transferring multiple frames in a single cycle. Reducing wakeups will help host processor remain in a low-power mode or a power-collapsed state for longer duration and reduce overall power consumption.
A burst mode display processing mode is proposed where multiple frames are composed by a host processor and transferred to a panel memory in a single cycle. The display processor is either instructed to switch to subsequent frames by explicit host processor commands or, the display processor is configured to switch to subsequent frames autonomously.
A display resolution or display mode of a display such as a digital television, computer monitor or other display device is the number of distinct pixels in each dimension that can be displayed. For example, the resolution may be recited as width×height, with the units in pixels: for example, “1024×768” means the width is 1024 pixels and the height is 768 pixels. For example, a display or display panel may be configured to display a frame at a specified full resolution intended for output. As used herein, the term “low-resolution” or “lower-resolution” refers to a spatial display resolution that is less than a full resolution. Common display resolutions in use today for output include DVD at 720×480 (NTSC) or 720×576 (PAL), 720p (HDTV) at 1280×72 or 1366×768 (FWXGA), 1080i, 1080p (HDTV, Blu-ray) at 1440×1080 or 1920×1080, 4K (UHDTV) at 3840×2160, 8K (UHDTV) at 7680×4320, and 16K (UHDTV) at 15360×8640.
The display processor may further compute and communicate a maximum number of low-resolution frames that can be stored in panel memory. The host processor may compute a subsequent frame memory offset (for example, a memory location address of a prior frame added to a frame size) and associate it with a subsequent frame buffer data. The host processor may render and compose subsequent low-resolution frames above the maximum number of frames that can be stored in panel memory, but such frames may be transmitted to panel memory at a later time, after prior frames have been displayed and consumed.
A video subsystem 800 may decode a set of low-resolution frames (Frame 1802A, Frame 2802B, Frame 3802C, etc.) for display to a user on a display panel. As discussed above, the frames may be rendered and composed in low-resolution to save system resources. In one example, the set of frames may be a portion of a video stream for playback to a user. Each frame is associated with timestamps and sent to a media server 804. The media server 804 may ensure the frames are synchronized with an associated audio content. A compositor 806 may compute draw commands draw 1808A, draw 2808B, and draw 3808C. The frames then proceed to the Display Subsystem 810, which composes the received data into frame 1812A, frame 2812B, and frame 3812C.
Each frame is associated with a memory offset, which indicates a memory location in the panel memory where the frame will be stored. The memory offsets are communicated via the Set Memory Offset command discussed above, resulting in commands SetOffset (frame 1) 814A, SetOffset (frame 2) 814B, and SetOffset (frame 3) 814C.
The frame data may be transmitted via a frame data transfer 816. Once the frame data is transmitted, the host processor, perhaps including one or more of the video subsystem 800, media server 804, compositor 806, and display subsystem 810 may enter a low-power mode. In this low-power mode, the host processor may retain functionality to transmit draw commands to a display controller or display processor 818. In this example, commands Draw 1808A, Draw 2808B, and Draw 3808C will be sent to the display processor 818 at the appropriate time to trigger a subsequent frame for display.
The display processor 818 may include a panel RAM or panel memory 820. The panel memory 820 may be partitioned into portions, each portion storing a low-resolution frame received from the host processor. As illustrated, Frame 1 may be stored at memory location 822A, Frame 2, may be stored at memory location 822B, and Frame 3 may be stored at 822C. Responsive to draw commands from the host processor, the display processor 818 may retrieve each frame in sequence, upscale the frame, and display the frame on the panel. A subsequent set of low-resolution frames may be received from the display processor to continue a video playback.
In one example, the panel processor may automatically switch to displaying a subsequent frame after a specified number of VSync units have elapsed. As discussed, this occurs while the host processor remains in a power saving mode and not sending further instructions. In addition to the DSI DCS command “Set Memory Offset” discussed above, another new DSI DCS command Periodicity is defined and added. Periodicity may be a quantity of VSync units to elapse before the display controller will fetch and display a subsequent frame.
A video subsystem 900 may decode a set of low-resolution frames (Frame 1910A, Frame 2910B, Frame 3910C, etc.) for display to a user on a display panel. As discussed above, the frames may be rendered and composed in low-resolution to save system resources. For example, the set of frames may, in total, make up a video stream for playback. Each frame may be associated with timestamps 902 and sent to a media server 904. The media server 904 may ensure the frames are synchronized with an audio content. A compositor 906 may compute draw commands.
Similar to above, each frame is associated with a memory offset, which indicates a memory location in the panel memory where the frame will be stored. Furthermore, each frame is associated with a periodicity or VSync quantity to elapse before triggering display of a subsequent frame. The Display Subsystem 916, may compose the received data into frame 1918A including its memory offset and VSync count 920A. Similarly, frame 2918B and its memory offset and VSync count 920B and frame 3918C including its memory offset and VSync count 920C are computed.
In this example, the frame data may be pushed through channel in data path 908 directly to the compositor 906. Furthermore, the compositor 906 and the host processor may skip computing and transmitting draw commands in loop 912, as the display controller or display processor 924 will handle triggering and displaying a subsequent frame.
The frame data may be transmitted via a frame data transfer. Once the frame data is transmitted, the host processor including the video subsystem 900, media server 804, compositor 906, and display subsystem 916 may enter a low-power mode. In this low-power mode, the host processor may not retain functionality to transmit draw commands to a display controller or display processor 818, thus allowing the host processor to further conserve system resources.
The display processor 924 may include a panel RAM or panel memory 926. The panel memory 926 may be partitioned into portions, each portion storing a low-resolution frame received from the host processor. As illustrated, Frame 1 may be stored at memory location 928A, Frame 2 may be stored at memory location 928B, and Frame 3 may be stored at 928C. Responsive to the correct number of VSync's that have elapsed, the display processor 924 may retrieve each frame in sequence, upscale the frame, and display the frame on the panel. A subsequent set of low-resolution frames may be received from the display processor to continue a video playback.
If the burst mode display render mode must be terminated (for example, synchronization is lost or user input renders previously rendered and composed frames obsolete), a cancel command 914 may be transmitted from the compositor 906 to display subsystem 916, further transferred to display processor 924 as command 922. When this occurs, the panel memory 926 is flushed and correctly rendered frames will be received as part of ordinary frame data transfer.
In one embodiment, the display processor 924 may be further configured to provide burst mode decoding. For example, burst mode decoding may allow the display processor 924 to rapidly decode low-resolution frames for display, and allow the display processor 924 to enter a low-power mode while the frames are sequentially displayed.
In 1002, the host processor may transmit the set of low-resolution frames to a display memory. In addition, the host processor may compute and transmit a memory offset and a timing offset for each frame. For example, as discussed, a memory offset may indicate where in a panel memory to store the low-resolution frame. For example, as discussed, a timing offset may be a period of time or a quantity of VSync's to elapse before displaying the associated or subsequent frame.
In 1004, the host processor may enter or remain in a low-power mode. In one example, the low-power mode allows the host processor to continue sending draw commands, as illustrated in
In 1006, the host processor may optionally send a draw call command to the display processor. This occurs in an approach discussed above, with the benefit of simplifying the display processor and display panel. However, the host processor will need to retain enough functionality to send the draw command, perhaps reducing the potential power savings.
In 1008, the host processor may determine whether the previously transmitted low-resolution frames have been displayed, consumed, or exhausted. If not, the host processor may remain in low power mode in 1004. If yes, the host processor may wake in 1010, and return to 1000 to render and compose a subsequent set of low-resolution frames.
In one or more examples, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over, as one or more instructions or code, a computer-readable medium and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media, which corresponds to a tangible medium such as data storage media. In this manner, computer-readable media generally may correspond to tangible computer-readable storage media which is non-transitory. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code and/or data structures for implementation of the techniques described in this disclosure. A computer program product may include a computer-readable medium.
By way of example, and not limitation, such computer-readable storage media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. It should be understood that computer-readable storage media and data storage media do not include carrier waves, signals, or other transient media, but are instead directed to non-transient, tangible storage media. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
Instructions may be executed by one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, application specific integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Accordingly, the term “processor,” as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. In addition, in some aspects, the functionality described herein may be provided within dedicated hardware and/or software modules configured for encoding and decoding, or incorporated in a combined codec. Also, the techniques could be fully implemented in one or more circuits or logic elements.
The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs (e.g., a chip set). Various components, modules, or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily require realization by different hardware units. Rather, as described above, various units may be combined in a codec hardware unit or provided by a collection of interoperative hardware units, including one or more processors as described above, in conjunction with suitable software and/or firmware.
Various examples have been described. These and other examples are within the scope of the following claims.