System and method for producing a semiconductor circuit arrangement

Abstract

Method and systems for producing a semiconductor circuit arrangement are disclosed. In one implementation, after a formation of a first electrically conductive layer at the surface of a semiconductor substrate for the purpose of realizing a base connection layer and a first split gate layer, an implantation mask is formed for the purpose of carrying out a first collector implantation for the purpose of forming a collector connection zone. After the formation of a hard mask layer and a first etching mask, the hard mask layer is patterned and an emitter window is uncovered using the patterned hard mask layer. Using the patterned hard mask layer a second collector implantation is effected for the purpose of forming a collector zone, a base layer being formed in the region of the emitter window. Afterward, using a second etching mask, a field effect transistor region is uncovered and the patterned hard mask layer is removed in this region in order finally to form a second electrically conductive layer over the whole area for the purpose of realizing an emitter layer and a second split gate layer. Both the bipolar transistor and the field effect transistor are subsequently completed in a customary manner, in particular a source/drain implantation being used simultaneously for the doping of the emitter layer. Since the gate is deposited in two layers, the first layer simultaneously serving as base connection layer and the second layer simultaneously serving as emitter layer, up to two lithography planes can be obviated and costs can thereby be saved.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The systems and methods are described in more detail below on the basis of exemplary embodiments with reference to the drawing.

FIGS. 1A to 1O show simplified sectional views for illustrating one embodiment of a method for producing a BiCMOS circuit arrangement;

FIG. 2 shows a partially enlarged sectional view of FIG. 1G; and

FIG. 3 shows a partially enlarged sectional view of FIG. 1H.

Claims

1. A method for producing a semiconductor circuit arrangement, the method comprising the steps of: a) preparing a semiconductor substrate with a bipolar transistor region and a field effect transistor region;b) forming a first electrically conductive layer at a surface of the semiconductor substrate for the purpose of realizing a base connection layer in the bipolar transistor region and a first split gate layer in the field effect transistor region;c) forming an implantation mask at a surface of the first electrically conductive layer;d) carrying out a first collector implantation for the purpose of forming a collector connection zone in the bipolar transistor region of the semiconductor substrate;e) forming a hard mask layer at a surface of the first electrically conductive layer;f) forming a first etching mask at a surface of the hard mask layer for the purpose of patterning the hard mask layer and for the purpose of uncovering at least one emitter window in the bipolar transistor region;g) patterning a base connection layer using the patterned hard mask layer;h) carrying out a second collector implantation using the patterned hard mask layer and the base connection layer for the purpose of forming a collector zone in the surface of the semiconductor substrate;i) forming a base layer in the region of the emitter window at the surface of the collector zone and at the sidewalls of the base connection layer;j) forming a second etching mask at a surface of the patterned hard mask layer for the purpose of uncovering a field effect transistor region;k) patterning the patterned hard mask layer anew using a second etching mask for the purpose of uncovering a first electrically conductive layer in the field effect transistor region;l) forming a second electrically conductive layer at a surface of the uncovered first electrically conductive layer, the patterned hard mask and the base layer;m) forming a third etching mask at a surface of the second electrically conductive layer;n) patterning a second electrically conductive layer using a third etching mask for the purpose of realizing an emitter layer in the region of the emitter window and a second split gate layer in the field effect transistor region; ando) completing a bipolar transistor in the bipolar transistor region and a field effect transistor in the field effect transistor region.

2. The method of claim 1, wherein the first and second electrically conductive layers have a polycrystalline semiconductor layer,

3. The method of claim 2, wherein the polycrystalline semiconductor layer is a poly-Si layer.

4. The method of claim 1, wherein step d) comprises: carrying out a base connection implantation for the purpose of doping the base connection layer using the implantation mask.

5. The method of claim 4, wherein the collector implantation is a high-energy implantation and the base connection implantation is a low-energy implantation.

6. The method of claim 1, wherein step e) comprises: forming, as hard mask layer, a double layer comprising an etching layer and an emitter/base connection insulation layer.

7. The method of claim 6, wherein the etching layer comprises Si3N4 layer and the emitter/base connection insulation layer comprises SiO2.

8. The method of claim 1, wherein step f) comprises: uncovering a collector connection window in the bipolar transistor region.

9. The method of claim 1, wherein steps f) and g) comprise: using a dry etching method for patterning the hard mask layer and the base connection layer.

10. The method of claim 1, wherein step i) comprises: carrying out a selective epitaxy method for laterally growing a side base layer and for horizontally growing a bottom base layer.

11. The method of claim 1, wherein step i) comprises: forming a compound SiGe semiconductor as the base layer.

12. The method of claim 1, wherein step i) comprises: forming an inner spacer at least at the sidewalls of the patterned hard mask in the region of the emitter window.

13. The method of claim 12, wherein step j) further comprises: uncovering a region of the collector connection window.

14. The method of claim 1, wherein a photoresist mask is used as implantation mask and as first, second and third etching masks.

15. The method of claim 1, wherein during a doping of the source/drain regions of the field effect transistor, the emitter layer (14A) of the bipolar transistor is doped concurrently.

16. The method of claim 1, wherein the gate of the field effect transistor comprises first and second split gate layers, the first split gate layer being formed concurrently with the base connection layer and the second split gate layer being formed concurrently with the emitter layer for the bipolar transistor.

17. A system for producing a semiconductor circuit arrangement, the system comprising: means for preparing a semiconductor substrate with a bipolar transistor region and a field effect transistor region;means for forming a first electrically conductive layer at a surface of the semiconductor substrate for the purpose of realizing a base connection layer in the bipolar transistor region and a first split gate layer in the field effect transistor region;means for forming an implantation mask at a surface of the first electrically conductive layer;means for carrying out a first collector implantation for the purpose of forming a collector connection zone in the bipolar transistor region of the semiconductor substrate;means for forming a hard mask layer at a surface of the first electrically conductive layer;means for forming a first etching mask at a surface of the hard mask layer for the purpose of patterning the hard mask layer and for the purpose of uncovering at least one emitter window in the bipolar transistor region;means for patterning a base connection layer using the patterned hard mask layer;means for carrying out a second collector implantation using the patterned hard mask layer and the base connection layer for the purpose of forming a collector zone in the surface of the semiconductor substrate;means for forming a base layer in the region of the emitter window at the surface of the collector zone and at the sidewalls of the base connection layer;means for forming a second etching mask at a surface of the patterned hard mask layer for the purpose of uncovering a field effect transistor region;means for patterning the patterned hard mask layer anew using a second etching mask for the purpose of uncovering a first electrically conductive layer in the field effect transistor region;means for forming a second electrically conductive layer at a surface of the uncovered first electrically conductive layer, the patterned hard mask and the base layer;means for forming a third etching mask at a surface of the second electrically conductive layer;means for patterning a second electrically conductive layer using a third etching mask for the purpose of realizing an emitter layer in the region of the emitter window and a second split gate layer in the field effect transistor region; andmeans for completing a bipolar transistor in the bipolar transistor region and a field effect transistor in the field effect transistor region.

18. A computer-readable storage medium comprising a set of instructions for directing a system to produce a semiconductor arrangement, the set of instructions to direct the system to perform acts of: a) preparing a semiconductor substrate with a bipolar transistor region and a field effect transistor region;b) forming a first electrically conductive layer at a surface of the semiconductor substrate for the purpose of realizing a base connection layer in the bipolar transistor region and a first split gate layer in the field effect transistor region;c) forming an implantation mask at a surface of the first electrically conductive layer;d) carrying out a first collector implantation for the purpose of forming a collector connection zone in the bipolar transistor region of the semiconductor substrate;e) forming a hard mask layer at a surface of the first electrically conductive layer;f) forming a first etching mask at a surface of the hard mask layer for the purpose of patterning the hard mask layer and for the purpose of uncovering at least one emitter window in the bipolar transistor region;g) patterning a base connection layer using the patterned hard mask layer;h) carrying out a second collector implantation using the patterned hard mask layer and the base connection layer for the purpose of forming a collector zone in the surface of the semiconductor substrate;i) forming a base layer in the region of the emitter window at the surface of the collector zone and at the sidewalls of the base connection layer;j) forming a second etching mask at a surface of the patterned hard mask layer for the purpose of uncovering a field effect transistor region;k) patterning the patterned hard mask layer anew using a second etching mask for the purpose of uncovering a first electrically conductive layer in the field effect transistor region;l) forming a second electrically conductive layer at a surface of the uncovered first electrically conductive layer, the patterned hard mask and the base layer;m) forming a third etching mask at a surface of the second electrically conductive layer;n) patterning a second electrically conductive layer using a third etching mask for the purpose of realizing an emitter layer in the region of the emitter window and a second split gate layer in the field effect transistor region; and o) completing a bipolar transistor in the bipolar transistor region and a field effect transistor in the field effect transistor region.