Claims
- 1-20. (Cancelled)
- 21. A system that provides error checking and correction for data saved in storage media, comprising
a storage medium that is utilized to store data and at least one associated data code; and an interface component that reads the data and the at least one associated data code from the storage medium, compares the at least one associated data code with at least one calculated data code in order to detect data errors, and facilitates correcting associated data errors.
- 22. The system of claim 1, the interface component further generates at least one data code for data to be written to the storage medium and writes the data and the at least one data code to the storage medium.
- 23. The systemi of claim 1, the interface component further monitors and controls a devices access to the storage medium.
- 24. The system of claim 1, the interface component provides at least one error notification upon detecting a data error.
- 25. The system of claim 24, the at least one error notification indicates that a data error is one of a single bit error, a plurality of single bit errors, and a multi-bit error.
- 26. The system of claim 24, the at least one error notification is utilized in a statistical analysis to generate information that is employed to troubleshoot the system.
- 27. The system of claim 1, data errors are corrected as background operations.
- 28. The system of claim 1, the interface component further latches an address to error data in order to point to the most recent fault storage location in the storage medium.
- 29. The system of claim 1, the interface component includes at least a storage medium controller, a bus interface, and error checking and correction logic.
- 30. The system of claim 29, the storage medium controller includes Read-Modify-Write (RMW) logic.
- 31. The system of claim 1, the storage medium is at least one of an array of memory locations and a plurality of memory devices.
- 32. The system of claim 1, the data code is a 7-bit Hamming code.
- 33. The system of claim 1 is employed in an industrial controller.
- 34. A method that corrects data errors in memory devices utilized in an industrial enviromment, comprising
retrieving requested data and at least one associated code from a memory; comparing the at least one retrieved code with at least one calculated code to detect data errors, and correcting the data errors prior to providing the requested data to a requester.
- 35. The method of claim 34, further comprising generating at least one data code for data that is to be written to the memory, and writing the data and the at least one generated data code to the memory.
- 36. The method of claim 34, further comprising setting at least one error flag when a data error is detected.
- 37. The method of claim 34, further comprising latching a memory address corresponding to data with errors to provide the most recent fault location.
- 38. The method of claim 34, further comprising monitoring and controlling a devices access to the memory.
- 39. The system of claim 34, the data and codes are retrieved and compared when at least one of the following occurs: a request to retrieve data is received, a predetermined interval lapses and an interrupt is received.
- 40. A system that corrects stored data errors, comprising
means for associating stored data with data codes, and means for detecting data errors via the data codes; means for indicating at least one data error is detected; and means for correcting the data error.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. patent application Ser. No. 09/520,780, filed on Mar. 8, 2000 and entitled SYSTEM AND METHOD FOR PROVIDING ERROR CHECK AND CORRECTION IN MEMORY SYSTEMS, the entirety of which is incorporated herein by reference.
Continuations (1)
|
Number |
Date |
Country |
Parent |
09520780 |
Mar 2000 |
US |
Child |
10768513 |
Jan 2004 |
US |