1. Technical Field
The present invention relates generally to communication protocols between a host computer and an input/output (I/O) adapter. More specifically, the present invention provides an implementation for supporting differentiated quality of service levels on a physical I/O adapter that supports I/O virtualization. In particular, the present invention provides a mechanism by which a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, can associate one or more virtual I/O adapters or virtual resources to a quality of service level.
2. Description of Related Art
Virtualization is the creation of substitutes for real resources. The substitutes have the same functions and external interfaces as their real counterparts, but differ in attributes such as size, performance, and cost. These substitutes are virtual resources and their users are usually unaware of the substitute's existence. Servers have used two basic approaches to virtualize system resources: partitioning and logical partitioning (LPAR) managers. Partitioning creates virtual servers as fractions of a physical server's resources, typically in coarse (e.g. physical) allocation units (e.g. a whole processor, along with its associated memory and I/O adapters). LPAR managers are software or firmware components that can virtualize all server resources with fine granularity (e.g. in small fractions that of a single physical resource).
In conventional systems, servers that support virtualization have two general options for handling I/O. The first option was to not allow a single physical I/O adapter to be shared between virtual servers. The second option was to add functionality into the LPAR manager, or another suitable intermediary, that provides the isolation necessary to permit multiple operating systems to share a single physical adapter.
The first option has several problems. One significant problem is that expensive adapters cannot be shared between virtual servers. If a virtual server only needs to use a fraction of an expensive adapter, an entire adapter would be dedicated to the server. As the number of virtual servers on the physical server increases, this leads to underutilization of the adapters and more importantly a more expensive solution, because each virtual server needs a physical adapter dedicated to it. For physical servers that support many virtual servers, another significant problem with this approach is that it requires many adapter slots, and the accompanying hardware (e.g., chips, connectors, cables, and the like) required to attach those adapters to the physical server.
Though the second option provides a mechanism for sharing adapters between virtual servers, that mechanism must be invoked and executed on every I/O transaction. The invocation and execution of the sharing mechanism by the LPAR manager or other intermediary on every I/O transaction degrades performance. It also leads to a more expensive solution, because the customer must purchase more hardware, either to make up for the cycles used to perform the sharing mechanism or, if the sharing mechanism is offloaded to an intermediary, for the intermediary hardware.
It would be advantageous to have an improved method, apparatus, and computer instructions for associating a quality of service level to one or more virtual I/O adapters or virtual resources that reside within a physical adapter, such as a PCI, PCI-X, or PCI-E adapter, and are associated with a virtual host. It would also be advantageous to have the mechanism apply for adapters that support memory mapped I/O interfaces, such as Ethernet NICs (Network Interface Controllers), FC (Fibre Channel) HBAs (Host Bus Adapters), pSCSI (parallel SCSI) HBAs, InfiniBand, TCP/IP Offload Engines, RDMA (Remote Direct Memory Access) enabled NICs (Network Interface Controllers), iSCSI adapters, iSER (iSCSI Extensions for RDMA) adapters, and the like.
The present invention provides a method, computer program product, and distributed data processing system for associating a quality of service level to one or more virtual I/O adapters or virtual resources that reside within a physical adapter, such as a PCI, PCI-X, or PCI-E adapter, and are associated with a virtual host. Specifically, the present invention is directed to a mechanism by which a single physical I/O Adapter, such as a PCI, PCI-X, or PCI-E adapter, can associate one or more virtual I/O adapters or virtual resources to a quality of service level. Quality of service differentiation is provided to system images by associating quality of service level weights to system images allocated in a logically partitioned data processing system. Trusted software, such as a hypervisor, assigns quality of service level weights to sets of processing queues that are allocated to a system image. Thus, quality of service differentiation is provided on a per-system image basis by providing processing precedence to system images with higher quality of service level weights relative to other system images with lower quality of service level weights. Additionally, each system image assigns quality of service level weights to the processing queues that have been assigned to that system image. Thereby, quality of service differentiation is provided on a per-processing queue basis by providing processing precedence to processing queues with higher quality of service level weights relative to processing queues with lower quality of service level weights.
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
The present invention applies to any general or special purpose host that uses a PCI family I/O adapter to directly attach a storage device or to attach to a network, where the network consists of endnodes, switches, routers and the links interconnecting these components. The network links can be, for example, Fibre Channel, Ethernet, InfiniBand, Advanced Switching Interconnect, or a proprietary link that uses proprietary or standard protocols. While embodiments of the present invention are shown and described as employing a peripheral component interconnect (PCI) family adapter, implementations of the invention are not limited to such a configuration as will be apparent to those skilled in the art. Teachings of the invention may be implemented on any physical adapter that support a memory mapped input/output (MMIO) interface, such as, but not limited to, HyperTransport, Rapid I/O, proprietary MMIO interfaces, or other adapters having a MMIO interface now know or later developed. Implementations of the present invention utilizing a PCI family adapter are provided for illustrative purposes to facilitate an understanding of the invention.
With reference now to the figures and in particular with reference to
Network 120 can also attach large host node 124 through port 136 which attaches to switch 140. Large host node 124 can also contain a second type of port 128, which connects to a direct attached storage subsystem, such as direct attached storage 132.
Network 120 can also attach a small integrated host node 144 which is connected to network 120 through port 148 which attaches to switch 140. Small integrated host node 144 can also contain a second type of port 152 which connects to a direct attached storage subsystem, such as direct attached storage 156.
Turning next to
In this example, small host node 202 includes two processor I/O hierarchies, such as processor I/O hierarchies 200 and 203, which are interconnected through link 201. In the illustrative example of
With reference now to
In this example, small integrated host node 302 includes two processor I/O hierarchies 300 and 303, which are interconnected through link 301. In the illustrative example, processor I/O hierarchy 300 includes processor chip 304, which is representative of one or more processors and associated caches. Processor chip 304 is connected to memory 312 through link 308. One of the links on the processor chip, such as link 330, connects to a PCI family adapter, such as PCI family adapter 345. Processor chip 304 has one or more PCI family (e.g., PCI, PCI-X, PCI-Express, or any future generation of PCI) links that is used to connect either PCI family I/O bridges or a PCI family I/O adapter, such as PCI family adapter 344 and PCI family adapter 345 through a PCI link, such as links 316, 330, and 324. PCI family adapter 345 can also be used to connect with a network, such as network 364, through link 356 via either a switch or router, such as switch or router 360. PCI family adapter 344 can be used to connect with direct attached storage 352 through link 348.
Turning now to
In this example, large host node 402 includes two processor I/O hierarchies 400 and 403 interconnected through link 401. In the illustrative example of
Turning next to
PCI bus transaction 500 shows three phases: an address phase 508; a data phase 512; and a turnaround cycle 516. Also depicted is the arbitration for next transfer 504, which can occur simultaneously with the address, data, and turnaround cycle phases. For PCI, the address contained in the address phase is used to route a bus transaction from the adapter to the host and from the host to the adapter.
PCI-X transaction 520 shows five phases: an address phase 528; an attribute phase 532; a response phase 560; a data phase 564; and a turnaround cycle 566. Also depicted is the arbitration for next transfer 524 which can occur simultaneously with the address, attribute, response, data, and turnaround cycle phases. Similar to conventional PCI, PCI-X uses the address contained in the address phase to route a bus transaction from the adapter to the host and from the host to the adapter. However, PCI-X adds the attribute phase 532 which contains three fields that define the bus transaction requester, namely: requester bus number 544, requester device number 548, and requester function number 552 (collectively referred to herein as a BDF). The bus transaction also contains a tag 540 that uniquely identifies the specific bus transaction in relation to other bus transactions that are outstanding between the requester and a responder. The byte count 556 contains a count of the number of bytes being sent.
Turning now to
PCI-E bus transaction 600 shows six phases: frame phase 608; sequence number 612; header 664; data phase 668; cyclical redundancy check (CRC) 672; and frame phase 680. PCI-E header 664 contains a set of fields defined in the PCI-Express specification. The requestor identifier (ID) field 628 contains three fields that define the bus transaction requester, namely: requestor bus number 684, requestor device number 688, and requester function number 692. The PCI-E header also contains tag 652, which uniquely identifies the specific bus transaction in relation to other bus transactions that are outstanding between the requestor and a responder. The length field 644 contains a count of the number of bytes being sent.
With reference now to
PCI family adapter 736 contains a set of physical adapter configuration resources 740 and physical adapter memory resources 744. The physical adapter configuration resources 740 and physical adapter memory resources 744 contain information describing the number of virtual adapters that PCI family adapter 736 can support and the physical resources allocated to each virtual adapter. As referred to herein, a virtual adapter is an allocation of a subset of physical adapter resources and virtualized resources such as a subset of physical adapter resources and physical adapter memory, that is associated with a logical partition, such as system image 712 and applications 716 and 720 running on system image 712, as described more fully hereinbelow. LPAR manager 708 is provided a physical configuration resource interface 738, and physical memory configuration interface 742 to read and write into the physical adapter configuration resource and memory spaces during the adapter's initial configuration and reconfiguration. Through the physical configuration resource interface 738 and physical configuration memory interface 742, LPAR manager 708 creates virtual adapters and assigns physical resources to each virtual adapter. LPAR manager 708 may use one of the system images, for example a special software or firmware partition, as a hosting partition that uses physical configuration resource interface 738 and physical configuration memory interface 742 to perform a portion, or even all, of the virtual adapter initial configuration and reconfiguration functions.
After LPAR manager 708 configures the PCI family adapter 736, each system image is allowed to only communicate with the virtual adapters that were associated with that system image by LPAR manager 708. As shown in
With reference now to
If the processor, I/O hub, or I/O bridge 800 uses the same bus number, device number, and function number for all transaction initiators, then when a software component initiates a PCI-X or PCI-E bus transaction, such as host to adapter PCI-X or PCI-E bus transaction 812, the processor, I/O hub, or I/O bridge 800 places the processor, I/O hub, or I/O bridge's bus number in the PCI-X or PCI-E bus transaction's requestor bus number field 820, such as requester bus number 544 field of the PCI-X transaction shown in
If the processor, I/O hub, or I/O bridge 800 uses a different bus number, device number, and function number for each transaction initiator, then the processor, I/O hub, or I/O bridge 800 assigns a bus number, device number, and function number to the transaction initiator. When a software component initiates a PCI-X or PCI-E bus transaction, such as host to adapter PCI-X or PCI-E bus transaction 812, the processor, I/O hub, or I/O bridge 800 places the software component's bus number in the PCI-X or PCI-E bus transaction's requester bus number 820 field, such as requestor bus number 544 field shown in
With reference now to
Turning next to
The functions performed at the super-privileged physical resource allocation level 1000 include but are not limited to: PCI family adapter queries, creation, modification and deletion of virtual adapters, submission and retrieval of work, reset and recovery of the physical adapter, and allocation of physical resources to a virtual adapter instance. The PCI family adapter queries are used to determine, for example, the physical adapter type (e.g. Fibre Channel, Ethernet, iSCSI, parallel SCSI), the functions supported on the physical adapter, and the number of virtual adapters supported by the PCI family adapter. The LPAR manager, such as LPAR manager 708 shown in
The functions performed at the privileged virtual resource allocation level 1008 include, for example, virtual adapter queries, allocation and initialization of virtual adapter resources, reset and recovery of virtual adapter resources, submission and retrieval of work through virtual adapter resources, and, for virtual adapters that support offload services, allocation and assignment of virtual adapter resources to a middleware process or thread instance. The virtual adapter queries are used to determine: the virtual adapter type (e.g. Fibre Channel, Ethernet, iSCSI, parallel SCSI) and the functions supported on the virtual adapter. A system image, such as system image 712 shown in
Finally, the functions performed at the non-privileged level 1016 include, for example, query of virtual adapter resources that have been assigned to software running at the non-privileged level 1016 and submission and retrieval of work through virtual adapter resources that have been assigned to software running at the non-privileged level 1016. An application, such as application 716 shown in
Turning next to
The first exemplary mechanism that LPAR manager 708 can use to associate and make available host memory to a system image and to one or more virtual adapters is to write into the virtual adapter's resources a system image association list 1122. Virtual adapter resources 1120 contains a list of PCI bus addresses, where each PCI bus address in the list is associated by the platform hardware to the starting address of a system image (SI) page, such as SI 1 page 11128 through SI 1 page N 1136 allocated to system image 1108. Virtual adapter resources 1120 also contains the page size, which is equal for all the pages in the list. At initial configuration, and during reconfigurations, LPAR manager 708 loads system image association list 1122 into virtual adapter resources 1120. The system image association list 1122 defines the set of addresses that virtual adapter 1104 can use in DMA write and read operations. After the system image association list 1122 has been created, virtual adapter 1104 must validate that each DMA write or DMA read requested by system image 1108 is contained within a page in the system image association list 1122. If the DMA write or DMA read requested by system image 1108 is contained within a page in the system image association list 1122, then virtual adapter 1104 may perform the operation. Otherwise virtual adapter 1104 is prohibited from performing the operation. Alternatively, the PCI family adapter 1101 may use a special, LPAR manager-style virtual adapter (rather than virtual adapter 1104) to perform the check that determines if a DMA write or DMA read requested by system image 1108 is contained within a page in the system image association list 1122. In a similar manner, virtual adapter 1112 associated with system image 1116 validates DMA write or read requests submitted by system image 1116. Particularly, virtual adapter 1112 provides validation for DMA read and write requests from system image 1116 by determining whether the DMA write or read request is in a page in system image association list (configured in a manner similarly to system image association list 1122) associated with system image pages of system image 1116.
The second mechanism that LPAR manager 708 can use to associate and make available host memory to a system image and to one or more virtual adapters is to write a starting page address and page size into system image association list 1122 in the virtual adapter's resources. For example, virtual adapter resources 1120 may contain a single PCI bus address that is associated by the platform hardware to the starting address of a system image page, such as SI 1 Page 11128. System image association list 1122 in virtual adapter resources 1120 also contains the size of the page. At initial configuration, and during reconfigurations, LPAR manager 708 loads the page size and starting page address into system image association list 1122 into the virtual adapter resources 1120. The system image association list 1122 defines the set of addresses that virtual adapter 1104 can use in DMA write and read operations. After the system image association list 1122 has been created, virtual adapter 1104 validates whether each DMA write or DMA read requested by system image 1108 is contained within a page in system image association list 1122. If the DMA write or DMA read requested by system image 1108 is contained within a page in the system image association list 1122, then virtual adapter 1104 may perform the operation. Otherwise, virtual adapter 1104 is prohibited from performing the operation. Alternatively, the PCI family adapter 1101 may use a special, LPAR manager-style virtual adapter (rather than virtual adapter 1104) to perform the check that determines if a DMA write or DMA read requested by system image 1108 is contained within a page in the system image association list 1122. In a similar manner, virtual adapter 1112 associated with system image 1116 may validate DMA write or read requests submitted by system image 1116. Particularly, a system image association list similar to system image association list 1122 may be associated with virtual adapter 1112. The system image association list associated with virtual adapter 1112 is loaded with a page size and starting page address of a system image page of system image 1116 associated with virtual adapter 1112. The system image association list associated with virtual adapter 1112 thus provides a mechanism for validation of DMA read and write requests from system image 1116 by determining whether the DMA write or read request is in a page in a system image association list associated with system image pages of system image 1116.
The third mechanism that LPAR manager 708 can use to associate and make available host memory to a system image and to one or more virtual adapters is to write into the virtual adapter's resources a system image buffer association list 1154. In
The fourth mechanism that LPAR manager 708 can use to associate and make available host memory to a system image and to one or more virtual adapters is to write into the virtual adapter's resources a single starting and ending address in system image buffer association list 1154. In this implementation, virtual adapter resources 1150 contains a single pair of PCI bus starting and ending address that is associated by the platform hardware to a pair (starting and ending) of addresses associated with a system image buffer, such as SI 2 Buffer 11166. At initial configuration, and during reconfigurations, LPAR manager 708 loads the starting and ending addresses of SI 2 buffer 11166 into the system image buffer association list 1154 in virtual adapter resources 1150. The system image buffer association list 1154 then defines the set of addresses that virtual adapter 1112 can use in DMA write and read operations. After the system image buffer association list 1154 has been created, virtual adapter 1112 validates whether each DMA write or DMA read requested by system image 1116 is contained within the system image buffer association list 1154. If the DMA write or DMA read requested by system image 1116 is contained within system image buffer association list 1154, then virtual adapter 1112 may perform the operation. Otherwise, virtual adapter 1112 is prohibited from performing the operation. Alternatively, the PCI family adapter 1101 may use a special, LPAR manager-style virtual adapter (rather than virtual adapter 1150) to perform the check that determines if DMA write or DMA read requested by system image 1116 is contained within a page system image buffer association list 1154. In a similar manner, virtual adapter 1104 associated with system image 1108 may validate DMA write or read requests submitted by system image 1108. Particularly, virtual adapter 1104 provides validation for DMA read and write requests from system image 1108 by determining whether the DMA write or read requested by system image 1108 is contained within a buffer in a buffer association list that contains a single PCI bus starting and ending address in association with a system image buffer starting and ending address allocated to system image 1108 in a manner similar to that described above for system image 1116 and virtual adapter 1112.
Turning next to
A notable difference between the system image and virtual adapter configuration shown in
The first and second mechanisms that LPAR manager 708 can use to associate and make available PCI family adapter memory to a system image and to a virtual adapter is to write into the PCI family adapter's physical adapter memory translation table 1290 a page size and the starting address of one (first mechanism) or more (second mechanism) pages. In this case all pages have the same size. For example,
The third and fourth mechanisms that LPAR manager 708 can use to associate and make available PCI family adapter memory to a system image and to a virtual adapter is to write into the PCI family adapter's physical adapter memory translation table 1290 one (third mechanism) or more (fourth mechanism) buffer starting and ending addresses (or starting address and length). In this case, the buffers may have different sizes. For example,
With reference next to
The first mechanism is to compare the memory address of incoming PCI bus transaction 1304 with each row of high address cell 1316 and low address cell 1320 in buffer table 1390. High address cell 1316 and low address cell 1320 respectively define an upper and lower address of a range of addresses associated with a corresponding virtual or physical adapter identified in association cell 1324. If incoming PCI bus transaction 1304 has an address that is lower than the contents of high address cell 1316 and that is higher than the contents of low address cell 1320, then incoming PCI bus transaction 1304 is within the high address and low address cells that are associated with the corresponding virtual adapter identified in association cell 1324. In such a scenario, the incoming PCI bus transaction 1304 is allowed to be performed on the matching virtual adapter. Alternatively, if incoming PCI bus transaction 1304 has an address that is not between the contents of high address cell 1316 and the contents of low address cell 1320, then completion or processing of incoming PCI bus transaction 1304 is prohibited. The second mechanism is to simply allow a single entry in buffer table 1390 per virtual adapter.
The third mechanism is to compare the memory address of incoming PCI bus transaction 1304 with each row of page starting address cell 1322 and with each row of page starting address cell 1322 plus the page size in page table 1392. If incoming PCI bus transaction 1304 has an address that is higher than or equal to the contents of page starting address cell 1322 and lower than page starting address cell 1322 plus the page size, then incoming PCI bus transaction 1304 is within a page that is associated with a virtual adapter. Accordingly, incoming PCI bus transaction 1304 is allowed to be performed on the matching virtual adapter. Alternatively, if incoming PCI bus transaction 1304 has an address that is not within the contents of page starting address cell 1322 and page starting address cell 1322 plus the page size, then completion of incoming PCI bus transaction 1304 is prohibited. The fourth mechanism is to simply allow a single entry in page table 1392 per virtual adapter.
With reference next to
The requestor bus number, such as host bus number 1408, requestor device number, such as host device number 1412, and requester function number, such as host function number 1416, referenced in incoming PCI bus transaction 1404 provides an additional check beyond the memory address mappings that were set up by a host LPAR manager.
Turning next to
Turning next to
Turning next to
In the illustrative example, two SIs 1712 and 1713 are shown as allocated in the logically partitioned data processing system. Each system image maintains a respective QoS table containing QoS settings for processing queues owned by that particular system image. For example, system image 1712 maintains QoS table 1748 containing QoS settings for processing queues owned by system image 1712, and system image 1713 maintains QoS table 1749 containing QoS settings for processing queues owned by system image 1713. System images 1712 and 1713 may also have a backing store, e.g., system image's 1712 backing store 1744 to store processing queue (PQ) context.
The PCI adapter, such as adapter 1720, contains a QoS table segment, such as quality of service (QoS) table segment 1728. The first entry in QoS table segment 1728 contains a pointer to a next QoS table segment, such as QoS table segment 1729 used to maintain additional SI QoS level weights in the event the capacity of QoS table segment 1728 is consumed. Each of the other entries in the QoS table segment 1728 contains QoS settings associated with a particular system image. As referred to herein, a QoS setting for an SI (referred to herein as an SI level weight) is a numerical or other identifier that defines a precedence for processing I/O transactions associated with the SI. For example, a QoS setting for an SI may be implemented as an SI level weight comprising an integer value of a predefined integer set, such as SI level weight value of “1” through “5” with an SI level weight value of “1” defining the highest QoS setting available to be assigned to an SI, and an SI level weight value of “5” defining the lowest QoS setting available to be assigned to an SI. Each QoS setting of an SI maintained in one of QoS table segment entries 1728b-1728n is uniquely associated with a system image and with a PQ table segment assigned to the system image. For illustrative purposes, assume entry 1728b is associated with SI 1712 and contains an SI level weight of “1”. Further assume that entry 1728b is associated with SI 1713 and contains an SI level weight of “2”. Thus, SI 1712 having a quality of service level “1” is provided higher processing precedence than SI 1713 having a quality of service level “2”.
In accordance with a preferred embodiment of the present invention, each system image contains a PQ table segment assigned thereto that defines QoS levels of each processing queue assigned to the system image. In the illustrative example, PQ table segment 1700 is assigned to SI 1712, and PQ table segment 1701 is assigned to SI 1713. Entries in a PQ table segment define (or reference) QoS levels of each PQ allocated to the system image to which the PQ table segment is assigned. Additionally, an entry of a PQ table segment may be used to reference another PQ table segment to facilitate processing of I/O operations according to QoS levels as described more fully below.
In the illustrative example, the first entry in each processing queue table segment contains a pointer to the next processing queue table segment. For example, entry 1700a of PQ table segment 1700 assigned to SI 1712 contains a pointer to PQ table segment 1701 assigned to SI 1713. Each of the other entries in a PQ table segment contains (or alternatively references) PQ context including PQ QoS values. For example, each of entries 1700b-1700o in processing queue table segment 1700 assigned to SI 1712 contains context and a PQ QoS value of a particular processing queue associated with SI 1712 or a reference to such context and PQ QoS data for a processing queue associated with the entry. In the illustrative example, SI 1712 has N processing queues allocated thereto, and each of entries 1700b-1700o contain (or reference) context and a QoS level of one of the PQs. For example, entry 1700o contains a reference to context 1758 associated with processing queue N allocated to SI 1712 and includes a QoS setting (or PQ QoS level weight) of processing queue N. Alternatively, entry 1700o may contain a pointer to the context and QoS setting for PQ N. In the illustrative example, PQ N has a PQ QoS level weight of “5.” In a similar manner, each of PQs 1-3 allocated to SI 1712 have PQ QoS level weights of “1”, “2”, and “1,” respectively. Also, for each PQ, the system image sets the processing queue's QoS level in the adapter's PQ QoS level weights 1766 (that is, the PQ QoS level weights in the PQ table segment allocated to the system image. A system image is restricted from accessing a PQ table segment assigned to other system images such that a given system image can only set PQ QoS level weights to PQs assigned to the particular system image.
Thus, QoS table segment 1728 provides a mechanism for defining QoS level service assignments to system images allocated in a logically partitioned data processing system. The SI level weights maintained by QoS table segment 1728 define QoS settings that specify a processing precedence afforded SIs. Additionally, a PQ table segment respectively assigned to each individual SI defines PQ level weights that establish a processing precedence of PQs allocated to an SI once the SI is selected for processing.
With reference next to
Through either a user management interface or an automated script/workflow, a request to assign QoS levels to a set of system images and their associated virtual adapters (if the PCI adapter uses virtual adapter level resource management) or virtual resources (if the PCI adapter uses virtual resource level management) is invoked (step 1800).
The super-privileged resource directly, or through an intermediary, checks to see if the PCI adapter has sufficient resources to complete the request (step 1804). The super-privileged resource may, for example, be the LPAR manager, such as LPAR manager 708 shown in
Returning again to step 1804, if the super-privileged resource determines the physical adapter has sufficient resources to complete the request, the super-privileged resource then directly, or through an intermediary, assigns QoS levels to a set of SIs by updating, for each SI, the QoS table segments associated with the virtual resources allocated to the particular SI (step 1816). For example, the super-privileged resource may write an SI level weight to entry 1728b of “1” to define the QoS setting assigned to SI 1712, and may write an SI level weight to entry 1728b of “2” to define the QoS setting assigned to SI 1713. Once each SI has an SI level weight written to the QoS table segment, the super-privileged resource directly, or through an intermediary, then returns a successful completion result for the operation according to step 1824.
With reference next to
Through either a user management interface or an automated script/workflow, a request to assign QoS levels to a set of processing queues that have been assigned to a specific system image is invoked (step 1900).
The system image or other privileged resource checks to see if the processing queues actually exist (step 1904). If the resources do not exist, then the system image returns an error result for the operation (step 1924).
Returning again to step 1904, if the privileged resource determines that the resources do exist, the privileged resource then directly, or through an intermediary, assigns QoS levels to the set of processing queues by updating, for each processing queue, the processing queue's QoS settings field (or fields) in the processing queue's context table (step 1916). For example, system image 1712 may update QoS settings for each processing queue allocated to system image 1712 by writing PQ QoS level weights to each entry 1700b-1700o respectively associated with a PQ allocated to SI 1712. The system image then returns a successful completion result for the operation according to step 1916.
With reference next to
The routine is entered when the adapter's outbound transmit queue is empty, the adapter's link layer is ready to accept another transmit request, and the adapter has set a “ready to transmit frame” indicator in the SI QoS level weight table, e.g., QoS table segment 1728 shown in
The adapter reads the next super-privileged QoS table entry to determine which processing queue segment to process next (step 2004). On an initial evaluation, that is on a first evaluation after the QoS table segment has been initialized, the adapter preferably begins by reading QoS table segment 1728 for an entry identifying an SI with the highest SI level weight, e.g., an entry with an SI level weight of “1.” On subsequent evaluations, the adapter performs this function by starting at the last entry that was checked and continuing through the set of entries within the same QoS table segment as the last entry that was checked until it reaches the end of the QoS Table Segment. Once a given QoS table segment is fully traversed, the adapter uses the QoS table segment pointer (first entry in the table) to go on to the next QoS table segment that is at the same SI QoS level. Once all QoS table segments that are at the same QoS level have been traversed, the adapter proceeds to the next QoS table segment pointed to by the first entry in the current QoS table segment and repeats until it reaches a processing queue segment that has an outbound queue ready to transmit.
The adapter then reads the next PQ table segment to determine which processing queue to process next (step 2012). The adapter retrieves the next outbound transmit frame by using the processing queue's work queue element (WQE) header to retrieve the processing queue's WQE and passes the next frame to be transmitted in sequence to the adapter's outbound transmit queue. The adapter then returns to step 2000.
Embodiments of the present invention provide a mechanism by which a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, can associate one or more virtual I/O adapters or virtual resources to a quality of service level. Quality of service differentiation is provided to system images by associating quality of service level weights to system images allocated in a logically partitioned data processing system. A system image assigns quality of service level weights to processing queues allocated to the system image. Thus, quality of service differentiation is provided on a per-system image basis by providing processing precedence to system images with higher quality of service level weights relative to other system images with lower quality of service level weights. Moreover, quality of service differentiation is provided on a per-processing queue basis by providing processing precedence to processing queues with higher quality of service level weights relative to processing queues with lower quality of service level weights.
The description of the present invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention, the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
This application is related to commonly assigned and co-pending U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040178US1) entitled “Method, System and Program Product for Differentiating Between Virtual Hosts on Bus Transactions and Associating Allowable Memory Access for an Input/Output Adapter that Supports Virtualization”; U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040179US1) entitled “Virtualized I/O Adapter for a Multi-Processor Data Processing System”; U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040180US1) entitled “Virtualized Fibre Channel Adapter for a Multi-Processor Data Processing System”; U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040181US1) entitled “Interrupt Mechanism on an IO Adapter That Supports Virtualization”; U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040182US1) entitled “System and Method for Modification of Virtual Adapter Resources in a Logically Partitioned Data Processing System”; U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040183US1) entitled “Method, System, and Computer Program Product for Virtual Adapter Destruction on a Physical Adapter that Supports Virtual Adapters”; U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040184US1) entitled “System and Method of Virtual Resource Modification on a Physical Adapter that Supports Virtual Resources”; U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040185US1) entitled “System and Method for Destroying Virtual Resources in a Logically Partitioned Data Processing System”; U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040186US1) entitled “Association of Memory Access Through Protection Attributes that are Associated to an Access Control Level on a PCI Adapter that Supports Virtualization”; U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040187US1) entitled “Association of Host Translations that are Associated to an Access Control Level on a PCI Bridge that Supports Virtualization”; U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040507US1) entitled “Method, Apparatus, and Computer Program Product for Coordinating Error Reporting and Reset Utilizing an I/O Adapter that Supports Virtualization”; U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040552US1) entitled “Method and System for Fully Trusted Adapter Validation of Addresses Referenced in a Virtual Host Transfer Request”; U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040553US1) entitled “System, Method, and Computer Program Product for a Fully Trusted Adapter Validation of Incoming Memory Mapped I/O Operations on a Physical Adapter that Supports Virtual Adapters or Virtual Resources”; U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040554US1) entitled “System and Method for Host Initialization for an Adapter that Supports Virtualization”; U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040555US1) entitled “Data Processing System, Method, and Computer Program Product for Creation and Initialization of a Virtual Adapter on a Physical Adapter that Supports Virtual Adapter Level Virtualization”; U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040556US1) entitled “System and Method for Virtual Resource Initialization on a Physical Adapter that Supports Virtual Resources”; U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040557US1) entitled “Method and System for Native Virtualization on a Partially Trusted Adapter Using Adapter Bus, Device and Function Number for Identification”; U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040558US1) entitled “Native Virtualization on a Partially Trusted Adapter Using PCI Host Memory Mapped Input/Output Memory Address for Identification”; U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040559US1) entitled “Native Virtualization on a Partially Trusted Adapter Using PCI Host Bus, Device, and Function Number for Identification; U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040560US1) entitled “System and Method for Virtual Adapter Resource Allocation”; and U.S. patent application Ser. No. ______ (Attorney Docket No. AUS920040562US1) entitled “System and Method for Managing Metrics Table per Virtual Port in a Logically Partitioned Data Processing System” all of which are hereby incorporated by reference.