Claims
- 1. A reference generator circuit for a receiver module coupled to a digital communications channel, the reference generator circuit comprising:
a reference voltage generation module to generate an adjustable reference voltage within the receiver module; an error measurement module, coupled to the reference voltage generation module, to determine an error signal value between a measured received signal and a desired signal; and wherein the reference voltage generation module uses the error signal to control the magnitude of the adjustable reference voltage.
- 2. The reference generator circuit according to claim 1, wherein a range of voltage values corresponding to a received symbol are decoded as a particular symbol using a maximum reference voltage and minimum reference voltage; and
the maximum reference voltage and minimum reference voltage are adjusted using error statistics collected within the error measurement module using the incoming data stream.
- 3. The reference generator circuit according to claim 2, wherein adaption of the maximum reference voltage and minimum reference voltage is performed during an initialization process.
- 4. The reference generator circuit according to claim 2, wherein the statistics within the error measurement module are collected using the equation:
- 5. The reference generator circuit according to claim 2, wherein adaption of the maximum reference voltage and minimum reference voltage is performed continuously, periodically, or intermittently.
- 6. The reference generator circuit according to claim 5, wherein the adaption of the maximum reference voltage and minimum reference voltage is selectively enabled or disabled.
- 7. The reference generator circuit according to claim 5, wherein the maximum reference voltage and minimum reference voltage reference magnitude are externally set to a predetermined value.
- 8. A reference generator circuit according to claim 5, where the spacing between reference levels is non-uniform.
- 9. The reference generator circuit according to claim 8, wherein a performance criteria for setting the non-uniformity between the range of voltage values is a measure of a bit-error rate (BER) for the receiver module.
- 10. The reference generator circuit according to claim 1, wherein the spacing between reference levels is non-uniform.
- 11. The reference generator according to claim 10, wherein the nonuniformity is asymmetric.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority to U.S. Provisional Patent Application Serial No. 60/313,455, entitled “Automatic Slicer Level Adaption”, filed Aug. 20, 2001, and U.S. Provisional Application Serial No. 60/313,214, entitled “Transceiver Apparatus and Method”, filed Aug. 17, 2001. The contents of these provisional applications are incorporated, in their entirety, by reference herein.
[0002] This application is related to U.S. Provisional Patent Application Serial No. 60/313,454, entitled “Transceiver System for High Speed Digital Signaling”, filed Aug. 20, 2001 (Docket No. 13764.1-US-P1); U.S. Provisional Patent Application Serial No. 60/313,456, entitled “Variable Rate Sub-Channel Using Block Code RDS”, filed Aug. 20, 2001 (Docket No. 13764.3-US-P1); U.S. Provisional Patent Application Serial No. 60/313,478, entitled “Variable Delay FIR Equalizer for Serial Baseband Communications”, filed Aug. 20, 2001 (Docket No. 13764.4-US-P1); U.S. Provisional Patent Application Serial No. 60/313,477, entitled “Crosstalk Management for High-Speed Signaling Links”, filed Aug. 20, 2001 (Docket No. 13764.5-US-P1); and U.S. Provisional Patent Application Serial No. 60/313,476, entitled “Method and Apparatus for Encoding and Decoding Digital Communications Data”, filed Aug. 20, 2001 (Docket No. 13764.6-US-P1). The aforementioned applications are hereby incorporated by reference herein.
[0003] This application is also related to non-provisional patent applications that claim priority to one or more of the above-referenced provisional patent applications. These non-provisional patent applications are entitled “System and Method for High Speed Digital Signaling”, filed Aug. 16, 2002 (Docket No. 209.001-US); “System and Method for Embedding a Sub-Channel in a Block Coded Data Stream”, filed Aug. 16, 2002 (Docket No. 209.003-US); “System and Method for Providing Variable Delay FIR Equalizer for Serial Baseband Communications”, filed Aug. 16, 2002 (Docket No. 209.004-US); “System and Method for Providing Crosstalk Management for High-Speed Signaling Links”, filed Aug. 16, 2002 (Docket No. 209.005-US); and “Method and Apparatus for Encoding and Decoding Digital Communications Data”, filed Aug. 16, 2002 (Docket No. 209.006US). The aforementioned non-provisional patent applications are hereby incorporated by reference, in their entirety, herein.
Provisional Applications (2)
|
Number |
Date |
Country |
|
60313455 |
Aug 2001 |
US |
|
60313214 |
Aug 2001 |
US |