A memory purge system destructively purges the memory circuits of a memory device. The system includes a power supply for supplying a selectable voltage and current. Switching circuits electrically connect the power supply to the memory circuits of the memory device. A controller selects a voltage and current supplied by the power supply and activates the switching circuit to apply the voltage and current to the memory circuits. The controller determines whether the memory circuits have been destroyed by monitoring current flow into the memory circuits.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram depicting the basic components of a memory device according to one embodiment of the invention.
FIG. 2 is a flowchart depicting a process for a destructive purge of a memory circuit according to one embodiment of the invention.
Claims
1. A memory purge system for purging a flash memory device, the memory purge system comprising:
a switching circuit for electrically connecting a power supply to a memory circuit of the flash memory device; anda controller for selecting a first voltage and current supplied by said power supply and activating said switching circuit to apply the first voltage and current to the memory circuit in response to a condition.
2. The memory purge system according to claim 1, further comprising a current detector for detecting current between said power supply and the memory circuit, wherein, if the detected current drops below a threshold, said controller deactivates said switching circuit to stop the application of the first voltage and current to the memory circuit.
3. The memory purge system according to claim 2, wherein the first voltage and current are applied to the memory circuit for a predetermined period of time.
4. The memory purge system according to claim 3, wherein, if the first current does not drop below the threshold within the predetermined period of time, said controller selects a second voltage, higher than the first voltage, to be supplied by said power supply and activates said switching circuit to apply the selected second voltage and current to the memory circuit for the predetermined period of time.
5. The memory purge system according to claim 1, wherein said switching circuit comprises a transistor.
6. The memory purge system according to claim 1, wherein said switching circuit comprises a field-effect transistor.
7. The memory purge system according to claim 1, wherein said power supply comprises a converter for converting input power into the selected voltage and current.
8. The memory purge system according to claim 7, wherein the first voltage and current are selected based on the power rating of the flash memory device.
9. The memory purge system according to claim 1, wherein the flash memory device includes a plurality of memory circuits, and the memory purge system further comprises a respective plurality of switching circuits.
10. The memory purge system according to claim 9, wherein said controller applies the first voltage and current to each of the plurality of flash memory circuits in time division multiplex fashion.
11. A method for purging a flash memory device, the method comprising the steps of:
selecting a voltage and current supplied by a power supply; andactivating a switching circuit connecting the power supply to a memory circuit of the memory device to apply the selected voltage and current to the memory circuit,wherein the switching circuit is activated in response to a condition.
12. The method according to claim 11, further comprising the step of:
confirming the purge of the flash memory device by attempting to write to the flash memory device.
13. The method according to claim 11, wherein the voltage and current are applied to the memory circuit of the memory device for a predetermined period of time.
14. The method according to claim 13, further comprising the steps of:
detecting current between the power supply and the memory circuit;increasing the supplied voltage if the detected current does not drop below the threshold within the predetermined period of time; andactivating the switching circuit for the predetermined period of time to apply the increased voltage and current to the memory circuit.
15. The method according to claim 14, further comprising the step of repeating said increasing step and said activating step until the current detected in said detecting step drops below the threshold.
16. The method according to claim 11, wherein the step of selecting the voltage and current supplied is based on the power rating of the flash memory device.
17. A system for purging a flash memory device, the system comprising:
a converter configured to supply a first voltage and current;a switching circuit electrically coupled to the converter and the flash memory device, the switching circuit comprising a switch configured to electrically connect the converter to a memory circuit of the flash memory device; anda first controller configured to activate the switch to apply the first voltage and current of the converter to the memory circuit of the flash memory device to damage a transistor in the memory circuit of the flash memory device.
18. The system of claim 17, wherein the transistor comprises a field-effect transistor.
19. The system of claim 17, wherein the switching circuit and the first controller reside on a single controller.
20. The system of claim 17, wherein the first controller is further configured to confirm the purge of the flash memory device by causing a write command to be sent to the flash memory device.
Patent Application
20070165456
