Claims
- 1. A receiver, comprising:a filtering circuit receiving and filtering an electromagnetic signal; an analog to digital converter (ADC) electrically connected to the filtering circuit and outputting a digitized signal representative of the electromagnetic signal; and a digital processor electrically connected to the ADC, the digital processor reconstructing the digitized signal, wherein the processor includes a mixer generating an intermediate frequency (IF) signal based on the digitized signal, and a demodulator decoding useful information from the IF signal.
- 2. The receiver of claim 1, wherein the ADC digitizes the signal prior to any analog demodulation thereof.
- 3. The receiver of claim 1, wherein the filter is controlled and tuned by the processor.
- 4. The receiver of claim 1, further comprising an amplifier connected to the filter, the amplifier being controlled by the processor.
- 5. The receiver of claim 4, wherein the filter is controlled and tuned by the processor.
- 6. The receiver of claim 1, wherein the processor reconstructs the digitized signal such that spurious signal elements and noise are removed therefrom.
- 7. The receiver of claim 1, wherein the processor reconstructs the digitized signal such that a desired signal is enhanced and amplified.
Parent Case Info
This application is a continuation of allowed U.S. patent application Ser. No. 09/178,229, filed Oct. 23, 1998, which in turn is a continuation of U.S. patent application Ser. No. 08/596,551, filed Feb. 5, 1996, now U.S. Pat. No. 5,864,754, both of which are incorporated herein by reference and priority from both of which is hereby claimed.
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Continuations (2)
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Number |
Date |
Country |
Parent |
09/178229 |
Oct 1998 |
US |
Child |
09/771821 |
|
US |
Parent |
08/596551 |
Feb 1996 |
US |
Child |
09/178229 |
|
US |