System and method for reducing phase distortion in a linear transmitter via the introduction of bias currents to a power amplifier

Abstract

The invention decreases phase distortion in a transmitter by balancing C load in the power amplifier input such that a PGA won't have phase distortion.

Description

BACKGROUND

1. Technical Field

This invention relates generally to wireless communication systems, and more particularly, but not exclusively, to a linear in-phase transmitter.

2. Description of the Related Art

Communication systems are known to support wireless and wire lined communications between wireless and/or wire lined communication devices. Such communication systems range from national and/or international cellular telephone systems to the Internet to point-to-point in-home wireless networks. Each type of communication system is constructed, and hence operates, in accordance with one or more communication standards. For instance, wireless communication systems may operate in accordance with one or more standards including, but not limited to, IEEE 802.11, Bluetooth, advanced mobile phone services (AMPS), digital AMPS, global system for mobile communications (GSM), code division multiple access (CDMA), and/or variations thereof.

Depending on the type of wireless communication system, a wireless communication device, such as a cellular telephone, two-way radio, personal digital assistant (PDA), personal computer (PC), laptop computer, home entertainment equipment, et cetera communicates directly or indirectly with other wireless communication devices. For direct communications (also known as point-to-point communications), the participating wireless communication devices tune their receivers and transmitters to the same channel or channel pair (e.g., one of the plurality of radio frequency (RF) carriers of the wireless communication system) and communicate over that channel or channel pair. For indirect wireless communications, each wireless communication device communicates directly with an associated base station (e.g., for cellular services) and/or an associated access point (e.g., for an in-home or in-building wireless network) via an assigned channel. To complete a communication connection between the wireless communication devices, the associated base stations and/or associated access points communicate with each other directly, via a system controller, via the public switch telephone network, via the internet, and/or via some other wide area network.

For each wireless communication device to participate in wireless communications, it includes a built-in radio transceiver (i.e., receiver and transmitter) or is coupled to an associated radio transceiver (e.g., a station for in-home and/or in-building wireless communication networks, RF modem, etc.). As is known, the receiver receives RF signals, removes the RF carrier frequency from the RF signals directly or via one or more intermediate frequency stages, and demodulates the signals in accordance with a particular wireless communication standard to recapture the transmitted data. The transmitter converts data into RF signals by modulating the data to RF carrier in accordance with the particular wireless communication standard and directly or in one or more intermediate frequency stages to produce the RF signals.

The IEE 802.11 g standard uses Orthogonal Frequency Division Multiplexing (OFDM) modulation that has data information in both the amplitude and phase. In order not to degrade the modulation quality, the transmitter may be operated 10 dB lower than the 1 dB compression point of the transmitter. That is, the operating output power backs off by 10 dB of its 1 dB compression point. The design target is to send out 5 dBm output power, which means the transmitter may be linear up to 15 dBm. That is, the transmitter and thus the power amplifier driver (PAD) (the last stage of the transmitter) has to be designed with output 1 dB compression point equal to or more than about 15 dBm. A balun coupled to the PAD combines the differential signal and then sends it to a power amplifier if extra output power is required.

The design of a power amplifier driver (PAD) can be classified as class A, class AB, class B, class C, etc when biased at different current levels. In some designs, a programmable gain amplifier (PGA) is coupled to and drives a PAD. Small and big swings in the PGA output cause PAD to present different capacitive loads to the PGA, which causes PGA phase distortion in the time frame. Since information is carried by both amplitude and phase therefore phase distortion will make the transmitter non-linear.

Accordingly, a system and method are needed in designing the PAD such that it presents a constant capacitive load for its previous stage PGA. The PGA and hence the whole transmitter can then have linear in phase response.

SUMMARY

Embodiments of the invention enable the power amplifier to present a constant capacitive load to PGA in order for PGA to overcome phase distortion, thereby maintaining phase linearity.

In one embodiment of the invention, a power amplifier comprises two sets of differential pairs and a differential inductor. The differential inductor is coupled to each of the differential pairs. Each of the differential pairs receives a bias voltage that in combination balances the Capacitance load (C load), which is the PAD input capacitive load presented to PGA, for its driving stage (PGA in this case). Constant Cload for the PGA will make the PGA have constant phase response for its small/big output amplitude and thus avoid phase distortion. In an embodiment of the invention, the one pair is biased at Class AB and one pair is biased at close to class B. To bias the pairs differently, current is changed independently in one pair via the use of current mirrors.

In one embodiment of the invention, the method comprises using two sets of differential pairs for the power amplifier; and supplying different bias voltages to the differential pairs that in combination present a balanced C load to its driving stage PGA. Bias voltage is varied independently of each other in the pairs via the use of current mirrors.

BRIEF DESCRIPTION OF THE DRAWINGS

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

FIG. 1 is a block diagram illustrating a network system according to an embodiment of the present invention;

FIG. 2A is a block diagram illustrating a section of a transmitter;

FIG. 2B is a block diagram illustrating a programmable gain amplifier (PGA) coupled to a PAD of the transmitter of FIG. 2;

FIG. 3A-F are graphs illustrating PAD input gate capacitance is capacitive load (C load) for PGA and how C load is a function of PAD input DC bias and PGA output (PAD input) amplitude. It also shows how the PGA phase got distorted when seeing different Cload.

FIG. 4 is a diagram illustrating the power amplifier driver (PAD);

FIG. 5 is a diagram illustrating a section of the power amplifier driver;

FIG. 6 is a diagram illustrating another section of the power amplifier driver;

FIG. 7 is a diagram illustrating how the bias voltages for the first and second differential pairs are generated; and

FIG. 8 is a flowchart illustrating a method of biasing a power amplifier driver.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

The following description is provided to enable any person having ordinary skill in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles, features and teachings disclosed herein.

FIG. 1 is a block diagram illustrating a network system 10 according to an embodiment of the present invention. The system 10 includes a plurality of base stations and/or access points 12-16, a plurality of wireless communication devices 18-32 and a network hardware component 34. The wireless communication devices 18-32 may be laptop host computers 18 and 26, personal digital assistant hosts 20 and 30, personal computer hosts 24 and 32 and/or cellular telephone hosts 22 and 28.

The base stations or access points 12 are operably coupled to the network hardware 34 via local area network connections 36, 38 and 40. The network hardware 34, which may be a router, switch, bridge, modem, system controller, etc. provides a wide area network connection 42 for the communication system 10. Each of the base stations or access points 12-16 has an associated antenna or antenna array to communicate with the wireless communication devices in its area. Typically, the wireless communication devices register with a particular base station or access point 12-14 to receive services from the communication system 10. For direct connections (i.e., point-to-point communications), wireless communication devices communicate directly via an allocated channel.

Typically, base stations are used for cellular telephone systems and like-type systems, while access points are used for in-home or in-building wireless networks. Regardless of the particular type of communication system, each wireless communication device includes a built-in radio and/or is coupled to a radio. The radio includes a transmitter capable of adjusting power amplifier output power.

FIG. 2A is a block diagram illustrating a section of a transmitter 200. The transmitter 200 includes digital to analog processing circuitry (not shown), communicatively coupled to I and Q branches. The I and Q branches each include a filter 210a and 210b respectively, a Gm stage 220a and 220b respectively and a mixer 230a and 230b respectively. The mixers 230a and 230b are communicatively coupled to a programmable gain amplifier (PGA) 240, which is communicatively coupled to a power amplifier driver (PAD) 250, which is communicatively coupled to a balun 260, which is communicatively coupled to a power amplifier 270, which is communicatively coupled to an antenna 280. The PAD 250 acts as a power amplifier (PA) and is referred to as a PAD to distinguish it from the PA 270.

After digital to analog processing, as is known in the art, the filters 210a and 210b, which may include low pass filters, filter the I and Q currents. The GM stages 220a and 220b then convert the voltage signals into current signals, which are up converted into 2.5 GHz signal via the mixers 230a and 230b in one embodiment. The PGA 240 provides the gain that amplifies the signals, and the PAD 250 then drives the balun 260 that combines the differential output signal into single ended signal. The balun 260 presents a load of 50 ohm to each side to the PAD 250. An external power amplifier 270 can be used if more output power (more than 5 dBm) is required.

FIG. 2B is a block diagram illustrating the PGA 240 coupled to the PAD 250. Output from inductors 285 of the PGA 240 is fed into differential pairs 290 of the PAD 250. PAD input gate capacitance (C load) will be shown to be a function of the PAD operating point and the PGA output (PAD input) amplitude. As will be discussed in further detail below, the variation of C load as a function of the amplitude will cause the PGA to show different phase delay over different amplitudes, i.e., phase distortion. In order to reduce phase distortion, the PAD 250 is biased such that the C load presented to PGA is constant regardless of output from the inductors 285.

FIG. 3A-F are graphs illustrating operation of the PAD 250. FIG. 3A shows bias current at the differential pair 290 versus operating bias voltage. Operating point A,B and C specified. Operating point A is such that the PAD is a class AB design and B is such that the PAD is a close to class B design. FIG. 3B shows C load (MOS gate capacitance of the PAD differential pair) versus operating bias voltage. Operating point A,B and C are specified. FIG. 3E shows the C load is a function of the amplitude at operating point A. FIG. 3F shows the C load is a function of the amplitude at operating point B. At operating point A, the C load decreases as PGA 240 output signal amplitude (PAD input signal amplitude) increases and is not linear over the amplitude range. At operating point B (bias current is close to 0), the C load decreases as PGA 240 output signal amplitude (PAD input signal amplitude) increases and is not linear over the amplitude range. As can be seen, depending on how the PAD is biased, C load is a different function of the PAD input bias voltage and PGA output amplitude. These different C loads effect the magnitude gain as shown in FIG. 3C and to a greater extent, phase gain, as shown in FIG. 3D.

FIG. 4 is a diagram illustrating the power amplifier driver 250. The PAD 250 comprises two differential pairs (having two branches each, one positive, one negative) coupled to a differential inductor 400. At about 2.5 GHz (the operating frequency, the transmitter band is around 2.5 GHz), the imaginary part of the impedance is 0 and the real part of the impedance is about 200. With the inductor 400 tunes out whatever capacitive load at 2.5 GHz, the equivalent load seen by the PAD is an impedance of 200+j*0. That is the PAD output sees a load impedance with real part=200 and imaginary part=0. Bias transistors in the differential pairs 290 supply bias voltage to the power amplifier driver 250. Specifically, the design biases transistors in one pair (290A) at operating point A while biasing transistors in the other pair (290B) at operating point B. Accordingly, the pairs generate C load that balance each other out as is shown and therefore prevents phase distortion for its driving stage PGA.

FIG. 5 is a diagram illustrating a section 500 of the power amplifier driver 250. Bias is supplied from current source 510, which passes through a diode connected MOS 515 to a resistor 520 coupled to a differential pair 290A of the PAD 250. The resistor 520 passes a DC bias Vgs. For the second differential pair, the bias must be less than Vgs, as will be discussed further below.

FIG. 6 is a diagram illustrating another section 600 of the power amplifier driver 250. The section 600 shows the biasing of the second differential pair 290B at a bias less than the bias of the differential pair 290A. Specifically, the differential pair 290B is biased at Vgs2 while the differential pair 290A is biased at Vgs1. Vgs2 is equal to Vgs1 minus an IR drop from the IR drop 610. The IR drop 610 will be discussed in further detail in conjunction with FIG. 7 below.

Bias from the current source 510 is supplied to the differential paid 290B via an IR drop 610, which is coupled to a resistor 620. The IR drop 610 reduces the bias supplied from the current source 510 to a bias less than the bias supplied to the differential pair 290A. The bias supplied to the differential pair 290A can be Class AB while the bias supplied to the differential pair 290B can be close to Class B.

FIG. 7 is a diagram illustrating the IR drop 610 of the power amplifier driver 250. The IR drop 610 comprises a plurality of current mirrors 710, 720, 730, 740, 760, 770 and 780 that mirror current. The mirrors enable supplying bias to the first differential pair 290A that is greater than the second differential pair 290B without affecting the bias at the first differential pair 290A when changing current to the second differential pair 290B. Current from the current source 510 passes through the current mirrors and the bias is reduced when passing through a resistor 750. Specifically, bias current passes through the mirror 710, which is coupled to the mirror 720. The mirror 720 is coupled to the mirror 730 and the mirror 770, which is coupled to the mirror 780, which is coupled to the resistor 750 and to output of V2 to the second differential pair. The mirror 730 is coupled to the mirror 740 and the mirror 760 as well as to output of V1 to the first differential pair 290A and to the resistor 750.

Bias current in the mirror 710=Ibias. Bias current in the mirror 720=Bias current in the mirror 770=Bias current in the mirror 780=Ibias*(W/L)1I/(W/L)0=I. (W is the MOS transistor width and L is the MOS transistor length). The second differential pair 290B bias voltage=V2=V1−I*R. Bias at the first differential pair 290A using V1 will make the first differential pair 290A bias current equal to bias current in the mirror 760=bias current in the mirror 730+bias current in the mirror 740−bias current in the mirror 780. The bias current in the mirror 730=Ibias*(W/L)1/(W/L)0=I. Bias current in the mirror 740=Ibias* (W/L)2/(W/L)0. The bias current in mirror 780=Ibias*(W/L)2/(W/L)0=I. The first differential pair 290A bias current=Bias current in the mirror 760=Bias current in the mirror 740=Ibias*(W/L)2/(W/L)0 and will not be effected by the choice of I. Otherwise every time the IR drop is changed by changing I, the bias current in the first differential pair 290A will be changed.

FIG. 8 is a flowchart illustrating a method 800 of biasing a power amplifier driver such that it improves the constant of PAD input differential pair gate capacitance and reduces phase distortion in the PGA 240. First, a simple PAD design (just like the differential pair like 290A) is done (810) with a bias voltage (V1) for its differential pair. Its C load curve is then a function of the PGA output amplitude. Second, another differential pair (290B) is designed (820) with a different bias voltage (V2=I*R)(by changing I value) for its differential pair. Its C load curve is then a function of the PGA output amplitude. The I value is changed using the IR drop 610 discussed above. Therefore, by changing the I value the bias voltage V1 for the first differential pair will not be effected. Third, add (830) the above two C load curves and see if they are constant (840) for the PGA output amplitude of interest. Finally, if they are not constant (840) then the designing (810 and/or 820) and adding (830) are repeated until the criteria are met.

The foregoing description of the illustrated embodiments of the present invention is by way of example only, and other variations and modifications of the above-described embodiments and methods are possible in light of the foregoing teaching. Components of this invention may be implemented using a programmed general purpose digital computer, using application specific integrated circuits, or using a network of interconnected conventional components and circuits. Connections may be wired, wireless, modem, etc. The embodiments described herein are not intended to be exhaustive or limiting. The present invention is limited only by the following claims.

Claims

1. A power amplifier, comprising: two sets of differential pairs; a differential inductor coupled to each of the differential pairs; wherein each of the differential pairs includes a bias transistor supplying a bias voltage to the amplifier that in combination balance the C load; and wherein a change in current in a bias transistor of one of the differential pairs is independent of current in the other bias transistor.

2. The amplifier of claim 1, wherein output of the pairs are combined.

3. The amplifier of claim 1, wherein the amplifier tunes out parasitic capacitance.

4. The amplifier of claim 1, wherein each pair includes a positive and a negative branch.

5. The amplifier of claim 1, wherein one pair has a bias voltage in Class AB operation while the other pair has a bias voltage close to Class B operation.

6. The amplifier of claim 1, wherein the amplifier includes a plurality current mirrors the enable the independent change of current in a bias transistor.

7. A transmitter having an amplifier according to claim 1.

8. A method, comprising: presenting a load by two sets of differential pairs of a power amplifier, wherein the pairs are coupled to a differential inductor; supplying bias voltages to the differential pairs that in combination balance the C load; and wherein a change in current in a bias transistor of one of the differential pairs is independent of current in the other bias transistor.

9. The method of claim 8, further comprising combining the output of the pairs.

10. The method of claim 8, wherein the amplifier tunes out parasitic capacitance.

11. The method of claim 8, wherein each pair includes a positive and a negative branch.

12. The method of claim 8, wherein one pair has a bias in Class AB operation while the other pair has a bias voltage close to Class B operation.

13. The method of claim 8, wherein the amplifier includes a plurality current mirrors the enable the independent change of current in a bias transistor.