Patent Application
20250124856
The present disclosure relates to a display and more specifically to circuitry and techniques used to reduce a current consumed while addressing the rows and columns of the display.
A memory-in-pixel (MIP) display can include a static random access memory (SRAM) cell for each pixel. A binary value can be written to the SRAM cell so that after writing, the SRAM cell is in one of two possible binary states. Each pixel of the display may emit light based on the binary state (i.e., state) of the SRAM cell. Power may be consumed to write to the SRAM cell (i.e., change states), but after writing, the state of the SRAM cell may be maintained with very little power consumption.
For a display with a million or more pixels, the power consumed by the write operations of the SRAM cells may be significant. A display is disclosed that can reduce the current consumed by a pixel while writing to the SRAM cell of the pixel.
In some aspects, the techniques described herein relate to a pixel for a display, the pixel including: a latch circuit powered by an upper rail voltage and a lower rail voltage; a first bit line coupled to a first output of the latch circuit by a first transistor, the first transistor controlled in a ON condition during a write operation by word line voltage on a word line and a LOW bit line voltage on the first bit line; a second bit line coupled to a second output of the latch circuit by a second transistor, the second transistor controlled in an OFF condition during the write operation by the word line voltage and a HIGH bit line voltage on the second bit line; and a word line regulator configured to control the word line voltage on the word line to float above the HIGH bit line voltage on the second bit line by a threshold voltage to limit a current conducted by the second transistor in the OFF condition during the write operation.
In some aspects, the techniques described herein relate to a method for writing to a memory cell of a pixel array, the method including: driving a first bit line to a lower rail voltage of the memory cell, the first bit line coupled to a first output of a latch circuit via a first transistor, the first transistor coupled at a first gate terminal to a word line; driving a second bit line to a HIGH bit line voltage, the second bit line coupled to a second output of the latch circuit via a second transistor, the second transistor coupled at a second gate terminal to the word line; driving the word line to a word line voltage so that the first transistor is biased in an ON condition to couple the lower rail voltage to the first output of the latch circuit; configuring the latch circuit to output an upper rail voltage of the memory cell to the second output based on the first output being coupled to the lower rail voltage; and controlling the word line voltage to float above the HIGH bit line voltage by a threshold voltage to limit a current through the second transistor while writing to the memory cell of the pixel array.
In some aspects, the techniques described herein relate to a pixel for a display including: a word line; a first bit line driven at a HIGH bit line voltage or a lower rail voltage; a second bit line driven at the lower rail voltage when the first bit line is driven at the HIGH bit line voltage and driven at the HIGH bit line voltage when the first bit line is driven at the lower rail voltage; a latch circuit configured to output an upper rail voltage or the lower rail voltage; a first transistor connected at a first drain terminal to the latch circuit, connected at a first source terminal to the first bit line, and connected at a first gate terminal to the word line; a second transistor connected at a second drain terminal to the latch circuit, connected at a second source terminal to the second bit line, and connected at a second gate terminal to the word line; and a word line regulator configured to generate a word line voltage on the word line that floats above the HIGH bit line voltage by a reference voltage, the HIGH bit line voltage being less than the upper rail voltage.
The foregoing illustrative summary, as well as other exemplary objectives and/or advantages of the disclosure, and the manner in which the same are accomplished, are further explained within the following detailed description and its accompanying drawings.
The components in the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding parts throughout the several views.
A display may include millions of pixels, each having a memory cell (i.e., SRAM cell) that controls a micron-sized light emitting diode (micro-LED) based on its stored binary value (i.e., its state). A write operation may change the state of the memory cell so that the pixels may be switched ON/OFF. The micro-LED display may require millions of write operations per second to render an image. At least one technical problem facing the micro-LED display is reducing the current drawn for each write operation to lower the overall power consumed by the micro-LED display. Reducing the overall power consumed by the micro-LED display can enable the display to be used in mobile applications, such as augmented/virtual reality glasses/goggles, smart watches, smart glasses, and the like.
A pixel array in these displays may function as an SRAM memory that includes a plurality of SRAM cells that can be addressed by row using word lines and by column using bit lines. Addressing the SRAM cells may include coupling the SRAM cells of a row to respective bit lines. The coupling may be initiated by transmitting a word line signal to a word line for the row. After coupling, bit line signals can be transmitted on respective bit lines to program (i.e. write to) the SRAM cells of the row.
Each bit line may have a parasitic capacitance (i.e., capacitance) due to the length and proximity of the conductors in the display. The bit line capacitance is charged while the SRAM cell is programmed (i.e., written). Charging the bit line capacitance (C) takes energy. The energy (E) is quadratically related to the bit line signal (VBL) transmitted on the bit line (E=½ CVBL2) during a write operation.
Reducing the capacitance can reduce the power consumed by the display. One problem facing reducing power in this way is that the bit line capacitance may not be easily reduced without changing the electrical layout of the display. Instead, the bit line signal (i.e., bit line voltage) applied to the bit line may be reduced so that the energy stored in (i.e., consumed by) the capacitance can be reduced. Reducing this bit line voltage can be problematic, however, because it can create a scenario in which a voltage difference between the word line and the bit line generates a current while the state of the SRAM cell is being changed (i.e., flipped). The present disclosure describes a circuit (i.e., word line regulator) that can control the voltage on the word line to mitigate, or prevent, this current while allowing the bit line voltage to be reduced in order to reduce the power consumed by the bit line capacitance, which provides a technical solution to the technical problem described above.
As shown in
The display 100 further includes a controller 101 configured to control the operation of the word-line driver 112 and the bit-line driver 113 to render an image on the pixel array 120. For example, the controller 101 may transmit a word-line signal (i.e., ROW) to activate a row and then transmit the image data (i.e., DATA(COLUMN)) to the columns of the activated row in parallel.
In a possible implementation, a rendering process includes transmitting a word-line signal to activate a row. After being activated, a bit-line signal for each pixel in the row controls the pixel ON/OFF according to the image data for each pixel in the active row. After the bit-line signals configure (i.e., write to) the pixels of the active row, the row may be deactivated, and another row may be activated until all rows of an image have been activated. The SRAM cells for pixels in deactivated rows can hold the pixels of the deactivated rows ON or OFF while the other rows of the image are activated. After writing an image to the SRAM cells of the pixel array 120, the SRAM cells can hold their values (e.g., 0, 1) until they are changed. As a result, updating the values in an SRAM display may only require a portion of the SRAM cells to change their state (i.e., flip) from image to image. This feature of the display contributes to the low power consumption of the display. A sequence of binary images, in which each pixel is either ON (e.g., SRAM at binary 1) or OFF (e.g., SRAM at binary 0) may be rendered at a high rate to create a grayscale image perceived by an observer.
The disclosed display is well suited for displaying digital images with pixels that are either ON or OFF. The digital image can be a bit plane. A series of bit planes can be displayed in rapid sequence so that a viewer perceives a grayscale image. A color display can render color images based on grayscale images for each color channel.
A bit plane sequence 220 can be generated to have a bit plane for each bit of the binary number. In other words, each pixel in a bit plane can be ON (e.g., 1) or OFF (e.g., 0) according to the bit. As shown, the bit plane sequence 220 includes four bit planes. A first bit plane in the sequence is a binary image that represents the most significant bit (MSB) of each pixel (i.e., the most significant bit plane 221). A second bit plane 222 is less significant than the most significant bit plane 221. A third bit plane 223 is less significant than the second bit plane 222 but is more significant than the least significant bit plane 224, which represents the least significant bit (LSB) of each pixel.
The significance of the bit planes with respect to the gray scale value decreases from the most significant bit plane 221 to the least significant bit plane 224. Accordingly, a first bit plane may be referred to as being below a second bit plane when the first bit plane is of lower significance (in the bit plane sequence 220) than the second bit plane. Likewise, the second bit plane may be referred to as being above the first bit plane when the second bit plane is of higher significance (in the bit plane sequence 220) than the first bit plane.
Rendering the gray scale image may include writing each bit plane to the pixel array (i.e., SRAM) in succession during a rendering period 230. When each bit plane is displayed at the same intensity, each bit plane may be weighted by the duration that it is displayed relative to the other bit planes during the sequence. As shown, the weights (W) of the bit planes may double for each bit plane from the least significant bit plane 224 to the most significant bit plane 221. In other words, the portions of a rendering period may double for each successive bit plane from the least significant bit plane 224 to the most significant bit plane 221 displayed during the rendering period 230.
Rendering a grayscale image using multiple bit planes may require a large number of write operations during the rendering period 230. Rendering one bit plane can include writing to each row in the pixel array. Accordingly, despite a low power consumed to write to a single row, the cumulative power consumed to write to (i.e., address) every row in the bit plane may be larger than desired for some applications (e.g., battery operated applications). Further, the cumulative power consumed to address every row in every be plane of a sequence of bit planes is even larger, especially for high bit depth displays. The disclosed circuits and methods can reduce this overall power consumption by reducing the power required to address pixels during write operations.
As shown in
An advantage of using an SRAM cell 400 to control the drive switch 320 is that while the SRAM cell 400 is in the HIGH-state (i.e., ON-state) or the LOW-state (i.e., OFF-state) it consumes very little current (e.g., approximately zero current) from the power supply. The SRAM cell 400 draws most of its current (e.g., approximately all of its current) as it transitions (i.e., is flipped) between states (i.e., during a write process).
As shown in
The write process to change the state of the SRAM cell 400 may include addressing the SRAM cell 400 using a word line 314 and asserting voltages on the latch circuit 450 using a positive bit line 315 (i.e., first bit line) and negative bit line 316 (i.e., second bit line).
During the write process, the latch circuit 450 is coupled to the positive bit line 315 and negative bit line 316 by switches, which are controlled by a word-line signal (WL) transmitted on the word line 314. For example, a first level (e.g., HIGH) on the word line 314 turns the switches ON to couple the input/output of latch circuit 450 to respective positive/negative lines of the bit line. A second level (e.g., LOW) on the word line 314 turns the switches OFF to decouple the input/output of the latch circuit 450 from the bit-line drivers so that the state is stored.
More specifically, the state of the SRAM cell 400 may be flipped by a positive bit line signal (BL+) transmitted to the latch circuit 450 by the positive bit line 315 and a negative bit line signal (BL−) transmitted to the latch circuit 450 by the negative bit line 316. The applied bit line signals (BL+, BL−) correspond to the desired state of the latch. Once the desired state is set, the output of the latch circuit 450 is stable and the signals (BL+, BL−) may be removed. The state of the SRAM cell 400 appears as a voltage at the output of one of the inverters of the latch circuit 450.
The state of the SRAM may be toggled to form a pulse width modulation signal (i.e., PWM signal 390) that controls the drive switch 320 so that a drive current (ID) is received by the micro-LED 310 during the ON portions of the PWM signal 390. The modulation of the PWM signal 390 may toggle between the upper rail voltage 311 and the lower rail voltage (i.e. ground voltage 312).
The latch circuit 450 is powered by an upper rail voltage 431 and a lower rail voltage 432. As a result, the latch circuit 450, may be configured to output the upper rail voltage (VDD)) while in a first state and output the lower rail voltage (VSS) in a second state. As mentioned previously, the VDD (i.e., HIGH) and VSS (i.e. LOW) output can drive the drive switch 320 in an ON-condition or an OFF-condition respectively. The latch circuit power domain (i.e. VDD−VSS) may match the power domain of the pixel shown in
The first transistor 401 is coupled at a gate terminal (G) to a word line 410, coupled at a source terminal(S) to the first bit line 411, and coupled at a drain terminal (D) to the first output 414 of the latch circuit 450. Accordingly, the ON-condition (i.e., conducting) or OFF-condition (i.e., not conducting) of the first transistor 401 can be controlled by the word line signal (VWL) on the word line 410 and the bit line signal on the first bit line 411.
The bit line signal on the first bit line 411 may be a HIGH bit line voltage 441 (VBL_H) or a LOW bit line voltage 442 (VBL_L). The bit line signal may be generated by a bit line driver 440 operating in a bit line power domain (VBL_H−VBL_L) which is less than the latch circuit power domain (i.e., VDD−VSS). In a possible implementation, the HIGH bit line voltage (VBL_H) of the first bit line 411 is less than the upper rail voltage (i.e., VBL_H<VDD). For example, the HIGH bit line voltage can be 50 percent or less than the upper rail voltage. In a possible implementation, the LOW bit line voltage (VBL_L) of the first bit line 411 is equal to the lower rail voltage (i.e., VBL_L=VSS). For example, the LOW bit line voltage can be ground.
The second transistor 402 is coupled at a gate terminal (G) to the word line 410, coupled at a source terminal(S) to the second bit line 412, and coupled at a drain terminal (D) to the second output 415 of the latch circuit 450. Accordingly, the ON-condition (i.e., conducting) or OFF-condition (i.e., not conducting) of the second transistor 402 can be controlled by the word line signal (VWL) on the word line 410 and the bit line signal on the second bit line 412.
The bit line signal on the second bit line 412 may be a HIGH bit line voltage 441 (VBL_H) or a LOW bit line voltage 442 (VBL_L). The bit line signal may be generated by the bit line driver 440 operating in a bit line power domain (VBL_H−VBL_L) which is less than the latch circuit power domain (i.e., VDD−VSS). In a possible implementation, the HIGH bit line voltage (VBL_H) of the second bit line 412 is less than the upper rail voltage (i.e., VBL_H<VDD). For example, the HIGH bit line voltage can be 50 percent or less than the upper rail voltage. In a possible implementation, the LOW bit line voltage (VBL_L) of the second bit line 412 is equal to the lower rail voltage (i.e., VBL_L=VSS). For example, the LOW bit line voltage can be ground.
The HIGH bit line voltage being less than the upper rail voltage can reduce a power consumed by a bit line capacitance 421 of the first bit line 411 and the second bit line 412. In other words, the HIGH bit line voltage can be reduced (from the upper rail voltage 431) to achieve a power savings. The reduction may be based on a target power savings and the bit line capacitance 421. Reducing the bit line power domain can create problems in controlling the current conducted by the first transistor 401 and the second transistor 402. For example, if the HIGH bit line voltage is made too low compared to the word line voltage (VWL) then the first transistor 401 or the first transistor 401 may be placed in an ON condition when it should be in an OFF condition during a write operation.
During a write operation, one of the bit lines (e.g., the first bit line 411) is driven to the HIGH bit line voltage and the other of the bit line (e.g., the second bit line 412) is driven to the LOW bit line voltage (e.g., the lower rail voltage). The transistor coupled to the LOW bit line voltage is placed in an ON condition which forces this output of the latch circuit 450 circuit to the lower rail voltage (e.g. ground). Feedback in the latch circuit then configures the other output of the latch circuit to the upper rail voltage. To prevent the voltage difference between the upper rail voltage and the (smaller) HIGH bit line voltage from creating a current, the transistor coupled to the HIGH bit line voltage should be in an OFF condition. Controlling this transistor to be OFF may be problematic without some control over the word line voltage (VWL) because of fluctuations in the HIGH bit line voltage levels and variations in the transistors (e.g., due to process, aging, temperature, etc.). Accordingly, the SRAM cell of the pixel includes a word line regulator 500 configured to generate a word line voltage (VWL) based on the HIGH bit line voltage. For example, the word line regulator can control the word line voltage on the word line to float above the HIGH bit line voltage by a threshold voltage (VTH) of the first transistor 401 and the second transistor 402 so that the transistor (i.e., VWL=VBL_H+VTH).
The word line regulator 500 includes a reference voltage source configured to receive the HIGH bit line voltage 441 and to generate a reference voltage at a reference node 515. In a possible implementation, the reference voltage source is a diode connected transistor 510, configured to generate a drain-to-source voltage equal to the threshold voltage (VTH) of the diode connected transistor 510.
The diode connected transistor 510 can be substantially matched (e.g., in dimensions) to the first transistor 401 and the second transistor 402 so the threshold voltage of the diode connected transistor 510 substantially matches the threshold voltages of the first transistor 401 and second transistor 402. In a possible implementation, the threshold voltage (VTH) of the diode connected transistor 510 may be adjusted to have a difference (e.g., guard band) that can accommodate variations in the threshold voltages of the transistors in the pixel array. In a possible implementation, the threshold voltage can be in a range between about 0.2 volts and 0.9 volts (i.e., 0.2≤VTH≤0.9).
The voltage of the reference node 515 can equal the HIGH bit line voltage 441 plus the threshold voltage. In other words, the voltage at the reference node can float above the HIGH bit line voltage 441 by the threshold voltage so that variations in the HIGH bit line voltage 441 also appear at the reference node 515.
The word line regulator 500 further includes a mirror circuit configured to transmit the reference voltage from the reference node 515 to an output node (i.e., output 545). The mirror circuit includes a reference transistor 520 coupled at a first source terminal(S) to the reference node 515 and having a first gate terminal (G) coupled to a first drain terminal (D). The mirror circuit further includes a driver transistor 540. The driver transistor 540 is coupled at a second gate terminal (G) to the first gate terminal of the reference transistor 520. The driver transistor 540 is also coupled at a second source terminal(S) to the output 545. The reference transistor 520 and the driver transistor 540 may be matched so that the gate-to-source voltage of each of the transistors is equal. This voltage may be created by currents generated by a reference current source 530 and a mirror current source 550, which provide equal currents in the legs of the mirror circuit. As a result, then voltage at the output 545 is equal to the threshold voltage above the HIGH bit line voltage.
The word line regulator 500 further includes a coupling transistor 560 configured to couple the output 545 to the word line 410 during the write operation. The coupling transistor may be coupled to a word line controller 565 configured to control the coupling transistor 560 so that the coupling transistor 560 the word line 410 of the SRAM cell 400. The output 545 may be coupled to multiple coupling transistors each coupled to a different word line of the pixel array so that the display may utilize the word line regulator 500 for their respective write operations. The write operation may begin when the word control line controls the coupling transistor in an ON condition.
The disclosed circuit has three different voltage domains. A first voltage domain is the voltage swing of the latch circuit (VDD−VSS), a second voltage domain is the voltage swing of the bit lines (VBL_H−VBL_L), and a third voltage domain is the voltage swing of the word line (VWL−VOFF). In a possible implementation VSS. VBL_L, and VOFF are equal to a ground voltage (i.e., ground). In a possible implementation, VDD>VWL>VBL_H. The word line regulator 500 is configured to adjust the third voltage domain so that it can control the first transistor 401 and the second transistor 402 when they are operated between the first voltage domain and the second voltage domain.
In the specification and/or figures, typical embodiments have been disclosed. The present disclosure is not limited to such exemplary embodiments. The use of the term “and/or” includes any and all combinations of one or more of the associated listed items. The figures are schematic representations and so are not necessarily drawn to scale. Unless otherwise noted, specific terms have been used in a generic and descriptive sense and not for purposes of limitation.
It will be understood that, in the foregoing description, when an element is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element, there are no intervening elements present. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application, if any, may be amended to recite exemplary relationships described in the specification or shown in the figures.
As used in this specification, a singular form may, unless definitely indicating a particular case in terms of the context, include a plural form. Spatially relative terms (e.g., over, above, upper, under, beneath, below, lower, and so forth) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms above and below can, respectively, include vertically above and vertically below. In some implementations, the term adjacent can include laterally adjacent to or horizontally adjacent to.
The application claims the benefit of U.S. Provisional Application No. 63/589,688 filed on Oct. 12, 2023, which is hereby incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63589688 | Oct 2023 | US |
