Patent Application
20060004557
1. Field of the Invention
The present invention relates to a value change file used in the simulation of an integrated circuit design and, in particular, to reducing the size of the value change file by determining a subset of signals that can be used to regenerate a target set of signals.
2. Description of the Related Art
The EDA software design process (step 110) is actually composed of a number of steps 112-130, shown in linear fashion for simplicity. Note that in an actual design process, certain steps (or series of steps) may have to be repeated until any associated tests are passed. Similarly, in any actual design process, these steps may occur in different orders and combinations. This description is therefore provided by way of context and general explanation rather than as a specific, or recommended, design flow for a particular integrated circuit. A brief description of the components steps of the EDA software design process (step 110) will now be provided.
In a system design step 112, the designers describe the functionality that they want to implement and perform what-if planning to refine functionality, check costs, etc. Hardware-software architecture partitioning can occur at this stage. Exemplary EDA software products from Synopsys, Inc. that can be used in step 112 include Model Architect, Saber, System Studio, and DesignWare® tools.
In a logic design and functional verification step 114, the source code (e.g. VHDL or Verilog) for modules of the integrated circuit can be written and the design checked for functional accuracy. Specifically, the design can be checked to ensure that it produces the correct outputs. Exemplary EDA software products from Synopsys, Inc. that can be used in step 114 include VCS, VERA, DesignWare®, Magellan, Formality, ESP and LEDA tools.
In a synthesis and design for test step 116, the source code can be translated to a netlist, which is optimized for a target technology. Additionally, tests to permit checking of the finished chip can be generated and implemented. Exemplary EDA software products from Synopsys, Inc. that can be used in step 116 include Design Compiler®, Physical Compiler, Test Compiler, Power Compiler, FPGA Compiler, Tetramax, and DesignWare® tools.
In a design planning step 118, an overall floorplan for the chip can be constructed and analyzed for timing and top-level routing. Exemplary EDA software products from Synopsys, Inc. that can be used in step 118 include Jupiter and Flooplan Compiler tools.
In a netlist verification step 120, the netlist can be checked for compliance with timing constraints and for correspondence with the source code. Exemplary EDA software tools from Synopsys, Inc. that can be used in step 120 include VCS, VERA, Formality and PrimeTime tools.
In a physical implementation step 122, the placement (i.e. the positioning of circuit elements in the design) and the routing (i.e. the connection of those circuit elements) can be performed. Exemplary EDA software products from Synopsys, Inc. that can be used in step 122 include the Astro tool.
In an analysis and extraction step 124, the integrated circuit function can be verified at a transistor level, which in turn can permit what-if refinement. Exemplary EDA software products from Synopsys, Inc. that can be used in step 124 include the Star RC/XT, Raphael, and Aurora tools.
In a physical verification step 126, various checking functions can be performed to ensure correctness for manufacturing, electrical issues, lithographic issues, and circuitry. Exemplary EDA software products from Synopsys, Inc. that can be used in step 126 include the Hercules tool.
In a resolution enhancement step 128, the layout can be geometrically manipulated to improve the manufacturability of the design. Exemplary EDA software products from Synopsys, Inc. that can be used in step 128 include the iN-Phase, Proteus, and AFGen tools.
In a mask data preparation step 130, the “tape-out” data for producing the masks used to make the integrated circuit can be generated. Exemplary EDA software products from Synopsys, Inc. that can be used in step 130 include the CATS® family of tools.
During logic design and functional verification step 114, a simulator can document signal changes in the design, thereby allowing defects (also called bugs) in the design to be detected. These signal changes can be documented by generating a trace (i.e. a history) of the values held by signals during simulation. In typical embodiments, a user can select the traces to be captured. For example, in one embodiment, the user could select traces for all signals in a design. In another embodiment, the user could select traces for only certain signals in the design. These traces can be captured in a file, called a value change file.
As designs continue to increase in complexity, the corresponding value change files also increase in size. These large value change files can cause capacity problems (i.e. require an undesirably large storage space). Moreover, these large value change files can be very tedious and time-consuming to analyze during run time. To reduce value change file size, certain compression techniques can be used. Unfortunately, even with compression, capacity problems are still occurring with increasing frequency.
Therefore, a need arises for a technique of reducing the size of the value change files.
During simulation of an integrated circuit design, a simulator can generate traces of certain signals, thereby allowing defects in the design to be detected. The traces of these signals, called a target set herein, are typically saved in a value change file. Unfortunately, this value change file can get very large, thereby causing capacity and performance problems.
In accordance with one aspect of the invention, a subset of signals that can regenerate the target set of signals is determined. Notably, only this subset of signals needs to be saved in the value change file, thereby significantly reducing its size. The target set of signals can be computed on demand after reading the value change file.
Determining the subset of signals can include identifying state elements (e.g. flip-flops, latches, or other storage devices) and corresponding signal dependencies of the integrated circuit design. In one embodiment, identifying the state elements can include all state elements of the integrated circuit design. In another embodiment, identifying the state elements can include a set of state elements of the integrated circuit design. Determining the subset of signals can occur during a compile time of the simulation.
Generating the subset of signals can include using the corresponding signal dependencies of the integrated circuit design. In one embodiment, generating the subset of signals can include correlating the corresponding signal dependencies to an equation table. In another embodiment, generating the subset of signals can include encoding the corresponding signal dependencies. In yet another embodiment, generating the subset of signals includes compressing the subset. Generating the subset of signals can occur during a run time of the simulation.
Regenerating the target set of signals can include initializing the state elements and then advancing by clock cycles to regenerate the target set of signals. In one embodiment, regenerating the target set of signals can include decompressing the subset of signals. Regenerating the target set of signals can occur during an analysis time.
A value change file for an integrated circuit design is also described. The value change file can include traces for a plurality of state elements. In one embodiment, the value change file can further include at least one signal dependency. In another embodiment, the signal dependencies can be stored in a separate file or executable. Advantageously, a target set of signals can be regenerated using these traces and the signal dependencies.
A computer-implemented software tool for performing a simulation on an integrated circuit design is also described. The software tool can include code for determining a subset of signals and corresponding signal dependencies that can regenerate a target set of signals, code for generating the subset of signals, code for regenerating the target set of signals using the subset of signals and corresponding signal dependencies, and code for analyzing the target set of signals.
In accordance with one aspect of the invention, providing a subset of signals can significantly reduced the number of signals typically provided in a value change file. Advantageously, the subset of signals can regenerate a target set by using state elements (e.g. flip-flops or any other edge-triggered devices) and signal dependencies. Specifically, any signal that can be computationally derived from values stored by a set of state elements can be regenerated using the values of the signals in those state elements and the corresponding signal dependency.
For example, assume that a signal C of a design is computed by performing a logic AND operation using signals A and B, wherein signals A and B are provided by state elements. In this case, to regenerate a target set including signals A, B, and C, the value change file can include traces of signals A and B as well as a signal dependency to compute C, i.e. A AND B=C. Using signal regeneration in this example could reduce storage by approximately 30% (i.e. traces for the values of signals A and B, but not signal C, can be stored in the value change file).
In step 202, a subset of signals that can regenerate the target set can be determined. This determination can take into account both state elements and corresponding signal dependencies. A compiler in the simulator can perform step 202 during a compile time 211. In one embodiment of step 202, a set of state elements can be identified, wherein the set of state elements is less than all the state elements in the design. This set of state elements could be determined by some optimization identifiable using the compiler. In another more aggressive embodiment of step 202, all the state elements in the design can be identified.
In step 203, the subset of signals can be generated. The simulator can perform step 203 during a run time 212. The resulting subset can be optionally compressed using any compression technique. In one embodiment, the corresponding signal dependencies could be generated by the simulator and then encoded. In another embodiment, the corresponding signal dependencies could be correlated to an equation of an equation table.
Generating this subset of signals can dramatically decrease the size of the value change file. For example, the reduced file size of the subset as a fraction of the target set size can range from approximately 2% to 36%. Logically, the amount of reduction depends on the number of signals that can be regenerated. In general, a design including a significant amount of combinational logic can result in a smaller subset (and hence a smaller value change file) than another design including less combinational logic.
Note that the subset determination and target set regeneration of steps 202 and 203, respectively, can advantageously replace a conventional “dump” step (i.e. creating a standard value change file). A conventional dump step for a design including at least a million signals (which is becoming more the rule than the exception) can significantly slow down the run time of the simulator. Notably, the above-described subset generation and target set regeneration can significantly reduce run time 212. In some examples, this reduction can be from 32% to 48% of the original run time.
In step 204, the target set can be regenerated using the subset (which is decompressed, as necessary) and the corresponding signal dependencies. Note that step 204 can begin by initializing the state elements of the design and then advancing by clock cycles to regenerate the target set. The simulator can perform step 204 during an analysis time 213. In one embodiment, the VCS simulator, licensed by Synopsys, Inc., can implement steps 202-204 of
Note that because of target regeneration (step 204), analysis time 213 will take longer compared to a conventional analysis time. However, the additional time for analysis time 213 is more than compensated for by the time saved in run time 212 compared to a conventional run time. Therefore, a combined run/analysis time using target regeneration can still be considerably faster than a conventional combined run/analysis time.
Once the target set is regenerated, standard analysis of the target set can be performed in step 205.
Although illustrative embodiments of the invention have been described in detail herein with reference to the figures, it is to be understood that the invention is not limited to those precise embodiments. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. For example, other embodiments may utilize different techniques to generate the subset of signals and/or to encode the dependencies required to regenerate the target set.
Many modifications and variations of the above-described value change file will be apparent. Accordingly, it is intended that the scope of the invention be defined by the following claims and their equivalents.
