System and method for supporting multiple speech codecs

Abstract

A method for performing a search of a codebook is provided. The codebook includes a plurality of tracks each having a plurality of even pulse positions. The method includes partitioning a codevector having a plurality of pulses into a first subset of pulses and a second subset of pulses. Each pulse is assignable to a pulse position in the codevector, and each pulse is associated with a shift bit for indicating an odd position. The method also includes performing a first search for determining a first set of possible pulse positions for the pulses in the codevector. The method further includes performing a second search for determining a second set of possible pulse positions for the pulses in the codevector. In addition, the method includes forming the codevector using the first and second sets of possible pulse positions.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119 to Singapore Patent Application No. 200407882-0 filed on Dec. 31, 2004, which is hereby incorporated by reference.

TECHNICAL FIELD

This disclosure relates generally to communication systems and more specifically to a system and method for supporting multiple speech codecs.

BACKGROUND

Speech coders and decoders, often referred to collectively as “codecs,” are routinely used in communication systems to encode and decode speech signals. In general, codecs are often implemented in software executed by a digital signal processor (DSP). Different codecs often require different processing times, depending on their complexities and the speed of the processor.

Speech codecs that are widely used in various applications include the International Telecommunication Union-Telecommunications (ITU-T) G.723.1 and G.729A codecs. These are complex codecs that usually require large amounts of processing time and memory. Speech coders for both codecs use Algebraic-Code-Excited Linear-Prediction (ACELP), which is based on the Code-Excited Linear-Prediction (CELP) coding model.

Products used in many communication systems often need to support multiple speech codecs, such as in Digital Simultaneous Voice and Data (DSVD) systems and Voice over Internet Protocol (VoIP) systems. Products such as gateway applications also often need to support multiple channels. Large amounts of processing power and memory are typically needed in these products.

FIG. 1 illustrates a conventional ACELP encoder 100. The functional blocks in the ACELP encoder 100 that typically consume the highest proportion of processing power and memory are a Linear Predictive Coding (LPC) analysis block 102, an adaptive codebook search block 104, and a fixed codebook search block 106. Implementing these three functional blocks 102-106 on a co-processor could allow the processing capacity of the DSP to be used for other computations and functions. However, the disparity between different speech codecs often requires that each codec be implemented on a separate co-processor. As a result, supporting multiple codecs would typically require the use of multiple co-processors.

Also, the fixed codebook search algorithms for the G.723.1 (5.3 kbps) and G.729A codecs are based on algebraic codebook searches. Implementing fixed codebook searches for both codecs on a single co-processor could reduce the complexity of the system. This could also allow unused processing power and memory of the DSP to be used for other functions, such as supporting multiple channels and other application-specific modules. However, fixed codebook searches for the G.729A codec use a “depth-first tree search” algorithm, while fixed codebook searches for the G.723.1 codec use a “nested-loop search” or a “focused nested-loop search” algorithm. The “focused nested-loop search” and the “depth-first tree search” algorithms are distinctly different. Attempting to implement these two fixed codebook searches, which are associated with different search algorithms for different codecs, may not result in the desired effect of freeing up processing power or memory. Instead, an additional processing burden would be imposed on the co-processor. Implementing the fixed codebook searches on two different co-processors may be more effective but not necessarily more efficient.

SUMMARY

This disclosure provides a system and method for supporting multiple speech codecs.

In a first aspect, a method for performing a search of a codebook is provided. The codebook includes a plurality of tracks each having a plurality of even pulse positions. The method includes partitioning a codevector having a plurality of pulses into a first subset of pulses and a second subset of pulses. Each pulse is assignable to a pulse position in the codevector, and each pulse is associated with a shift bit for indicating an odd position. The method also includes performing a first search for determining a first set of possible pulse positions for the pulses in the codevector. The method further includes performing a second search for determining a second set of possible pulse positions for the pulses in the codevector. In addition, the method includes forming the codevector using the first and second sets of possible pulse positions.

In particular aspects, the method includes repeating the partitioning, performing, and forming steps to produce a second codevector associated with a second codebook. The second codevector includes pulses not associated with shift bits, and the second codebook includes tracks having a plurality of odd and even pulse positions. In other particular aspects, the codebook represents a G.723.1 codebook, and the second codebook represents a G.729A codebook.

In a second aspect, a system includes a processor capable of performing functions for at least one of encoding and decoding communication signals. The system also includes a co-processor capable of performing a search of a codebook to support at least one of encoding and decoding of the communication signals. The codebook includes a plurality of tracks each having a plurality of even pulse positions. The co-processor is capable of performing the search by partitioning a codevector having a plurality of pulses into a first subset of pulses and a second subset of pulses. Each pulse is assignable to a pulse position in the codevector, and each pulse is associated with a shift bit for indicating an odd position. The co-processor is also capable of performing a first search for determining a first set of possible pulse positions for the pulses in the codevector. The co-processor is further capable of performing a second search for determining a second set of possible pulse positions for the pulses in the codevector. In addition, the co-processor is capable of forming the codevector using the first and second sets of possible pulse positions.

In a third aspect, a computer program is embodied on a computer readable medium and is operable to be executed by a processor. The computer program is for performing a search of a codebook, where the codebook includes a plurality of tracks each having a plurality of even pulse positions. The computer program includes computer readable program code for partitioning a codevector having a plurality of pulses into a first subset of pulses and a second subset of pulses. Each pulse is assignable to a pulse position in the codevector, and each pulse is associated with a shift bit for indicating an odd position. The computer program also includes computer readable program code for performing a first search for determining a first set of possible pulse positions for the pulses in the codevector. The computer program further includes computer readable program code for performing a second search for determining a second set of possible pulse positions for the pulses in the codevector. In addition, the computer program includes computer readable program code for forming the codevector using the first and second sets of possible pulse positions.

Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of this disclosure, reference is now made to the following description, taken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a conventional Algebraic-Code-Excited Linear-Prediction (ACELP) encoder;

FIG. 2 illustrates a method for performing a fixed codebook search according to one embodiment of this disclosure;

FIG. 3 illustrates a method for performing a depth-first tree search during the method of FIG. 2 according to one embodiment of this disclosure;

FIG. 4 illustrates a method for performing a first search during the method of FIG. 3 according to one embodiment of this disclosure;

FIG. 5 illustrates a method for performing a second search during the method of FIG. 3 according to one embodiment of this disclosure;

FIGS. 6A through 6C illustrate simulation results of the method of FIG. 2 according to one embodiment of this disclosure;

FIGS. 7A through 7C illustrate speech samples during testing of the method of FIG. 2 according to one embodiment of this disclosure;

FIG. 8 illustrates a processing flow in a system supporting multiple speech codecs according to one embodiment of this disclosure;

FIG. 9 illustrates an encoder supporting the G.723.1 codec according to one embodiment of this disclosure; and

FIGS. 10A and 10B illustrate DSP and co-processor designs supporting multiple speech codecs according to one embodiment of this disclosure.

DETAILED DESCRIPTION

FIGS. 2 through 10B, discussed below, and the various embodiments described in this disclosure are by way of illustration only and should not be construed in any way to limit the scope of the claimed invention. Those skilled in the art will understand that the principles described in this disclosure may be implemented in any suitably arranged device or system.

As described in more detail below, particular embodiments of this disclosure may support multiple codecs on a single co-processor. For example, the G.723.1 (5.3 kbps) codec and the G.729A codec could be supported on a single co-processor. Also, a single fixed codebook search algorithm may be used for both the G.723.1 codec and the G.729A codec. This may help to simplify the fixed codebook search process so that a single co-processor running the fixed codebook search algorithm may be used for both codecs. As a particular example, the fixed codebook search algorithm of the G.723.1 codec could be modified to be similar to that of the G.729A codec, such as by using a “depth-first tree search” fixed codebook search algorithm with the G.723.1 codec as well as with the G.729A codec.

Fixed codebook search algorithms are typically used in conjunction with a codebook. A codebook, in the CELP context, typically represents an indexed set of L-sample long sequences, referred to as L-dimensional “codevectors.” The codebook includes an index ν ranging from 1 to M, where M represents the size of the codebook. The size of the codebook may be expressed as a number of bits b, where: M=2^b.  (1) An algebraic codebook typically represents a set of indexed codevectors ν_ξ. Each codevector defines a plurality of different positions p and N non-zero amplitudes pulses, where each pulse is assignable to a predetermined valid position p of the codevector. The amplitudes and positions of the pulses of the ξ^th codevector can be derived from a corresponding index ξ through a rule requiring minimal physical storage. Therefore, algebraic codebooks typically are not limited by storage requirements and are designed for efficient searches.

The conventional G.723.1 (5.3 kbps) codebook search uses a 17-bit algebraic codebook for a fixed code excitation v[n]. Each fixed codevector contains, at most, four non-zero pulses. The four pulses can assume the signs and positions shown in Table 1.

TABLE 1
Pulse
Number	Track	Sign	Positions
0	T0	S0: ±1	m0: 0, 8, 16, 24, 32, 40, 48, 56
1	T1	S1: ±1	m1: 2, 10, 18, 26, 34, 42, 50, 58
2	T2	S2: ±1	m2: 4, 12, 20, 28, 36, 44, 52, (60)
3	T3	S3: ±1	m3: 6, 14, 22, 30, 38, 46, 54, (62)

A codebook vector v(n) may be constructed by taking a zero vector of dimension 60 and placing four unit pulses at four locations (each pulse multiplied with its corresponding sign). This can be represented by the following equation: v(n)=s₀δ(n m₀)+s₁δ(nm₁)+s₂δ(nm₂)+s₃δ(nm₃),n=0, . . . , 59  (2) where δ (0) represents a unit pulse.

The positions of the pulses can be simultaneously shifted by one (to occupy odd positions). This may require the use of an extra bit, referred to as a “shift bit.” The last position of each of the last two pulses may fall outside a subframe boundary, which signifies that the pulses are not present.

In some embodiments, each pulse position is encoded in three bits, and each pulse sign is encoded in one bit. This gives a total of sixteen bits for the four pulses. Also, an extra bit may be used to encode the shift, resulting in a 17-bit codebook.

The codebook may be searched by minimizing a mean square error between a weighted speech signal r[n] and a weighted synthesis speech signal. This may be expressed as: $\begin{array}{cc}{E}_{\xi }=r-{\mathrm{GHv}}_{\xi }& \left(3\right)\end{array}$ where E represents the error, r represents a target vector containing the weighted speech signal after subtracting a zero-input response of a weighted synthesis filter and a pitch contribution, G represents the codebook gain, v_ξ represents the algebraic codeword at index ξ, and H represents a lower triangular Toeplitz convolution matrix with diagonal h(0) and lower diagonals h(1), . . . , h(L−1), with h(n) being the impulse response of the weighted synthesis filter S_i(z). It can be shown that an optimum codeword is one that maximizes the term: $\begin{array}{cc}{\tau }_{\xi }=\frac{C_{\xi }^2}{{\varepsilon }_{\xi }}=\frac{{\left(d^T{v}_{\xi }\right)}^2}{v_{\xi }\phi v_{\xi }}& \left(4\right)\end{array}$ where C_ξ represents a correlation value at index ξ, ε_ξ represents an energy at index ξ, d=H^Tr represents a correlation between the target vector signal r[n] and the impulse response h(n), and φ=H^TH represents the covariance matrix of the impulse response. The vector d and the matrix φ may be computed prior to the codebook search. The elements of the vector d may be computed using the following formula: $\begin{array}{cc}d\left(j\right)=\sum _{n=j}^{59}r\left[n\right]·h\left[n-j\right],0\le j\le 59.& \left(5\right)\end{array}$ The elements of the symmetric matrix φ(i,j) may be computed using the following formula: $\begin{array}{cc}\phi \left(i,j\right)=\sum _{n=j}^{59}h\left[n-i\right]·h\left[n-j\right],j\ge i,0\le i\le 59.& \left(6\right)\end{array}$

The algebraic structure of the codebook allows for very fast search procedures since the excitation vector v_ξ contains only four non-zero pulses. The conventional G.723.1 (5.3 kbps) codebook search is performed in four nested loops corresponding to each pulse position, where in each loop the contribution of a new pulse is added.

The correlation in equation (4) may be given by: C=α₀d[m₀]+α₁d[m₁]+α₂d[m₂]+α₃d[m₃]  (7) where m_k represents the position of the k^th pulse, and α_k represents the sign (±1) of the k^th pulse. The energy for even pulse position codevectors in equation (4) may be given by: $\begin{array}{cc}\varepsilon =\sum _{i=0}^3\phi \left(m_i,m_i\right)+2\sum _{i=0}^2\sum _{j=i+1}^3{\alpha }_i{\alpha }_j\phi \left(m_i,m_j\right).& \left(8\right)\end{array}$ For odd pulse position codevectors, the energy in equation (4) may be approximated by the energy of the equivalent even pulse position codevector obtained by shifting the odd position pulses to one sample earlier in time.

To simplify the search procedure, the functions d[j] and φ(m_i,m_j) may be modified. This simplification may be performed as follows, and it may occur prior to the codebook search. The signal s[j] is defined using the following formula: s[2j]=s[2j+1]=sign(d[2j])if d[2j]>|d[2j+1]s[2j]=s[2j+1]=sign(d[2j+1])otherwise.  (9) A signal d′[j] is constructed as given by d′[j]=d[j]s[j]. The matrix φ may be modified by including the signal information, where φ′(i,j)=s[i]s[j]φ(i,j). The correlation in equation (7) may now be expressed as: C=d′[m₀]+d′[m₁]+d′[m₂]+d′[m₃].  (10) The energy in equation (8) may now be expressed as: $\begin{array}{cc}\varepsilon =\sum _{i=0}^3{\phi }^{\prime }\left(m_i,m_i\right)+2\sum _{i=0}^2\sum _{j=i+1}^3{\phi }^{\prime }\left(m_i,m_j\right),& \left(11\right)\end{array}$ which may be further expanded to obtain: $\begin{array}{cc}\varepsilon ={\phi }^{\prime }\left(m_0,m_0\right)+{\phi }^{\prime }\left(m_1,m_1\right)+2{\phi }^{\prime }\left(m_0,m_1\right)+{\phi }^{\prime }\left(m_2,m_2\right)+2\left[{\phi }^{\prime }\left(m_0,m_2\right)+{\phi }^{\prime }\left(m_1,m_2\right)\right]+{\phi }^{\prime }\left(m_3,m_3\right)+2\left[{\phi }^{\prime }\left(m_0,m_3\right)+{\phi }^{\prime }\left(m_1,m_3\right)+{\phi }^{\prime }\left(m_2,m_3\right)\right].& \left(12\right)\end{array}$

In conventional G.723.1 (5.3 kbps) codecs, the four pulses are divided into four tracks, each pulse position corresponds to one track, and each track has eight possible pulse positions. In an “exhaustive nested-loop search” approach, there are four nested loops. A “focused nested-loop search” approach is used to simplify the search procedure. A predetermined threshold is tested before entering the last loop, and the loop is entered only if this threshold is exceeded. The maximum number of times the loop can be entered is fixed so that a lower percentage of the codebook is searched. This threshold is computed based on the correlation C as given in equation (10). The maximum absolute correlation max₃ and the average correlation av₃ due to the contribution of the first three pulses may be found prior to the codebook search. The threshold may be given by: thr₃=av₃+(max₃−av₃)/2.  (13)

The fourth loop is then entered only if the absolute correlation (due to three pulses) exceeds the value of thr₃. This results in a variable complexity search. To further control the search, the number of times the last loop is entered (for four subframes) may not be allowed to exceed 600 (the average worst case per subframe is 150 times, which can be viewed as searching only 150×8 or 2,000 entries of the codebook, ignoring the overhead of the first three loops). In exhaustive nested-loop searches, 8⁴ or 4,096 possible pulse positions are searched.

In the conventional G.729 codec, the fixed codebook is based on an algebraic codebook structure using an Interleaved Single-Pulse Permutation (ISPP) design. In this codebook, each codebook vector contains four non-zero pulses. Each pulse can have either the amplitude +1 or −1. Also, each pulse can assume the positions given in Table 2, which illustrates the structure of the fixed codebook.

TABLE 2
Pulse
Number	Track	Sign	Positions
0	T0	S0: ±1	m0: 0, 5, 10, 15, 20, 25, 30, 35
1	T1	S1: ±1	m1: 1, 6, 11, 16, 21, 26, 31, 36
2	T2	S2: ±1	m2: 2, 7, 12, 17, 22, 27, 32, 37
3	T3	S3: ±1	m3: 3, 8, 13, 18, 23, 28, 33, 38
			4, 9, 14, 19, 24, 29, 34, 39

The codebook vector v(n) may be constructed by taking a zero vector of dimension 40 and placing four unit pulses at four locations (each pulse multiplied with its corresponding sign). This can be represented by the following equation: v(n)=s₀δ(nm₀)+s₁δ(nm₁)+s₂δ(nm₂)+s₃δ(nm₃),n=0, . . . , 39  (14) where δ(0) represents a unit pulse.

The fixed codebook may be searched by minimizing a mean squared error as shown in equation (3). The matrix H may be defined as the lower triangular Toeplitz convolution matrix with diagonal h(0) and lower diagonal h(1), . . . , h(39). The matrix φ=H^tH may contain the correlations of h(n), and the elements of this symmetric matrix may be given by: $\begin{array}{cc}\phi \left(i,j\right)=\sum _{n=j}^{39}h\left[n-i\right]·h\left[n-j\right],j\ge i,0\le i\le 39.& \left(15\right)\end{array}$ The correlation signal d(n) may be obtained from the target signal r(n) and the impulse response h(n) by: $\begin{array}{cc}d\left(j\right)=\sum _{n=j}^{39}r\left[n\right]·h\left[n-j\right],0\le j\le 39.& \left(16\right)\end{array}$ If ν_ξ is the ξ^th fixed codebook vector, the codebook may be searched by maximizing the term: $\begin{array}{cc}{\tau }_{\xi }=\frac{C_{\xi }^2}{{\varepsilon }_{\xi }}=\frac{{\left(\sum _{n=0}^{39}d\left(n\right)v_{\xi }\left(n\right)\right)}^2}{v_{\xi }\phi v_{\xi }}& \left(17\right)\end{array}$ The signal d(n) and the matrix φ may be computed before the codebook search. Only the elements actually needed may be computed, and an efficient storage procedure may speed up the search procedure.

The algebraic structure of the codebook allows for a fast search procedure since the codebook vector v_ξ contains only four non-zero pulses. The correlation in the numerator of equation (17) for a given vector ν_ξ may be given by: C=α₀d[m₀]+α₁d[m₁]+α₂d[m₂]+α₃d[m₃]  (18) where m_i represents the position of the i^th pulse, and α_i represents the amplitude of the i^th pulse. The energy in the denominator of equation (17) may be given by: $\begin{array}{cc}\varepsilon =\sum _{i=0}^3\phi \left(m_i,m_i\right)+2\sum _{i=0}^2\sum _{j=i+1}^3{\alpha }_i{\alpha }_j\phi \left(m_i,m_j\right).& \left(19\right)\end{array}$

To simplify the search procedure, the pulse amplitudes may be predetermined by quantizing the signal d(n). This may be done by setting the amplitude of a pulse at a certain position equal to the sign of d(n) at that position. Before the codebook search, the following steps may be performed. The signal d(n) may be decomposed into two parts, its absolute value |d(n)| and its sign (denoted “sign [d (n)] ”). The matrix φ may be modified by including the sign information, such as: φ′(i,j)=sign[d(i)]sign[d(j)]φ(i,j),i=0, . . . , 39,j=i+1, . . . 39.  (20) The main-diagonal elements of φ may be scaled to remove the factor of two in Equation (19) as follows: φ′(i,i)=0.5φ′(i,i),i=0 . . . , 39.  (21) The correlation in Equation (18) may now be given by: C=|d(m₀)+|d(m₁)|+|d(m₂)|+|d(m₃)|.  (22) The energy in Equation (19) may now be given by: $\begin{array}{cc}\frac{\varepsilon }{2}=\sum _{i=0}^3{\phi }^{\prime }\left(m_i,m_i\right)+\sum _{i=0}^2\sum _{j=i+1}^3{\phi }^{\prime }\left(m_i,m_j\right),& \left(23\right)\end{array}$ which may be further expanded to obtain: $\begin{array}{cc}\begin{array}{c}\frac{\varepsilon }{2}={\phi }^{\prime }\left(m_0,m_0\right)+{\phi }^{\prime }\left(m_1,m_1\right)+{\phi }^{\prime }\left(m_0{m}_1\right)+\\ {\phi }^{\prime }\left(m_2,m_2\right)+{\phi }^{\prime }\left(m_0,m_2\right)+{\phi }^{\prime }\left(m_1,m_2\right)+\\ {\phi }^{\prime }\left(m_3,m_3\right)+{\phi }^{\prime }\left(m_0,m_3\right)+{\phi }^{\prime }\left(m_1,m_3\right)+{\phi }^{\prime }\left(m_2,m_3\right)\end{array}& \left(24\right)\end{array}$

A “focused nested-loop search” approach may be used to further simplify the search procedure. In this approach, a precomputed threshold may be tested before entering the last loop, and the loop is entered only if this threshold is exceeded. The maximum number of times the loop can be entered is also fixed so that a low percentage of the codebook is searched. The threshold may be computed based on the correlation C. The maximum absolute correlation max₃ and the average correlation av₃ due to the contribution of the first three pulses may be found before the codebook search. The threshold may be given by: thr₃=av₃+K₃(max₃−av₃).  (25) The fourth loop may be entered only if the absolute correlation (due to three pulses) exceeds thr₃, where 0≦K₃<1. The value of K₃ controls the percentage of the codebook searched, and it may be set to 0.4 as an example. This results in a variable search time. To further control the search, the number of times that the last loop is entered (for two subframes) may not exceed a certain maximum, which may be set to 180 (the average worst case per subframe is 90 times, so the total possible pulse search combination would be 180*8 or 1,440). In exhaustive nested-loop searches, 8⁴*2 or 8,192 possible pulse positions are searched.

In a fixed codebook search for the G.729A codec, a “depth-first tree search” algorithm is used in place of a “focused nested-loop search.” In the G.729 codec, a fast search procedure based on a nested-loop search approach is used, and only 1,440 possible position combinations are tested in the worst case out of 213 position combinations (17.5 percent). In the G.729A codec, search criteria C²/ε tested for a smaller percentage of possible position combinations using a depth-first tree search approach. In this approach, the P excitation pulses in a subframe are partitioned into M subsets of N_m pulses. The search begins with the first subset and proceeds with subsequent subsets according to a tree structure, whereby subset m is searched at the m^th level of the tree. The search may be repeated by changing the order in which pulses are assigned to the position tracks.

In particular codebook structures, the pulses may be partitioned into two subsets (M=2) of two pulses (N_m=2). The codebook search is started with the following assignments of pulses to tracks: pulse i₀ is assigned to track T₂, pulse i₁ is assigned to track T₃, pulse i₂ is assigned to track T₀, and pulse i₃ is assigned to track T₁. The search starts with determining the positions of pulses i₀ and i₁ by testing a predetermined search criteria for 2×8 or 16 position combinations (i.e. the positions at two maxima of |d(n)| in track T₂ are tested in combination with the eight positions in track T₃). Once the positions of pulses i₀ and i₁ are found, the search proceeds to determine the positions of pulses i₂ and i₃ by testing the search criteria for the 8×8 or 64 position combinations in tracks T₀ and T₁. The procedure is repeated by cyclically shifting the pulse assignments to the tracks, such as when pulse i₀ is assigned to track T₃, pulse i₁ is assigned to track T₀, pulse i₂ is assigned to track T₁, and pulse i₃ is assigned to track T₂. The whole procedure is repeated twice by replacing track T₃ with track T₄ since the fourth can be placed in either T₃ or T₄. Thus, in total, (64+16)*4 or 320 position combinations are tested (about 3.9 percent of all possible position combinations). About fifty percent of the complexity reduction in the coder may be attributed to the new algebraic codebook search. This is at the expense of a slight degradation in coder performance (about 0.2 dB drop in the signal-to-noise ratio).

The positions of pulses i₀, i₁ and i₂ may be encoded with three bits each, and the position of pulse i₃ may be encoded with four bits. Each pulse amplitude may be encoded with one bit. This gives a total of 17 bits for the four pulses. By defining s=1 if the sign is positive and s=0 if the sign is negative, the sign codeword may be obtained from: S=s₀+2s₁+4s₂+8s₃,  (25) and the fixed codebook codeword may be obtained from: C=(m₀/5)+8(m₁/5)+64 (m₂/5)+512(2(m₃/5)+jx)  (26) where jx=0 if m₃=3,8, . . . , 38 and jx=1 if m₃=4,9 . . . , 39.

A “focus nested-loop search” algorithm is currently used for conventional G.723.1 and G.729 codebook searches. A “depth-first tree search” algorithm is currently used for G.729A codebook searches. By adopting a single fixed codebook search algorithm for both G.723.1 and G.729A, this may simplify the fixed codebook search process so that a single co-processor running one fixed codebook search algorithm may be used for both codecs.

This disclosure proposes a new G.723.1 codebook search algorithm based on a “depth-first tree search” approach, thus having the desired effect of providing one fixed codebook search for both G.723.1 and G.729A codecs. In general, the proposed G.723.1 codebook search algorithm searches a subset of pulses in a subset of tracks rather than searching in a full range of tracks, thereby reducing the number of possible pulse positions being searched.

The similarities and differences between the G.723.1 and G.729A fixed codebook searches are shown below. There are several fixed parameters for both speech codecs:

• • Number of pulses (N)=4 (both codecs)
  • Number of samples per subframe=40/60 (G.729A/G.723.1)
  • Number of tracks=4 (both codecs)
  • Number of pulse positions per track=8 (both codecs)
  • Step for speech codec=5/8 (G.729A/G.723.1). Also, the initial pulse positions for the speech codecs are different. For the G.723.1 codec, the initial positions are i₀=0, i₁=2, i₂=4, and i₃=6. For the G.729A codec, the initial positions are i₀=0, i₁=1, i₂=2, and i₃=3. This can be seen by comparing Table 1 and Table 2 above.

FIG. 2 illustrates a method 200 for performing a fixed codebook search according to one embodiment of this disclosure. The method 200 adopts a “depth-first tree search” algorithm approach for a G.723.1 fixed codebook search.

The method 200 begins by computing a sign of the correlation signal d(n) at step 210. This may occur in the same or similar manner as in the conventional ITU-T G.723.1 codec. Depending on the sign, cross correlation values d(n) between target signal r(n) and impulse response h(n) are modified at step 215. The main diagonal elements of φp(n) are scaled at step 220 to remove the factor of two as given in equation (11) above. A depth-first tree search is used to find the best possible pulse positions that maximize search criteria at step 225. One example of step 225 is shown in FIG. 3. Finally, a 17-bit codebook vector is computed at step 230.

FIG. 3 illustrates a method 225 for performing a depth-first tree search during the method of FIG. 2 according to one embodiment of this disclosure. As noted above in Table 1, the ACELP codebook for G.723.1 (5.3 kbps) has four pulses that are searched for in four tracks. The method 225 for applying the depth-first tree search begins by partitioning the pulses of the optimum codevector into a first subset and a second subset (M=2) at step 310. The first subset has a first pulse and a second pulse, and the second subset has the third and fourth pulse (N_m=2).

The method 225 then proceeds with performing a first search for determining a first possible set of pulse positions at step 315, followed by performing a second search for determining a second possible set of pulse positions at step 320. Each search includes two phases (denoted “A” and “B”), providing the following sequence:

• • Search 1, Phase A
  • Search 1, Phase B
  • Search 2, Phase A
  • Search 2, Phase B. One example of step 315 is shown in FIG. 4, and one example of step 320 is shown in FIG. 5. In some embodiments, the first codebook search at step 315 begins with the following pulse/track assignments: pulse i₀ is assigned to the third track T₂, pulse i₁ is assigned to the fourth track T₃, pulse i₂ is assigned to the first track T₀, and pulse i₃ is assigned to the second track T₁.

FIG. 4 illustrates a method 315 for performing a first search during the method of FIG. 3 according to one embodiment of this disclosure. In particular, the method 315 is used to determine a first set of possible pulse positions.

In Phase A of Search 1, the positions of pulses i₀ and i₁ are determined by testing the search criteria for 2×8 or 16 position combinations. In other words, the positions at two maxima of |d(n)| in track T₂ (including even and odd indexed pulse positions) are tested in combination with the eight positions in track T₃ (including odd and even indexed pulse positions). In this manner, the positions of pulses i₀ and i₁ are found.

The method 315 begins by determining the two maximum pulse positions in the third track assignable to the first pulse i₀ at step 410. Next, the pulse positions in the fourth track are tested in combination with each of the two maximum pulse positions in the third track at step 415. This results in one maximum pulse position being assignable to the second pulse i₁. The positions of pulses i₀ and i₁ for the first set of possible pulse positions are then determined in accordance with the predetermined search criteria at step 420.

In Phase B of Search 1, the search proceeds to determine the positions of pulses i₂ and i₃ by testing the search criteria for the 8×8 or 64 position combinations in tracks T₀ and T₁ (including odd and even indexed pulse positions). The method 315 continues by testing the pulse positions in the second track in combination with each of the pulse positions in the first track at step 425. The pulse positions of the third pulse and the fourth pulse in the first set of possible pulse positions are determined in accordance with the predetermined search criteria at step 430. In this manner, the positions of pulses i₂ and i₃ are found, and a total of 16+64 or 80 possible pulse position combinations have been searched.

In other embodiments, the correlation signal values of each pulse position of the first set are compared at both even and odd indexed pulse positions. Whichever value is higher may be selected and re-assigned as the pulse position. If the odd indexed correlation signal value is higher, the “shift bit” value may be set to one. Otherwise, if the even correlation signal value is higher, the “shift bit” value may be set to zero. This may be summarized as follows:

if (dn[i] > dn[i+1]) // where i is even index
shift = 0
else
shift = 1.

FIG. 5 illustrates a method 320 for performing a second search during the method of FIG. 3 according to one embodiment of this disclosure. In particular, the method 320 is used to determine a second set of possible pulse positions.

The method 320 begins by performing a cyclical shift of the pulse assignments to the tracks at step 510. For example, pulse i₀ may be reassigned to track T₃, pulse i₁ may be reassigned to track T₀, pulse i₂ may be reassigned to track T₁, and pulse i₃ may be reassigned to track T₂.

In Phase A of Search 2, a procedure similar to that of step 315 is performed. The two maximum pulse positions in the fourth track assignable to the first pulse i₀ are determined at step 515. The pulse positions in the first track are tested in combination with each of the two maximum pulse positions in the fourth track at step 520. This may result in one maximum pulse position assignable to the second pulse i₁. The pulse positions i₀ and i₁ for the second set of possible pulse positions are then determined in accordance with the predetermined search criteria at step 525.

In Phase B of Search 2, the positions i₂ and i₃ are determined by testing the search criteria for the 8×8 or 64 position combinations in tracks T₃ and T₀ (including odd and even indexed pulse positions). The pulse positions in the third track are tested in combination with each of the pulse positions in the second track at step 530. The pulse positions of the third pulse and the fourth pulse of the second set are determined in accordance with the predetermined search criteria at step 535.

In other embodiments, the correlation signal values of each pulse position of the second set are again compared at both even and odd indexed pulse positions. Thus, in total, (64+16)*2 or 160 position combinations are searched. This may compare to, for example, approximately 2,000 positions searched in the original ITU-T G.723.1 fixed codebook search, which represents about 8 percent of the original G.723.1 fixed codebook search.

The first and second sets of possible pulse positions may then be compared. The four final pulse positions are then selected from the first and second sets, and the selected pulse positions and their sign and shift values are used to compute the 17-bit codebook vector. In this way, decoder compatibility may not be lost due to the change in the algorithm. Using this technique, there may be up to a 50 percent or more reduction in the complexity of the G.723.1 (5.3 kbps) algebraic codebook search.

FIGS. 6A through 6C illustrate simulation results of the method of FIG. 2 according to one embodiment of this disclosure. The simulations were performed for both the ITU-T version of the G.723.1 search algorithm and for the algorithm of FIG. 2 using 23 speech test vectors. About 20 speech test vectors were taken from the ITU-T P.862 standards, where the test vectors are generated from different sources (including women, men, and children, as well as different language speakers). Three other test vectors represent sample test speech vectors of about one minute each. Three types of validation tests were carried out, including Perceptual Evaluation of Speech Quality (PESQ) Mean Opinion Score (MOS), Signal-to-Noise Ratio (SNR), and Segmental Signal-to-Noise Ratio (SEGSNR).

FIG. 6A shows the PESQ-MOS score comparison for the algorithm of FIG. 2 and the ITU-T algorithm using the 23 test vectors. The PESQ-MOS score for the modified algorithm varies from 3.4 to 3.55 for different test vectors, as compared to the PESQ-MOS score for the original ITU-T algorithm that varies from 3.5 to 3.8. This shows a slight (5-8 percent) degradation of the PESQ-MOS score for the modified algorithm of FIG. 2 as compared to the original ITU-T algorithm. However, this degradation in performance is balanced by more than 50 percent savings in the complexity of the algorithm.

FIGS. 6B and 6C show the SNR and SEGSNR performances, respectively, of both algorithms for the 23 speech test vectors. The results show an approximate 2 dB SNR degradation and an approximate 1.5 dB SEGSNR degradation in the modified algorithm compared to the original ITU-T algorithm.

FIGS. 7A through 7C illustrate speech samples during testing of the method of FIG. 2 according to one embodiment of this disclosure. In particular, FIG. 7A shows an original speech signal used for testing the ITU-T algorithm and the modified algorithm of FIG. 2. FIGS. 7B and 7C show reconstructed speech signals generated using the original algorithm and the modified algorithm, respectively. As can be seen, the reconstructed speech signal generated using the modified algorithm closely approximately the original signal and the reconstructed signal generated using the original algorithm.

Listening tests were also carried out for different speech test vectors by different subjects. There was generally no significant degradation in the perceived speech quality as compared to the original ITU-T algorithm. As a result, the modified algorithm, while possibly providing a slight degradation in speech quality, results in savings of more than 50 percent in processing power over the standard algorithm.

Based on these algorithmic changes to the G.723.1 codebook search algorithm, it is possible to implement a single co-processor solution that supports codebook searches for multiple speech codecs, such as the G.723.1 (5.3 kbps) and G.729A codecs.

FIG. 8 illustrates a processing flow in a system 800 supporting multiple speech codecs according to one embodiment of this disclosure. As shown in this example, the system 800 includes a DSP 802 and a co-processor 804 supporting multiple speech codecs.

A fixed codebook search may be performed twice in each frame for the G.729A speech codec, while a fixed codebook search may be performed four times in a frame for the modified G.723.1 algorithm. This may be handled in a co-processor design by varying the number of times the fixed codebook search is called by the DSP 802. Also, reconfigurable parameters of both speech codecs can be configured by the DSP 802 before the start of processing by the co-processor 804, and the DSP 802 may pass the parameters to the co-processor 804. The reconfigurable parameters may include:

• • Number of pulses (N)=4
  • Number of samples per subframe (SubFrLen)=40/60
  • Number of tracks=4
  • Number of pulse positions per track=8
  • Step for speech codec=5/8
  • Initial pulse positions (0, 2, 4, 6 or 0, 1, 2, 3). There may be an additional reconfigurable parameter SubFrLen2 for the G.723.1 codec. The SubFrLen value may be fixed at 40 or 60. When considering track T₂ and track T₃ in the G.723.1 codec, SubFrLen2 is set at 62 to accommodate the maximum pulse position index of 60 and 62 as shown in Table 1. During a G.723.1 codebook search, pulses searched in track T₂ and track T₃ end at SubFrLen2 (i.e. 62) instead of SubFrLen (i.e. 60). As noted above, if the pulses are found at positions 60 and 62, they are not considered.

From the codebook structure for both speech codecs shown in Table 1 and Table 2, it can be seen that the G.729A codebook structure has continuous pulse positions from 0-39, while the G.723.1 (5.3 kbps) codebook structure has only even indexed pulse positions from 0-62. Odd indexed pulse position conditions are taken care of by comparing the correlation signal values |d (n)| at both odd and even indexes. Depending on this comparison, a “shift” value is computed as explained above. In G.729A, there is no concept of even and odd indexed pulse positions, and it is therefore unaffected.

In the co-processor design for supporting both codecs in accordance with this disclosure, a codec flag may be implemented for identifying which codec is to be handled. The codec flag could also indicate which parameters to adopt during operation. As such, the same codec flag may be used to handle the added indexed pulses of G.723.1. During the codebook search for G.729A, the fourth pulse i₃ is selected from track T₃ or track T₄. The algorithm thus starts from track T₃, and the process is repeated by replacing track T₃ by track T₄. When considering this in co-processor 804, the same codec flag may be used to indicate the repetition of the algorithm for G.729A by replacing track T₃ by track T₄.

While maintaining compatibility with ITU-T G.723.1 and ITU-T G.729A decoders, other portions of the fixed codebook search remains the same. The other portions of the algorithm may include computing the sign of the correlation signal d(n), modifying the cross correlation values, and computing the 17-bit codebook vector.

Codebook searches for both speech codecs include computing the autocorrelation value φ(n) of the impulse response h(n) and computing the cross correlation value d(n) using the target signal r(n) and the impulse response h(n). These values may be computed before the start of a codebook search. The way these values are computed may be similar for both speech codecs, except for differences in subframe size (which is a reconfigurable parameter).

Using the new modified algorithm for the G.723.1 (5.3 kbps) fixed codebook search, a single implementation of the G.723.1 and G.729A codebook searches on the co-processor 804 can be made. Codec selection is made using the codec flag and the reconfigurable parameters, which are controlled by the DSP 802. The co-processor 804 mainly handles aspects of the fixed codebook search. The functionality of the co-processor 804 includes:

check the codec flag for G.723.1 or G.729A encoding;

configure the reconfigurable parameters depending on the codec flag;

compute the co-variance φ(n) and the cross-correlation value d(n);

compute the sign and modify the co-variance values depending on the codec flag;

perform pulse assignment and “depth-first tree search” depending on the codec flag (whole range search is repeated for track T₃ and T₄ in G.729A, and “shift” value is computed depending on even and odd index value in G.723.1); and

compute the 17-bit codevector based on the pulse position indexes and flags.

FIG. 9 illustrates an encoder 900 supporting the G.723.1 codec according to one embodiment of this disclosure. As shown in FIG. 9, certain modules of the encoder 900 are grouped into blocks denoted “Block A” and “Block B.” The components in the two blocks may be implemented independently, meaning the blocks could be implemented or supported by different components (such as the DSP 802 and the co-processor 804) simultaneously. In particular embodiments, Block A could be implemented in the co-processor 804 via hardware, and Block B could be implemented in the DSP 802 via software.

In this example, Block A contains a pitch estimator, a Formant Perceptual Weighting filter, and a Harmonic Noise Shaping module. Block B contains Line Spectrum Pair (LSP) routines. Both Blocks A and B may be synchronized so that weighted speech W(z) and noise shaper response P(z) are available for the impulse response calculation. In this manner, processing power is reduced by about 17 percent for G.723.1 (5.3 kbps) and about 11 percent for G.723.1 (6.3 kbps).

FIGS. 10A and 10B illustrate DSP and co-processor designs supporting multiple speech codecs according to one embodiment of this disclosure. In particular, FIG. 10A illustrates a configuration of the system 800 for supporting G.723.1. The DSP 802 is used for high pass filtering and LPC analysis. The co-processor 804 then takes over for the processing of Block A, while Block B continues to be processed by the DSP 802. The co-processor 804 can then perform the fixed codebook search upon completion of the Block A processing. This allows for the simultaneous processing of both Block A and Block B. It is estimated that by using this proposed design, 30-40 percent or more of the processing power may be saved.

Similarly, FIG. 10B illustrates a configuration of the system 800 for supporting G.729A. This configuration may also save up to 30 percent or more of the processing power. The DSP 802 is used for high pass filtering, LPC/LSP analysis, and adaptive codebook searches, while the co-processor 804 is used for fixed codebook searches.

In some embodiments, various functions performed in conjunction with fixed codebook searches are implemented or supported by a computer program that is formed from computer readable program code and that is embodied in a computer readable medium. The phrase “computer readable program code” includes any type of computer code, including source code, object code, and executable code. The phrase “computer readable medium” includes any type of medium capable of being accessed by a computer, such as read only memory (ROM), random access memory (RAM), a hard disk drive, a compact disc (CD), a digital video disc (DVD), or any other type of memory.

It may be advantageous to set forth definitions of certain words and phrases used throughout this patent document. The term “couple” and its derivatives refer to any direct or indirect communication between two or more elements, whether or not those elements are in physical contact with one another. The term “application” refers to one or more computer programs, sets of instructions, procedures, functions, objects, classes, instances, or related data adapted for implementation in a suitable computer language. The terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation. The term “or” is inclusive, meaning and/or. The phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like. The term “controller” means any device, system, or part thereof that controls at least one operation. A controller may be implemented in hardware, firmware, software, or some combination of at least two of the same. The functionality associated with any particular controller may be centralized or distributed, whether locally or remotely.

While this disclosure has described certain embodiments and generally associated methods, alterations and permutations of these embodiments and methods will be apparent to those skilled in the art. For example, the above embodiments refer specifically to two codecs (G.723.1 and G.729A). It will be appreciated that various modifications and improvements can be made by a person skilled in the art without departing from the scope of this disclosure. As a particular example, other codecs having ACELP coding and substantially similar structures to the codecs described above could be used. Accordingly, the above description of example embodiments does not define or constrain this disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of this disclosure, as defined by the following claims.

Claims

1. A method for performing a search of a codebook, the codebook comprising a plurality of tracks each having a plurality of even pulse positions, the method comprising: partitioning a codevector comprising a plurality of pulses into a first subset of pulses and a second subset of pulses, each pulse assignable to a pulse position in the codevector, each pulse associated with a shift bit for indicating an odd position; performing a first search for determining a first set of possible pulse positions for the pulses in the codevector; performing a second search for determining a second set of possible pulse positions for the pulses in the codevector; and forming the codevector using the first and second sets of possible pulse positions.

2. The method of claim 1, further comprising repeating the partitioning, performing, and forming steps to produce a second codevector associated with a second codebook, the second codevector comprising pulses not associated with shift bits, the second codebook comprising tracks having a plurality of odd and even pulse positions.

3. The method of claim 2, further comprising identifying one or more reconfigurable parameters, the one or more reconfigurable parameters associated with a particular one of the codebooks.

4. The method of claim 2, wherein: the codebook comprises a G.723.1 codebook; and the second codebook comprises a G.729A codebook.

5. The method of claim 1, wherein performing the first search comprises: assigning first and second pulses in the first subset and third and fourth pulses in the second subset to third, fourth, first, and second tracks of the codebook, respectively; determining two maximum pulse positions in the third track that are assignable to the first pulse; testing the pulse positions in the fourth track in combination with each of the two maximum pulse positions in the third track to identify one maximum pulse position in the fourth track that is assignable to the second pulse; determining the possible pulse positions for the first and second pulses in the first set of possible pulse positions using search criteria; testing the pulse positions in the second track in combination with each of the pulse positions in the first track to identify pulse positions that are assignable to the third and fourth pulses; and determining the possible pulse positions for the third and fourth pulses in the first set of possible pulse positions using the search criteria.

6. The method of claim 5, wherein performing the first search further comprises: comparing a first correlation signal value for one of the possible pulse positions in the first set of possible pulse positions with a second correlation signal value for that possible pulse position incremented by one; and shifting the possible pulse position and setting a shift bit for the possible pulse position if the second correlation signal value is higher than the first correlation signal value.

7. The method of claim 5, wherein performing the second search comprises: determining two maximum pulse positions in the fourth track that are assignable to the first pulse; testing the pulse positions in the first track in combination with each of the two maximum pulse positions in the fourth track to identify one maximum pulse position in the first track that is assignable to the second pulse; determining the possible pulse positions for the first and second pulses in the second set of possible pulse positions using the search criteria; testing the pulse positions in the third track in combination with each of the pulse positions in the second track to identify pulse positions that are assignable to the third and fourth pulses; and determining the possible pulse positions for the third and fourth pulses in the second set of possible pulse positions using the search criteria.

8. The method of claim 7, wherein performing the second search further comprises: comparing a first correlation signal value for one of the possible pulse positions in the second set of possible pulse positions with a second correlation signal value for that possible pulse position incremented by one; and shifting the possible pulse position and setting a shift bit for the possible pulse position if the second correlation signal value is higher than the first correlation signal value.

9. A system, comprising: a processor capable of performing functions for at least one of encoding and decoding communication signals; and a co-processor capable of performing a search of a codebook to support at least one of the encoding and decoding of the communication signals, the codebook comprising a plurality of tracks each having a plurality of even pulse positions, the co-processor capable of performing the search by: partitioning a codevector comprising a plurality of pulses into a first subset of pulses and a second subset of pulses, each pulse assignable to a pulse position in the codevector, each pulse associated with a shift bit for indicating an odd position; performing a first search for determining a first set of possible pulse positions for the pulses in the codevector; performing a second search for determining a second set of possible pulse positions for the pulses in the codevector; and forming the codevector using the first and second sets of possible pulse positions.

10. The system of claim 9, wherein the co-processor is further capable of repeating the partitioning, performing, and forming to produce a second codevector associated with a second codebook, the second codevector comprising pulses not associated with shift bits, the second codebook comprising tracks having a plurality of odd and even pulse positions, the codebooks associated with different codecs.

11. The system of claim 10, wherein the processor is capable of setting a codec flag to identify one of the codecs, the co-processor capable of using the codec flag to generate one of the codevectors.

12. The system of claim 11, wherein one or more reconfigurable parameters are configured by the co-processor according to the codec flag.

13. The system of claim 9, wherein the co-processor is capable of performing the first search by: assigning first and second pulses in the first subset and third and fourth pulses in the second subset to third, fourth, first, and second tracks of the codebook, respectively; determining two maximum pulse positions in the third track that are assignable to the first pulse; testing the pulse positions in the fourth track in combination with each of the two maximum pulse positions in the third track to identify one maximum pulse position in the fourth track that is assignable to the second pulse; determining the possible pulse positions for the first and second pulses in the first set of possible pulse positions using search criteria; testing the pulse positions in the second track in combination with each of the pulse positions in the first track to identify pulse positions that are assignable to the third and fourth pulses; and determining the possible pulse positions for the third and fourth pulses in the first set of possible pulse positions using the search criteria.

14. The system of claim 13, wherein the co-processor is capable of performing the first search further by: comparing a first correlation signal value for one of the possible pulse positions in the first set of possible pulse positions with a second correlation signal value for that possible pulse position incremented by one; and shifting the possible pulse position and setting a shift bit for the possible pulse position if the second correlation signal value is higher than the first correlation signal value.

15. The system of claim 13, wherein the co-processor is capable of performing the second search by: determining two maximum pulse positions in the fourth track that are assignable to the first pulse; testing the pulse positions in the first track in combination with each of the two maximum pulse positions in the fourth track to identify one maximum pulse position in the first track that is assignable to the second pulse; determining the possible pulse positions for the first and second pulses in the second set of possible pulse positions using the search criteria; testing the pulse positions in the third track in combination with each of the pulse positions in the second track to identify pulse positions that are assignable to the third and fourth pulses; and determining the possible pulse positions for the third and fourth pulses in the second set of possible pulse positions using the search criteria.

16. The system of claim 15, wherein the co-processor is capable of performing the second search further by: comparing a first correlation signal value for one of the possible pulse positions in the second set of possible pulse positions with a second correlation signal value for that possible pulse position incremented by one; and shifting the possible pulse position and setting a shift bit for the possible pulse position if the second correlation signal value is higher than the first correlation signal value.

17. The system of claim 9, wherein the co-processor is further capable of implementing a pitch estimator, a Formant Perceptual Weighting filter, and a Harmonic Noise Shaping module.

18. The system of claim 9, wherein the processor comprises a digital signal processor.

19. A computer program embodied on a computer readable medium and operable to be executed by a processor, the computer program for performing a search of a codebook, the codebook comprising a plurality of tracks each having a plurality of even pulse positions, the computer program comprising computer readable program code for: partitioning a codevector comprising a plurality of pulses into a first subset of pulses and a second subset of pulses, each pulse assignable to a pulse position in the codevector, each pulse associated with a shift bit for indicating an odd position; performing a first search for determining a first set of possible pulse positions for the pulses in the codevector; performing a second search for determining a second set of possible pulse positions for the pulses in the codevector; and forming the codevector using the first and second sets of possible pulse positions.

20. The computer program of claim 19, further comprising computer readable program code for repeating the partitioning, performing, and forming steps to produce a second codevector associated with a second codebook, the second codevector comprising pulses not associated with shift bits, the second codebook comprising tracks having a plurality of odd and even pulse positions.