The present technology is in the field of computer system design and, more specifically, related to protocol conversion for a network-on-chip interconnect used in a system-on-chip (SoC).
Networks-on-chip (NoC) are interconnects that are used to connect IP blocks that exist in a system-on-chip (SoC). The process of creating packet-based interconnects for SoC, which need to communicate with many IP blocks and hardware components, use interfaces with different communication protocols. The protocols used by the IP blocks and hardware components are typically different from the protocol used by the interconnect. The protocol converters are part of the overall design process. The known processes of designing and setting conversion from one protocol to another is an inefficient process.
Thus, there is a challenge of accurately and efficiently connecting an external hardware element or IP block, which uses a particular physical interface (made of a set of pins) and a communication protocol, to the NoC interconnect thereby allowing for exchange of requests and responses with other IP blocks and components of the SoC. The challenge also includes the difference between the IP block communication protocol and conversion to a packet-based NoC interconnect that uses a different communication protocol internally.
When connecting multiple IP blocks, due to distance between IP blocks. limited range of IP block to drive a signal, and signal routing congestion (e.g., not enough physical space to route every signal of each block), it can be advantageous to connect the IP blocks with a NoC. A challenge the system designer faces is to create a protocol converter block to go between the IP block and the protocol used internally in the NoC, and connecting all these components. The challenge is made even more complex when the system designer has to manage the different interfaces implemented by each IP block. A system designer must manually mange each IP blocks protocol, the NoC internal protocol, the pins for the IP block and the NoC, and the connections both between the IP blocks and NoC and the internal NoC connections. This manually management is both time consuming and error prone which increases the cost of a NoC and the risk of an SoC not performing as expected due to a design error.
Therefore, what is needed is a system and method that increases the efficiency and automates the process of generating protocol converters using machine-readable descriptions of the external hardware components interfaces and the associated protocol.
In accordance with the various aspects and embodiment of the invention, a system and method are disclosed that automate the process of generating protocol converters using machine-readable descriptions of the external hardware components interfaces and the associated protocol. One advantage of the invention is lowered mistakes in generating the protocol converters. Another advantage is increased productivity when designing the interconnect, such as a network-on-chip (NoC) and assembling the system-on-chip (SoC).
In order to understand the invention more fully, reference is made to the accompanying drawings. The invention is described in accordance with the aspects and embodiments in the following description with reference to the drawings or figures (FIG.), in which like numbers represent the same or similar elements. Understanding that these drawings are not to be considered limitations in the scope of the invention, the presently described aspects and embodiments and the presently understood best mode of the invention are described with additional detail through use of the accompanying drawings.
The following describes various examples of the present technology that illustrate various aspects and embodiments of the invention. Generally, examples can use the described aspects in any combination. All statements herein reciting principles, aspects, and embodiments as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. The examples provided are intended as non-limiting examples. Additionally, it is intended that such equivalents include both currently known equivalents and equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.
It is noted that, as used herein, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise. Reference throughout this specification to “one embodiment,” “an embodiment,” “certain embodiment,” “various embodiments,” or similar language means that a particular aspect, feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention.
Thus, appearances of the phrases “in one embodiment,” “in at least one embodiment,” “in an embodiment,” “in certain embodiments,” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment or similar embodiments. Furthermore, aspects and embodiments of the invention described herein are merely exemplary, and should not be construed as limiting of the scope or spirit of the invention as appreciated by those of ordinary skill in the art. The disclosed invention is effectively made or used in any embodiment that includes any novel aspect described herein. All statements herein reciting principles, aspects, and embodiments of the invention are intended to encompass both structural and functional equivalents thereof. It is intended that such equivalents include both currently known equivalents and equivalents developed in the future. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a similar manner to the term “comprising.”
The terms “source,” “master,” and “initiator” refer to hardware intellectual property (IP) modules/blocks or units; these terms are used interchangeably within the scope and embodiments of the invention. As used herein, the terms “sink,” “slave,” and “target” refer to hardware IP modules or units and the terms are used interchangeably within the scope and embodiments of the invention. As used herein, a transaction may be a request transaction or a response transaction. Examples of request transactions include write request and read request.
Various references are made herein to integrated circuits (ICs) and the designs of ICs. One example of an IC is a multiprocessor system that is implemented in systems-on-chip (SoCs) that communicates through networks-on-chip (NoC), which is an interconnect. The SoCs include instances of initiator intellectual properties (IPs) and target IPs. The IP elements or blocks includes pins that have names and connect to the NoC's pins. The NoC pins also have names. Transactions are sent from an initiator to one or more targets using industry-standard protocols. The initiator, which is connected to the NoC, sends a request transaction to a target or targets, using a protocol. The transaction includes an address that identifies or selects the target or targets. The protocol used by one IP can vary from the protocol used by another IP; both can be different from the protocol used by the NoC or interconnect. The NoC includes network interface units (NIU) that act as protocol converters, which are at the boundary of the NoC and convert (decode) from a protocol (of an external device connected to the pins of the NoC) to the internal protocol of the NoC in accordance with various embodiments and aspects of the invention. The NoC decodes the address at the boundary (where the NIUs are located) and transports the request through the NoC to another NIU located at the boundary of the NoC, which other NIU is in communication with the target (destination). The transaction is converted from the NoC's protocol to the target's protocol at the NIU or the boundary of the NoC. The target receives and handles the transaction. The target then sends a response transaction, which is transported back by the NoC to the initiator. As such, the SoC and NoC include complexity and configurability, especially in situation when the NoC is configurable.
Referring now to
Referring now to
Referring specifically to
In accordance with the various aspects and embodiments of the invention, the process produces other collaterals to help with the ASIC implementation flow, such as, for instance: synthesis scripts, integration-oriented XML files, gates, and power estimates and so on. In accordance with some aspects and embodiments of the invention, the protocol converter is integrated in a network interface unit (NIU) of the packet-based interconnect. The NIU and enables communication with the external hardware element, which uses a different protocol. In accordance with some aspects and embodiments of the invention, the protocol converter uses the same pins and the same pin names as the ones used by the IP block or the external hardware element. Thus, connection of pins of the external hardware element to the pins of the protocol converter is straightforward because pins with identical names connect to each other.
Based on the process being implement in accordance with the various aspects of the invention, protocol converts are automatically, efficiently, and accurately created for packet-based NoC interconnects. The protocol converters include interfaces that have pins with names that exactly match the pin name of the external hardware elements or IP blocks, to which the pins connect. In accordance with various embodiments and aspects of the invention, a NoC description, which includes the protocol converter description, is generated using a synthesis tool during the design process.
Referring now to
At step 320, an output interconnect protocol is received. According to one or more aspects and embodiments of the invention, the output interconnect protocol may be read from a computer file. According to one or more aspects and embodiments of the invention, a computer file describes an interface along with the pins and the associated output interconnect protocol. According to one or more aspects and embodiments of the invention, the output interconnect protocol may be specified as a standard interface type (e.g., Advanced eXtensible Interface (AMBA-AXI)). According to one or more aspects and embodiments of the invention, the output interconnect protocol may be specified by a behavioral description of the interface.
At step 330, a protocol interface module or model is created using the input protocol and the output interconnect protocol. According to one or more aspects and embodiments of the invention, the protocol interface model is read from a computer file.
At step 340, a protocol converter block is created using the protocol interface model. According to one or more aspects and embodiments of the invention, the protocol converter block has an interface to handle bi-directional traffic flow, using input interfaces and output interfaces. The input interface of the protocol converter block implements the input protocol and the output interface implements the output interconnect protocol. According to one or more aspects and embodiments of the invention, the protocol converter converts in a bi-directional manner between input protocol and the output interconnect protocol. According to one or more aspects and embodiments of the invention, the protocol converter block translates requests and responses between the input protocol and the output interconnect protocol. According to one or more aspects and embodiments of the invention, the input protocol is packet-based. According to one or more aspects and embodiments of the invention, the output interconnect protocol is packet-based. According to one or more aspects and embodiments of the invention, creating the protocol converter block may be done locally, remotely (e.g., remote server), and any combination of the preceding.
According to one or more aspects and embodiments of the invention, the protocol converter block is created in a hardware format (e.g., HDL, Verilog, netlist, etc.). According to one or more aspects and embodiments of the invention, the protocol converter block is created in a high-level description (e.g., SystemVerilog, System-C, etc.).
According to one or more aspects and embodiments of the invention, one or more of the input protocols, output interconnect protocol, and protocol interface model may be contained within one or more computer files. According to one or more aspects and embodiments of the invention, one or more of the input protocols, output interconnect protocol, and protocol interface model may be contained within a database. According to one or more aspects and embodiments of the invention, one or more of the input protocols, output interconnect protocol, and protocol interface model may be contained within any computer readable format capable of storing protocols and/or models. According to one or more aspects and embodiments of the invention, one or more of the input protocols, output interconnect protocol, and protocol interface model may be stored locally, remotely, or a combination of locally and remotely.
Referring now to
At step 404, IP slave block and IP slave protocol is received. According to one or more aspects and embodiments of the invention, the IP slave block protocol may be read from a computer file. According to one or more aspects and embodiments of the invention, IP master block protocol and IP slave block protocol are read from the same computer file. According to one or more aspects and embodiments of the invention, IP slave block protocol may be the same or similar to the input protocol of step 310.
At step 406, interconnect protocol is received. According to one or more aspects and embodiments of the invention, the interconnect protocol may be read from a computer file. According to one or more aspects and embodiments of the invention, one or more of the IP master block protocol, IP slave protocol is received, and interconnect protocol is read from one or more computer files. According to one or more aspects and embodiments of the invention, interconnect protocol may be the same or similar to the output interconnect protocol of step 320.
At step 408, a master protocol interface model is created using the IP master block protocol and the interconnect protocol. According to one or more aspects and embodiments of the invention, creating master protocol interface model may be the same or similar to creating the protocol interface of step 330. At step 410, a slave protocol interface model using IP slave block protocol and interconnect protocol is created. According to one or more aspects and embodiments of the invention, creating slave protocol interface model may be the same or similar to creating the protocol interface of step 330.
At step 412, a master interface protocol converter block is created using the master protocol interface model and a slave interface protocol converter block is created using the slave protocol interface model. According to one or more aspects and embodiments of the invention, the master interface protocol converter block and/or slave interface protocol converter block is created in a hardware format (e.g., HDL, Verilog, netlist, etc.). According to one or more aspects and embodiments of the invention, the master interface protocol converter block and/or slave interface protocol converter block is created in a high-level description (e.g., SystemVerilog, System-C, etc.). According to one or more aspects and embodiments of the invention, creating the master interface protocol converter block is the same or similar as creating the protocol converter block of step 340. According to one or more aspects and embodiments of the invention, creating the slave interface protocol converter block is the same or similar as creating the protocol converter block of step 340. According to one or more aspects and embodiments of the invention, the master interface protocol converter block pins are given the same respective name as the IP master block pins. A potential benefit of having the same pin names between the master interface protocol converter block pins and the IP master blocks pins is to aid in the connection of the master interface protocol convert block and the IP master block. For example, if a human is connecting the blocks, the person would know to connect the same pin names. For another example, automated software can be used to connect the same pin names.
According to one or more aspects and embodiments of the invention, the slave interface protocol converter block pins are given the same respective name as the IP slave block pins. A potential benefit of having the same pin names between the slave interface protocol converter block pins and the IP slave blocks pins is to aid in the connection of the slave interface protocol convert block and the IP slave block. For example, if a human is connecting the blocks, the person would know to connect the same pin names. For another example, automated software can be used to connect the same pin names. According to one or more aspects and embodiments of the invention, a lookup table may be used to map between a protocol and the pin names.
At step 414, a packet-based interconnect block is created that include the master interface protocol converter block, the slave interface protocol converter block, and connection between the master interface protocol converter block and the slave interface protocol converter block.
At step 416, the IP master block is connected to the packet-based interconnect block via master interface protocol converter block. At step 418, the IP slave block is connected to the packet-based interconnect block via slave interface protocol converter block.
According to one or more aspects and embodiments of the invention, packet-based interconnect block enables the IP master block to communicate with the IP slave block. The IP master block communicates with the master interface protocol converter block using the IP master block protocol. The IP slave block communicates with the slave interface protocol converter block using the IP slave block protocol. The IP master block converter converts the IP master block protocol into an interconnect protocol. The packet-based interconnect block routes the interconnect protocol to the IP slave block converter. The IP slave block converter converts the interconnect protocol to the IP slave protocol and then communicates with the IP slave block using the IP slave protocol.
According to one or more aspects and embodiments of the invention, though it is taught that a master and slave communicate via the packet-based interconnect block, any number of IP blocks may communicate using the packet-based interconnect block. For example, a central processor unit (CPU), a memory array, and a hard driver interface controller may communicate between using the packet-based interconnect block.
According to one or more aspects and embodiments of the invention, interfaces to IP blocks includes the packet-based interconnect, any number of connections (e.g., wires), and components (e.g., switches, buffers, queues, etc.).
According to one or more aspects and embodiments of the invention, the IP master block and/or the IP slave block may have a non-packet-based interface (e.g., serial interface, parallel interface, etc.), and the packet-based interconnect black has an internal packet-based interface (e.g., interconnect protocol). For example, IP master block protocol and/or IP slave block protocol may have a non-packet-based interface, and the interconnect protocol is packet based.
Referring now to
Protocol converter block generator 520 creates one or more converter blocks with the one or more protocols from receiver 510. According to one or more aspects and embodiments of the invention, protocol converter block generator 520 may perform the same or similar to steps 330 and 340 of
Certain methods according to the various aspects of the invention may be performed by instructions that are stored upon a non-transitory computer readable medium, for example a module. The non-transitory computer readable medium stores code including instructions that, if executed by one or more processors, would cause a system or computer to perform steps of the method described herein, including methods performed by a module, such as the modules described herein. The non-transitory computer readable medium includes: a rotating magnetic disk, a rotating optical disk, a flash random access memory (RAM) chip, and other mechanically moving or solid-state storage media.
Any type of computer-readable medium is appropriate for storing code comprising instructions according to various example. Some examples are one or more non-transitory computer readable media arranged to store such instructions for methods described herein. Additionally, modules may be represented by codes stored in non-transitory media or represented by hardware components that performs a specific function. Whatever machine holds non-transitory computer readable media comprising any of the necessary code may implement an example. Some examples may be implemented as: physical devices such as semiconductor chips; hardware description language representations of the logical or functional behavior of such devices; and one or more non-transitory computer readable media arranged to store such hardware description language representations.
Descriptions herein reciting principles, aspects, and embodiments encompass both structural and functional equivalents thereof. Elements described herein as coupled have an effectual relationship realizable by a direct connection or indirectly with one or more other intervening elements.
Certain examples have been described herein and it will be noted that different combinations of different components from different examples may be possible. Salient features are presented to better explain examples; however, it is clear that certain features may be added, modified and/or omitted without modifying the functional aspects of these examples as described.
Various examples are methods that use the behavior of either or a combination of machines. Method examples are complete wherever in the world most constituent steps occur. For example, and in accordance with the various aspects and embodiments of the invention, IP elements or units include: processors (e.g., CPUs or GPUs), random-access memory (RAM—e.g., off-chip dynamic RAM or DRAM), a network interface for wired or wireless connections such as ethernet, Wi-Fi, 3G, 4G long-term evolution (LTE), 5G, and other wireless interface standard radios. The IP block or element may also include various I/O interface devices, as needed for different peripheral devices such as touch screen sensors, geolocation receivers, microphones, speakers, Bluetooth peripherals, and USB devices, such as keyboards and mice, among others. By executing instructions stored in RAM devices processors perform steps of methods as described herein.
Practitioners skilled in the art will recognize many modifications and variations. The modifications and variations include any relevant combination of the disclosed features. Descriptions herein reciting principles, aspects, and embodiments encompass both structural and functional equivalents thereof. Elements described herein as “coupled” or “communicatively coupled” have an effectual relationship realizable by a direct connection or indirect connection, which uses one or more other intervening elements. Embodiments described herein as “communicating” or “in communication with” another device, module, or elements include any form of communication or link and include an effectual relationship. For example, a communication link may be established using a wired connection, wireless protocols, near-field protocols, or RFID.
The scope of the invention, therefore, is not intended to be limited to the exemplary embodiments shown and described herein. Rather, the scope and spirit of present invention is embodied by the appended claims.
This application claims priority to U.S. Provisional Application Ser. No. 63/149,184 filed on Feb. 12, 2021 and titled PACKET BASED INTERCONNECT IN A SYSTEM-ON-CHIP (SoC) by K. Charles JANAC, et. al, the entire disclosure of which is incorporated herein by reference.
Number | Name | Date | Kind |
---|---|---|---|
5485396 | Brasen et al. | Jan 1996 | A |
5541849 | Rostoker et al. | Jul 1996 | A |
5623420 | Yee et al. | Apr 1997 | A |
5638288 | Deeley | Jun 1997 | A |
5761078 | Fuller et al. | Jun 1998 | A |
5887670 | Tabata et al. | Mar 1999 | A |
5903886 | Heimlich et al. | May 1999 | A |
5983277 | Heile et al. | Nov 1999 | A |
6002857 | Ramachandran | Dec 1999 | A |
6134705 | Pedersen et al. | Oct 2000 | A |
6145117 | Eng | Nov 2000 | A |
6249902 | Igusa et al. | Jun 2001 | B1 |
6321363 | Huang et al. | Nov 2001 | B1 |
6360356 | Eng | Mar 2002 | B1 |
6378121 | Hiraga | Apr 2002 | B2 |
6421321 | Sakagawa et al. | Jul 2002 | B1 |
6437804 | Ibe et al. | Aug 2002 | B1 |
6449761 | Greidinger et al. | Sep 2002 | B1 |
6622225 | Kessler et al. | Sep 2003 | B1 |
6883455 | Maeda et al. | Apr 2005 | B2 |
6907591 | Teig et al. | Jun 2005 | B1 |
7096436 | Bednar et al. | Aug 2006 | B2 |
7398497 | Sato et al. | Jul 2008 | B2 |
7587687 | Watanabe et al. | Sep 2009 | B2 |
7788625 | Donlin et al. | Aug 2010 | B1 |
8020168 | Hoover | Sep 2011 | B2 |
8042087 | Murali et al. | Oct 2011 | B2 |
8302041 | Chan et al. | Oct 2012 | B1 |
8423715 | Heil | Apr 2013 | B2 |
8819611 | Philip et al. | Aug 2014 | B2 |
9184998 | Xue | Nov 2015 | B2 |
9262359 | Noice et al. | Feb 2016 | B1 |
9444702 | Raponi et al. | Sep 2016 | B1 |
9569574 | Khan et al. | Feb 2017 | B1 |
9792397 | Nagaraja | Oct 2017 | B1 |
9825779 | Ruymbeke et al. | Nov 2017 | B2 |
9940423 | Lescure | Apr 2018 | B2 |
10068047 | Finn | Sep 2018 | B1 |
10282502 | BShara et al. | May 2019 | B1 |
10348563 | Rao et al. | Jul 2019 | B2 |
10460062 | Feld et al. | Oct 2019 | B2 |
10733350 | Prasad et al. | Aug 2020 | B1 |
10853545 | Nardi et al. | Dec 2020 | B1 |
10922471 | Baeckler et al. | Feb 2021 | B2 |
10990724 | Cherif et al. | Apr 2021 | B1 |
11121933 | Cherif et al. | Sep 2021 | B2 |
11281827 | Labib et al. | Mar 2022 | B1 |
11449655 | Cherif et al. | Sep 2022 | B2 |
20030093765 | Lam et al. | May 2003 | A1 |
20040040007 | Harn | Feb 2004 | A1 |
20040230919 | Balasubramanian et al. | Nov 2004 | A1 |
20050073316 | Graham | Apr 2005 | A1 |
20050268258 | Decker | Dec 2005 | A1 |
20070156378 | McNamara | Jul 2007 | A1 |
20070157131 | Watanabe et al. | Jul 2007 | A1 |
20070174795 | Lavagno et al. | Jul 2007 | A1 |
20070186018 | Radulescu et al. | Aug 2007 | A1 |
20080046854 | Tang | Feb 2008 | A1 |
20080049753 | Heinze et al. | Feb 2008 | A1 |
20080279183 | Wiley et al. | Nov 2008 | A1 |
20080291826 | Licardie et al. | Nov 2008 | A1 |
20090031277 | Mcelvain et al. | Jan 2009 | A1 |
20090313592 | Murali et al. | Dec 2009 | A1 |
20100061352 | Fasolo et al. | Mar 2010 | A1 |
20100162189 | Lavagno et al. | Jun 2010 | A1 |
20100218146 | Platzker et al. | Aug 2010 | A1 |
20100274785 | Procopiuc et al. | Oct 2010 | A1 |
20110170406 | Krishnaswamy | Jul 2011 | A1 |
20120013509 | Wisherd et al. | Jan 2012 | A1 |
20120311512 | Michel et al. | Dec 2012 | A1 |
20130174113 | Lecler et al. | Jul 2013 | A1 |
20130208598 | Nakaya et al. | Aug 2013 | A1 |
20130258847 | Zhang et al. | Oct 2013 | A1 |
20130283226 | Ho et al. | Oct 2013 | A1 |
20140115218 | Philip et al. | Apr 2014 | A1 |
20140126572 | Hutton et al. | May 2014 | A1 |
20140153575 | Munoz | Jun 2014 | A1 |
20140156826 | Chang et al. | Jun 2014 | A1 |
20140160939 | Arad et al. | Jun 2014 | A1 |
20140169173 | Naouri et al. | Jun 2014 | A1 |
20140204735 | Kumar et al. | Jul 2014 | A1 |
20140211622 | Kumar et al. | Jul 2014 | A1 |
20140298281 | Varadarajan et al. | Oct 2014 | A1 |
20140321839 | Armstrong | Oct 2014 | A1 |
20150036536 | Kumar et al. | Feb 2015 | A1 |
20150106778 | Mangano et al. | Apr 2015 | A1 |
20150121319 | Hutton et al. | Apr 2015 | A1 |
20150178435 | Kumar | Jun 2015 | A1 |
20150254325 | Stringham | Sep 2015 | A1 |
20150341224 | Van et al. | Nov 2015 | A1 |
20150347641 | Gristede et al. | Dec 2015 | A1 |
20160103943 | Xia et al. | Apr 2016 | A1 |
20160275213 | Tomita | Sep 2016 | A1 |
20160321390 | Bozman et al. | Nov 2016 | A1 |
20170060204 | Gangwar et al. | Mar 2017 | A1 |
20170063734 | Kumar | Mar 2017 | A1 |
20170132350 | Janac | May 2017 | A1 |
20170177778 | Lescure | Jun 2017 | A1 |
20170193136 | Prasad et al. | Jul 2017 | A1 |
20180115487 | Thubert et al. | Apr 2018 | A1 |
20180144071 | Yu et al. | May 2018 | A1 |
20180227180 | Rao et al. | Aug 2018 | A1 |
20190012909 | Mintz | Jan 2019 | A1 |
20190073440 | Farbiz et al. | Mar 2019 | A1 |
20190179992 | Giaconi | Jun 2019 | A1 |
20190205493 | Garibay et al. | Jul 2019 | A1 |
20190246989 | Genov et al. | Aug 2019 | A1 |
20190251227 | Fink | Aug 2019 | A1 |
20190260504 | Philip et al. | Aug 2019 | A1 |
20190363789 | Lee et al. | Nov 2019 | A1 |
20200092230 | Schultz et al. | Mar 2020 | A1 |
20200162335 | Chen et al. | May 2020 | A1 |
20200234582 | Mintz | Jul 2020 | A1 |
20200366607 | Kommula et al. | Nov 2020 | A1 |
20210203557 | Cherif et al. | Jul 2021 | A1 |
20210226887 | Mereddy | Jul 2021 | A1 |
20210320869 | Bourai et al. | Oct 2021 | A1 |
20210409284 | Cherif et al. | Dec 2021 | A1 |
20220294704 | Lescure et al. | Sep 2022 | A1 |
Number | Date | Country |
---|---|---|
105187313 | May 2018 | CN |
109587081 | Apr 2019 | CN |
113051215 | Jun 2021 | CN |
113055219 | Jun 2021 | CN |
102015014851 | May 2016 | DE |
3842987 | Jun 2021 | EP |
4024262 | Jul 2022 | EP |
4057179 | Sep 2022 | EP |
Entry |
---|
Anonymous: “Network on a chip—Wikipedia”, Jun. 15, 2021, https://en.wikipedia. org/w/index.php?title-Network_on_a_chip&oldid-1028654828. |
Haytham Elmiligi et al: “Networks-on-chip topology optimization subject to power, delay, and reliability constraints”, IEEE International Symposium on Circuits and Systems, May 30, 2010, pp. 2354-2357 DOI: 10.1109/ISCAS 2010.5537194. |
Jain R. et al: “Predicting system-level area and delay for pipelined and nonpipelined designs”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 11, No. 8, Jan. 1, 1992, pp. 955-965, DOI: 10.1109/43.149767. |
Jingye Xu et al: “Latch Based Interconnect Pipelining For High Speed Integrated Circuits”, Proceedings of the International Conference on Electro/Information Technology, May 1, 2006, pp. 295-300 DOI: 10.1109/EIT.2006.252152. |
Jun Minje et al: “Exploiting Implementation Diversity and Partial Connection of Routers in Application-Specific Network-on-Chip Topology Synthesis”, IEEE Transactions on Computers, IEEE, USA, vol. 63, No. 6, Jun. 1, 2014 (Jun. 1, 2014), pp. 1434-1445, XP011550397, ISSN: 0018-9340, DOI: 10.1109/TC.2012.294. |
Saponara S et al: “Design and coverage-driven verification of a novel network-interface IP macrocell for network-on-chip interconnects”, Microprocessors and Microsystems, vol. 35, No. 6 , pp. 579-592, XP028255708 ISSN: 0141-9331, DOI: 10.1016/J.MICPRO, 2011.06.005. |
Saponara Sergio et al: “Configurable network-on-chip router macrocells”, Microprocessors and Microsystems, IPC Business Press Ltd. London, GB, vol. 45, Apr. 29, 2016 (Apr. 29, 2016), pp. 141-150 XP029678799, ISSN: 0141-9331, DOI: 10.1016/J.MICPRO.2016.04.008. |
Song Z et al: “A NoC-Based High Performance Deadlock Avoidance Routing Algorithm”, Computer and Computational Sciences, 2008. IMSCCS '08, International Multisymposiums On, IEEE Piscataway, NJ, USA, Oct. 18, 2008, pp. 140-143, XP031411025, ISBN: 978-0-7695-3430-5. |
Anonymous: “Intel Hyperflex Architecture HighPerformance Design Handbook”, Oct. 4, 2021 (Oct. 4, 2021), pp. 1-147, XP093063924, Retrieved from the Internet: URL:https://cdrdv2.intel.com/vl/dl/getContent/667078?fileName=sl0_hp_hb-683353-667078.pdf. |
Ken Eguro et al: “Simultaneous Retiming and Placement for Pipelined Net lists”, Proceedings of the 16th International Symposium on Field-Programmable Custom Computing Machines, Apr. 14, 2008 (Apr. 14, 2008), pp. 139-148, XP031379339. |
Chaari Moomen Moomen Chaari@Infineon Com et al: “A model-based and simulation-assisted FMEDA approach for safety-relevant E/E systems”, Proceedings of the 34th ACM SIGMOD-SIGACT-SIGAI Symposium on Principles of Database Systems, ACMPUB27, New York, NY, USA, Jun. 7, 2015 (Jun. 7, 2015), pp. 1-6, XP058511366, DOI: 10.1145/2744769.2747908 ISBN: 978-1-4503-3550-8. |
Mariani R et al: “Fault-Robust Microcontrollers for Automotive Applications”, On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International Como, Italy Jul. 10-12, 2006, Piscataway, NJ, USA, IEEE, Jul. 10, 2006 (Jul. 10, 2006), pp. 213-218, XP010928275, DOI: 10.1109/IOLTS.2006.38 ISBN: 978-0-7695-2620-1. |
Dumitriu Vet Al: “Throughput-Oriented Noc Topology Generation and Analysis for High Performance SoCs”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Service Center, Piscataway, NJ, USA, vol. 17, No. 10, Oct. 1, 2009 (Oct. 1, 2009), pp. 1433-1446, XP011267808, ISSN: 1063-8210, DOI: 10.1109/TVLSI.2008.2004592. |
Fangfa Fu et al: “A Noc performance evaluation platform supporting designs at multiple levels of abstraction”, Industrial Electronics and Applications, 2009. ICIEA 2009. 4TH IEEE Conference on, IEEE, Piscataway, NJ, USA, May 25, 2009 (May 25, 2009), pp. 425-429, XP031482069, ISBN: 978-1-4244-2799-4 *abstract* * p. 426-p. 429 *. |
Murali et al: “Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Service Center, Piscataway, NJ, USA, vol. 15, No. 8, Aug. 1, 2007 (Aug. 1, 2007) , pp. 869-880, XP011187732, ISSN: 1063-8210, DOI: 10.1109/TVLSI.2007.900742. |
Picornell Tomas tompic@gap.upv.es et al: “DCFNoC A Delayed Conflict-Free Time Division Multiplexing Network on Chip”, Designing Interactive Systems Conference, ACM, 2 Penn Plaza, Suite 701 New York NY10121-0701 USA, Jun. 2, 2019 (Jun. 2, 2019), pp. 1-6, XP058637807, DOI: 10.1145/3316781.3317794 ISBN: 978-1-4503-5850-7. |
Francesco Robino: “A model-based design approach for heterogeneous NoC-based MPSoCs on FPGA”, Jul. 1, 2014 (Jul. 1, 2014), XP002806918, Retrieved from the Internet: URL: http://www.divaportal.org/smash/get/diva2:718518/FULLTEXT02.pdf [retrieved on Jun. 22, 2022]. |
James C. Tiernan. 1970. An efficient search algorithm to find the elementary circuits of a graph. Commun. ACM 13, 12 (Dec. 1970), 722-726. https://doi.org/10.1145/362814.362819. |
U.S. Appl. No. 17/134,384, filed Dec. 26, 2020, Federico Angiolini. |
U.S. Appl. No. 17/665,578, filed Feb. 6, 2022, K. Charles Janac. |
“A distributed interleaving scheme for efficient access to wideIO dram memory”, Seiculescu Ciprian, Benini Luca, De Micheli Giovanni, CODES+ISSS'12 (Year: 2012). |
“Thread-Fair Memory Request Reordering”; Kun Fang, Nick Iliev, Ehsan Noohi, Suyu Zhang, and Zhichun Zhu; Dept. of ECE, Univeristy of Illinois at Chicago; JWAC-3 Jun. 9, 2012. |
19th Asia and South Pacific Design Automation Conterence Alberto Ghiribaldi, Herve Tatenguem Fankem, Federico Angiolini, Mikkel Stensgaard, Tobias Bjerregaard, Davide Bertozzi A Vertically Integrated and Interoperable Multi-Vendor Synthesis Flow for Predictable NoC Design in Nanoscale Technologies. |
ACM ICCAD '06 Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo Designing Application-Specific Networks on Chips with Floorplan Information p. 8, Figure 8. |
Alessandro Pinto et al, “System level design paradigms”, ACM Transactions on Design Automation of Electronic Systems, ACM, New York, NY, US, (Jun. 7, 2004), vol. 11, No. 3, doi:10.1145/1142980.1142982, ISSN 1084-4309, pp. 537-563, XP058222500. |
Annual IEEE International SoC Conference Proceedings Mohammad reza Kakoee, Federico Angiolin, Srinivasan Murali, Antonio Pullini, Ciprian Seiculescu, and Luca Benini A Floorplan-aware Interactive Tool Flow for NoC Design and Synthesis pp. 1, 2, 4 2009 Belfast, Northern Ireland, UK. |
Bo Huang et al, “Application-Specific Network-on-Chip synthesis with topology-aware floorplanning”, Integrated Circuits and Systems Design (SBCCI), 2012 25th Symposium On, IEEE, (Aug. 30, 2012), doi:10.1109/SBCCI.2012.6344421, ISBN 978-1-4673-2606-3, pp. 1-6, XP032471227. |
David Atienza et al, Network-on-Chip Design and Synthesis Outlook, Science Direct, Integration the VLSI, journal 41 (2008) 340-359. |
Jean-Jacques Lecler et al: Application driven network-on-chip architecture exploration & refinement for a complex SoC, Design Automation for Embedded Systems, vol. 15 No. 2, Apr. 7, 2011, DOI: 10.1007/S10617-011-9075-5. |
K. R. Manik et al., “Methodology for Design of Optimum NOC Based on I PG,” 2017 Int'l Conference on Algorithms, Methodology, Model and Applications in Emerging Technologies (ICAMMAET), Chennai, India, IEEE, 6 pages. (Year: 2017). |
Luca Benini: “Application specific Noc design”, Design, Automation and Test in Europe, 2006, Date '06 : Mar. 6-10, 2006, [Munich, Germany; Proceedings] / [Sponsored By the European Design and Automation Association], IEEE, Piscataway, NJ, USA, Mar. 6, 2006 (Mar. 6, 2006), pp. 491-495, XP058393584, ISBN: 9783981080100. |
Partha et al., Design, Synthesis, and Test of Networks on Chips, IEEE (Year: 2005). |
Srinivasan K et al, “Linear programming based techniques for synthesis of network-on-chip architectures”, Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Pr Oceedings. IEEE International Conference on San Jose, CA, USA Oct. 11-13, 2004, Piscataway, NJ, USA, IEEE, (Oct. 11, 2004), doi: 10.1109/ICCD.2004.1347957, ISBN 978-0-7695-2231-9, pp. 422-429, XP010736641. |
Srinivasan Murali et al: “Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees”, Proceedings of the 2005 Asia and South Pacific Design Automation Conference, Jan. 18, 2005, DOI: 10.1145/1120725.1120737. |
Tobias Bjerregaard et al: “A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip”, Proceedings of the IEEE Conference and Exhibition on Design, Automation, and Test in Europe, Mar. 7, 2005, DOI: 10.1109/DATE.2005.36. |
Wei Zhong et al: “Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips”, IEICE Transactions on Fundamentals of Electronics< Communications and Computer Sciences, Jun. 1, 2013, DOI: 10.1587/TRANSFUN.E96.A.1174. |
Zhou Rongrong et al: A Network Components Insertion Method for 3D Application-Specific Network-on-Chip, Proceedings of the 11th IEEE International Conference on Asic, Nov. 3, 2015, pp. 1-4, DOI: 10.1109/ASICON.2015.7516952. |
Number | Date | Country | |
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20220263925 A1 | Aug 2022 | US |
Number | Date | Country | |
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63149184 | Feb 2021 | US |