System and method for synthesis reuse

Abstract

A method of synthesis of multiple implementations of a design is provided comprising: translating a model of the design to a first output model compliant with first constraints; and translating the model of the design to a second output model compliant with second constraints.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1B are illustrative drawings of a prior design system and process in which each of two different behavioral models, representing different implementations of the same functionality, are modified to incorporate changed requirements or to fix design flaws.

FIGS. 2A-2B are illustrative drawings representing a novel synthesis system and method in accordance with an embodiment of the invention.

FIG. 3 is an illustrative drawing of a system and method in accordance with an embodiment of the invention for using a single base input model to produce multiple different IC implementations of an MPEG4 decoder for use in different environments having different power and fidelity constraints.

FIG. 4 is a schematic drawing of an illustrative computer system that can be programmed to implement the system and method of FIGS. 2-3 in accordance with an embodiment of the invention.

Claims

1. A method of synthesis of multiple implementations of an integrated circuit design comprising: translating a model of the design to a first output model compliant with a first set of constraints; andtranslating the input model to a second output model compliant with a second set of constraints.

2. The method of claim 1, wherein translating the input model of the design to the first output model includes using a synthesis tool to map the input model to a lower level model based upon the first set of constraints; andwherein translating the input model to the second output model includes using the synthesis tool to map the model to a lower level model based upon the second set of constraints.

3. The method of claim 1, wherein the first set of constraints is directed to higher speed operation of the integrated circuit than is the second set of constraints.

4. The method of claim 1, wherein the first set of constraints is directed to lower power operation of the integrated circuit than is the second set of constraints.

5. The method claim 1, wherein the first set of constraints is directed to higher fidelity performance of the integrated circuit than is the second set of constraints.

6. The method of claim 1, wherein the first set of constraints optimizes the design for a different implementation than does the second set of constraints.

7. A method of synthesis of multiple implementations of an integrated circuit design, comprising: using a synthesis tool to translate a model of the design to output models, each output model compliant with one of a plurality of sets of constraints;changing the model of the design so as to produce a changed model of the design; andusing the synthesis tool to translate the changed model of the design to changed output models, each output model compliant with one of the plurality of sets of constraints.

8. A method of synthesis of multiple implementations of an integrated circuit design, comprising: providing a model of the design comprising an algorithm implemented by the design;providing a first constraint file including at least one first constraint upon implementation of the model;inputting the model of the design and the first constraint file to a synthesis tool;receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint;providing a second constraint file including at least one second constraint upon implementation of the model;inputting the model of the design and the second constraint file to the synthesis tool; andreceiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one second constraint.

9. The method of claim 8, further including: changing the model of the design to produce a changed model of the design;inputting the changed model of the design and the first constraint file to the synthesis tool; andreceiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint.

10. The method of claim 8, further including: changing the model of the design to produce a changed model of the design;inputting the changed model of the design and the constraint files to the synthesis tool; andreceiving as output from the synthesis tool an output model of the design for implementing the design to meet both the constraint files.

11. The method of claim 8, wherein the at least one first constraint is directed to higher speed operation of the integrated circuit than is the at least one second constraint.

12. The method of claim 8, wherein the at least one first constraint is directed to lower power operation of the integrated circuit than is the at least one second constraint.

13. The method of claim 8, wherein the at least one first constraint is directed to higher fidelity performance of the integrated circuit than is the at least one second constraint.

14. The method claim 8, wherein the at least one first constraint optimizes the design for a different implementation of the integrated circuit than does the at least one second constraint.

15. A computer readable storage media storing code for performing the method of claim 1.

16. A computer readable storage media storing code for performing the method of claim 7.

17. A computer readable storage media storing code for performing the method of claim 8.

18. A computer system programmed to carry out the method of claim 1.

19. A computer system programmed to carry out the method of claim 7.

20. A computer system programmed to carry out the method of claim 8.

21. A computer system, comprising: a CPU;a storage; anda bus coupling the CPU to the storage;wherein the storage stores code for execution by the CPU, the code performing:translating an input model of an integrated circuit design to a first output model compliant with a first set of constraints; andtranslating the input model to a second output model compliant with a second set of constraints.