SYSTEM AND METHOD FOR TESTING AN INPUT/OUTPUT FUNCTIONAL BOARD

Abstract

A computer-based method for testing an input/output functional board is provided. The method includes the steps of: obtaining control information of the computer; testing devices coupled with the input/output functional board by using the control information; and determining whether the devices work normally according to test results. A related system is also disclosed.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of hardware infrastructure of a system for testing an input/output functional board in accordance with a preferred embodiment;

FIG. 2 is a schematic diagram of function modules of a test unit in FIG. 1;

FIG. 3 is a flowchart of a preferred method for testing an input/output functional board in accordance with a preferred embodiment; and

FIG. 4 is a flowchart illustrating one step of FIG. 3 in detail, namely testing an LM 75 chip.

Claims

1. A system for testing an input/output functional board comprising a computer, the computer being connected with the input/output functional board through a test fixture and having a test unit, the test unit comprising: an obtaining module for obtaining control information of the computer;a testing module for testing devices coupled with the input/output functional board by using the control information; anda judging module for determining whether the devices tested work normally according to test results.

2. The system according to claim 1, wherein the test unit further comprises: a saving module for saving the test results; anda reporting module for displaying the test results.

3. The system according to claim 1, wherein the computer further comprises: a general purpose input/output header, a system management bus header and a universal serial bus port.

4. The system according to claim 1, wherein the control information comprises: universal serial bus signals, general purpose input/output signals, and inter-integrated circuit bus signals.

5. The system according to claim 1, wherein the test fixture comprises: a universal serial bus port, a system management bus port, a general purpose input/output port, a power port, and an input/output functional board connector.

6. A computer-based method for testing an input/output functional board, the method comprising the steps of: obtaining control information of the computer;testing devices coupled with the input/output functional board by using the control information; anddetermining whether the tested devices work normally according to test results.

7. The method according to claim 6, wherein the control information comprises: universal serial bus signals, general purpose input/output signals, and inter-integrated circuit bus signals.

8. The method according to claim 6, wherein the testing step comprises: turning on the power of inter-integrated circuit devices of the input/output functional board;selecting a channel to be tested;testing one or more memory storage devices connected with the input/output functional board;testing one or more chips of the input/output functional board; andtesting one or more indicator lights.

9. The method according to claim 8, wherein the memory storages comprise: CDROMs, FDDs, and USB disks.

10. The method according to claim 8, wherein the step of testing one of the chips comprises: reading the environmental temperature of the computer as T1;reading the environmental temperature of the chip as T2;determining whether the difference between T1 and T2 is less than a predetermined value;detecting the interrupt pin status of the chip if the difference is less than the predetermined value;changing a limited temperature of the chip; anddetermining the interrupt pin is normal if the interrupt pin status changes;determining the interrupt pin is abnormal if the interrupt pin status does not change.

11. The method according to claim 10, further comprising: determining the chip is abnormal if the difference between T1 and T2 is more than the predetermined value.

12. The method according to claim 10, wherein the predetermined value is 5° C.

13. The method according to claim 10, wherein the interrupt pin status is one of: a low level status and a high level status.

14. The method according to claim 13, wherein the step of changing a limited temperature of the chip comprises: reducing the limited temperature of the chip to make the limited temperature lower than the environmental temperature of the chip if the interrupt pin of the chip outputs the low level status;raising the limited temperature of the chip to make the limited temperature higher than the environmental temperature of the chip if the interrupt pin of the chip outputs the high level status.

15. The method according to claim 6, further comprising: saving the test results; andreporting the test results.