Claims
- 1. A method of controlling clock-data phase relationship in a high-speed data conversion circuit, comprising the steps of:
receiving a data signal at the data conversion circuit; recovering a high-speed clock signal having a first clock rate from the data signal; receiving multiple-phase input clock signals having a second clock rate at an interpolator, wherein the interpolator functions in either a normal mode of operation or a testing mode of operation, wherein in the testing mode of operation the first clock rate and second clock rate differ; rotating with the interpolator the phase of the multiple-phase input clock signals to produce multiple-phase output clock signals at the second clock rate, wherein the multiple-phase output clock signals input into a slicer; sensing a phase difference between the data signal and the multiple-phase output clock signals at the slicer, wherein the phase difference generates a feedback signal used by the interpolator to adjust the multiple-phase output clock signals; and slicing the data signal with the multiple-phase output clock signal about midway between crossing points of the multiple-phase output clock signals to produce at least one output data signal.
- 2. The method of claim 1, wherein the interpolator manipulates the phase difference between the data signal and the multiple-phase output clock signal by rotating individual phases of the multiple-phase input clock signals.
- 3. The method of claim 1, wherein the interpolator manipulates the phase difference between the data signal and the multiple-phase output clock signal by selectively weighting and summing a plurality of multiple-phase input clock signals having differing phases.
- 4. The method of claim 1, wherein a loop filter attenuates rapid variations in the phase difference between the data signal and the multiple-phase output clock signal.
- 5. The method of claim 3, further comprising the steps of:
dividing down a reference clock signal at a reference frequency to produce a reduced frequency clock signal; multiplexing the reduced frequency clock signal with a testing clock signal to produce a multiplexed reduced frequency clock/testing clock signal; and differentially dividing the multiplexed reduced frequency clock/testing clock signal to produce the multiple-phase input clock signals.
- 6. The method of claim 1, further comprising the steps of:
demultiplexing the output data signal of the slicer to produce a plurality of reduced data rate signals; and aligning the plurality of reduced data rate signals to a second reduced frequency clock signal with an elastic FIFO buffer.
- 7. The method of claim 1, wherein a testing clock signal, being at a frequency different from the reduced frequency clock signal, forces functions of the interpolator to be exercised.
- 8. A method of testing for proper operation an interpolator used within a data conversion circuit to align a clock signal to a data signal, comprising the steps of
receiving a data signal at the data conversion circuit; recovering a high-speed clock signal having a first clock rate from the data signal; generating multiple-phase input clock signals having a second clock rate as inputs to the interpolator, wherein in a normal mode of operation the multiple-phase input clock signals are derived from a reference clock, and wherein in a testing mode of operation a testing clock combines with the reference clock to produce the multiple-phase input clock signals and wherein the second clock rate and first clock rate differ in the testing mode of operation; rotating with the interpolator the phase of the multiple-phase input clock signals to produce multiple-phase output clock signals at the second clock rate, wherein the multiple-phase output clock signals input into a slicer; and sensing a phase difference between the data signal and the multiple-phase output clock signals at the slicer, wherein the phase difference generates a feedback signal used by the interpolator to adjust the multiple-phase output clock signals, such that the data signal may be sampled with the multiple-phase output clock signal at about midway between crossing points of the multiple-phase output clock signals.
- 9. The method of claim 8, wherein the interpolator manipulates the phase difference between the data signal and the multiple-phase output clock signal by rotating individual phases of the multiple-phase input clock signals.
- 10. The method of claim 8, wherein the interpolator manipulates the phase difference between the data signal and the multiple-phase output clock signal by selectively weighting and summing a plurality of input clock signals having differing phases.
- 11. The method of claim 8, wherein a loop filter attenuates rapid variations in the phase difference between the data signal and the multiple-phase output clock signal.
- 12. The method of claim 8, further comprising the steps of:
dividing down a reference clock signal at a reference frequency to produce a reduced frequency clock signal; multiplexing the reduced frequency clock signal with a testing clock signal to produce a multiplexed reduced frequency clock/testing clock signal; and differentially dividing the multiplexed reduced frequency clock/testing clock signal to produce the multiple-phase input clock signals.
- 13. A high-speed data conversion circuit, that controls a clock-data phase relationship, comprising:
a slicer that is operable to receive a data signal having a data rate and that slices the data signal to produce an output data signal wherein the slicer further comprises a phase detector that is operable to determine a phase difference between the data signal and multiple-phase output clock signals to produce a phase difference signal; an up/down counter that is operable to receive the phase difference signal from the slicer; an interpolator that is operable to receive an output from the up/down counter, to rotate multiple-phase input clock signals to produce the multiple-phase output clock signals based on the output from the up/down counter, and that to supply the multiple-phase output clock signals; and wherein the interpolator is operable to rotate individual phases of the multiple-phase input clock signals to establish a predetermined phase difference between the data signal and the multiple-phase output clock signals.
- 14. The high-speed data conversion circuit of claim 13, wherein the predetermined phase difference aligns a sample point on the data signal to about midway between crossing points of at least one phase of the multiple-phase output clock signals.
- 15. The high-speed data conversion circuit of claim 13, wherein the interpolator is operable to manipulate the phase difference between the data signal and the multiple-phase output clock signals by rotating individual phases of the multiple-phase input clock signals.
- 16. The high-speed data conversion circuit of claim 13, wherein the interpolator is operable to manipulate the phase difference between the data signal and the multiple-phase output clock signals by selectively weighting and summing the multiple-phase input clock signals.
- 17. The high-speed data conversion circuit of claim 13, further comprising a loop filter that is operable to attenuate rapid variations in the phase difference between the data signal and the multiple-phase output clock signals.
- 18. The high-speed data conversion circuit of claim 13, further comprising:
a reference clock signal operable to produce a reference frequency; a first divider circuit that is operable to divide the reference clock signal to produce a reduced frequency clock signal; a 2:1 multiplexer that is operable to multiplex the reduced frequency clock signal with a testing clock signal; and a differential divider that is operable to divide a multiplexed reduced frequency clock/testing clock signal outputted from the 2:1 multiplexer to produce multiple-phase input clock signals.
- 19. The high-speed data conversion circuit of claim 18, further comprising: a 2:4 demultiplexer that is operable to demultiplex the output data signal of the slicer, and to produce reduced data rate signals; and
an elastic FIFO buffer that is operable to align the reduced data rate signals to a reduced frequency clock signal derived from the reference clock signal.
- 20. The high-speed data conversion circuit of claim 18, wherein the testing clock signal, being at a frequency different from the reduced frequency clock signal forces the interpolator's functions to be exercised.
RELATED APPLICATIONS
[0001] This application is a continuation-in-part of U.S. patent application Ser. No. 10/390,490, entitled LOOP BACK TESTING STRUCTURE FOR HIGH-SPEED SERIAL BIT STREAM TX AND RX CHIP SET, and filed Mar. 17, 2003 which claims the benefit of U.S. Provisional Patent Application Serial No. 60/401,708, filed Aug. 6, 2002, both of which are incorporated herein by reference in their entirety for all purposes. This application is also a continuation-in-part of U.S. patent application Ser. No. 10/445,771, filed May 27, 2003 which claims the benefit of U.S. Provisional Patent Application Serial No. 60/403,457, filed Aug. 12, 2002, both of which are incorporated herein by reference in their entirety for all purposes.
Provisional Applications (2)
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Number |
Date |
Country |
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60401708 |
Aug 2002 |
US |
|
60403457 |
Aug 2002 |
US |
Continuation in Parts (2)
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Number |
Date |
Country |
Parent |
10390490 |
Mar 2003 |
US |
Child |
10778419 |
Feb 2004 |
US |
Parent |
10445771 |
May 2003 |
US |
Child |
10778419 |
Feb 2004 |
US |