Patent Application
20130033335
The present disclosure relates generally to semi-digital finite impulse response (sFIR) filters, including, without limitation, a system and method for tuning a semi-digital finite impulse response filter.
Wireless communications systems are used in a variety of telecommunications systems, television, radio and other media systems, data communication networks, and other systems to convey information between remote points using wireless transmitters and wireless receivers. A transmitter is an electronic device which, usually with the aid of an antenna, propagates an electromagnetic signal such as radio, television, or other telecommunications. Transmitters often include signal amplifiers which receive a radio-frequency or other signal, amplify the signal by a predetermined gain, and communicate the amplified signal. A receiver is an electronic device which receives and processes a wireless electromagnetic signal. A transmitter and receiver may be combined into a single device called a transceiver.
Transmitters, receivers, and transceivers often include components known as oscillators. An oscillator may serve many functions in a transmitter, receiver, and/or transceiver, including generating a local oscillator signal (e.g., a clock signal) (usually in a radio-frequency range) for upconverting baseband signals onto a radio-frequency (RF) carrier and performing modulation for transmission of signals, and/or for downconverting RF signals to baseband signals and performing demodulation of received signals.
Some oscillators may comprise a voltage controlled oscillator module configured to generate the clock signal, where the frequency of the oscillator may be controlled by a control voltage. The control voltage may be based on a control signal from a digital controller and the control signal may be converted into an analog signal by a digital to analog converter (DAC). However, the DAC may have undesirable high frequency, high power noise. Traditional systems may use a passive resistor/capacitor (RC) network to filter out this noise. However, such networks may not be sufficiently precise, especially considering variations that may occur during fabrication.
In accordance with some embodiments of the present disclosure, a method for tuning a semi-digital finite impulse response (sFIR) filter comprises coupling a switch between an output of a shift register element associated with an input of the sFIR filter and a resistor coupled to an output of the sFIR filter. The shift register element and the resistor are associated with a tap of the sFIR filter. The method further comprising at least one of closing the switch according to a control signal to couple the resistor with the output of the shift register element such that a tap is added to the sFIR filter in order to tune a corner frequency of the sFIR filter and opening the switch according to the control signal to decouple the resistor from the output of the shift register element such that a tap is subtracted from the sFIR filter in order to tune the corner frequency of the sFIR filter.
For a more complete understanding of the present disclosure and its features and advantages, reference is now made to the following description, taken in conjunction with the accompanying drawings, in which:
A terminal 110 may or may not be capable of receiving signals from satellites 130. Satellites 130 may belong to a satellite positioning system such as the well-known Global Positioning System (GPS). Each GPS satellite may transmit a GPS signal encoded with information that allows GPS receivers on earth to measure the time of arrival of the GPS signal. Measurements for a sufficient number of GPS satellites may be used to accurately estimate a three-dimensional position of a GPS receiver. A terminal 110 may also be capable of receiving signals from other types of transmitting sources such as a Bluetooth transmitter, a Wireless Fidelity (Wi-Fi) transmitter, a wireless local area network (WLAN) transmitter, an IEEE 802.11 transmitter, and any other suitable transmitter.
In
System 100 may be a Code Division Multiple Access (CDMA) system, a Time Division Multiple Access (TDMA) system, or some other wireless communication system. A CDMA system may implement one or more CDMA standards such as IS-95, IS-2000 (also commonly known as “1x”), IS-856 (also commonly known as “1xEV-DO”), Wideband-CDMA (W-CDMA), and so on. A TDMA system may implement one or more TDMA standards such as Global System for Mobile Communications (GSM). The W-CDMA standard is defined by a consortium known as 3GPP, and the IS-2000 and IS-856 standards are defined by a consortium known as 3GPP2.
As discussed further below, element 200 may include an oscillator circuit 210 that may comprise a voltage controlled oscillator module configured to generate a clock signal, where the frequency of the oscillator may be controlled by a control voltage. The control voltage may be based on a control signal from digital circuitry 202 and the control signal may be converted into an analog signal by a digital to analog converter (DAC) of oscillator circuit 210. As described in further detail below, oscillator circuit 210 may also include a tunable, semi-digital finite impulse response (sFIR) filter configured to filter out noise that may be generated by the DAC controlling the oscillator circuit. The sFIR filter may include both digital and analog components that may filter generated by the DAC. As such, the sFIR filter may include a digital corner frequency and an analog corner frequency. As discussed further below, the sFIR filter may be configured to be tuned such that its analog corner frequency may more closely relate to a desired analog corner frequency to more effectively filter out the noise of the DAC.
Element 200 may include a transmit path 201 and/or a receive path 221. Depending on the functionality of element 200, element 200 may be considered a transmitter, a receiver, or a transceiver.
As depicted in
Controller 211 may comprise any system, device, or apparatus configured to interpret and/or execute program instructions and/or process data, and may include without limitation a microprocessor, microcontroller, digital signal processor (DSP), application specific integrated circuit (ASIC), or any other digital or analog circuitry configured to interpret and/or execute program instructions and/or process data. In some embodiments, controller 211 may interpret and/or execute program instructions and/or process data stored in memory communicatively coupled to controller 211 (not expressly shown).
Memory may comprise any system, device or apparatus operable to retain program instructions or data for a period of time (e.g., computer-readable media). Memory may include random access memory (RAM), electrically erasable programmable read-only memory (EEPROM), a PCMCIA card, flash memory, magnetic storage, opto-magnetic storage, or any suitable selection and/or array of volatile or non-volatile memory that retains data after power to controller 211 is turned off.
Transmit path 201 may include a digital-to-analog converter (DAC) 204. DAC 204 may be configured to receive a digital signal from digital circuitry 202 and convert such digital signal into an analog signal. Such analog signal may then be passed to one or more other components of transmit path 201, including upconverter 208. Upconverter 208 may be configured to frequency upconvert an analog signal received from DAC 204 to a wireless communication signal at a radio frequency based on an oscillator signal provided by oscillator circuit 210.
Oscillator circuit 210 may be any suitable device, system, or apparatus configured to produce an analog waveform of a particular frequency for modulation or upconversion of an analog signal to a wireless communication signal, or for demodulation or downconversion of a wireless communication signal to an analog signal. Accordingly, oscillator circuit 210 may produce a clock signal that may be used for modulation or demodulation.
As described above, in some embodiments, oscillator circuit 210 may comprise a voltage controlled oscillator module configured to generate a clock signal having the desired frequency according to a received control voltage that may be based on a control signal received from controller 211. As mentioned previously, and described in further detail with respect to
Transmit path 201 may include a variable-gain amplifier (VGA) 214 to amplify an upconverted signal for transmission, and a bandpass filter 216 configured to receive an amplified signal VGA 214 and pass signal components in the band of interest, and remove out-of-band noise and undesired signals. The bandpass filtered signal may be received by power amplifier 220 where it is amplified for transmission via antenna 218. Antenna 218 may receive the amplified signal from power amplifier 220 and may transmit the amplified signal through a wireless communication network (e.g., to one or more of a terminal 110, a base station 120, and/or a satellite 130).
Receive path 221 may include a bandpass filter 236 configured to receive a wireless communication signal (e.g., from a terminal 110, a base station 120, and/or a satellite 130) via antenna 218. Bandpass filter 236 may pass signal components in the band of interest and remove out-of-band noise and undesired signals. In addition, receive path 221 may include a low-noise amplifier (LNA) 224 to amplify a signal received from bandpass filter 236.
Receive path 221 may also include a downconverter 228. Downconverter 228 may be configured to frequency downconvert a wireless communication signal received via antenna 218 and amplified by LNA 234 by an oscillator signal provided by oscillator 210 (e.g., downconvert to a baseband signal). Receive path 221 may further include a filter 238, which may be configured to filter a downconverted wireless communication signal in order to pass the signal components within a radio-frequency channel of interest and/or to remove noise and undesired signals that may be generated by the downconversion process. In addition, receive path 221 may include an analog-to-digital converter (ADC) 224 configured to receive an analog signal from filter 238 and convert such analog signal into a digital signal. Such digital signal may then be passed to digital circuitry 202 for processing.
VCO module 310 may be configured to generate a signal having a particular frequency based on the received control voltage. A VCO may comprise any suitable component configured to generate a signal having a particular frequency according to a control voltage received by the VCO. In some embodiments, the VCO may comprise a voltage controlled, temperature compensated oscillator (VCTCXO) that may comprise any suitable component configured to generate a signal having a particular frequency according to a control voltage, and that also includes one or more temperature compensating components.
The control voltage generated by DAC 302 may include noise that may need to be filtered out such that VCO module 310 may generate a sufficiently clean signal. Accordingly, oscillator circuit 210 may also include a tunable sFIR filter 304 configured to have a digital corner frequency and an analog corner frequency at a desired level such that the noise of DAC 302 may be sufficiently filtered out. The output of sFIR filter 304 may be coupled to VCO module 310 such that VCO module 310 may receive the filtered signal.
As mentioned above, tunable sFIR filter 304 may be configured to have corner frequencies for filtering out noise that may be caused by DAC 302. Filter 304 may be configured such that the number of taps of filter 304 may be increased or decreased such that the analog component of filter 304 may be tuned to a desired corner frequency. Filter 304 may also include a capacitor C that may establish the analog corner frequency of filter 304. The desired analog corner frequency may be based on filtering out undesirable noise that may be generated by DAC 302.
Filter 304 may include a shift register 306 that may include “M-N” number of elements (e.g., elements E1-EM−N). Shift register 306 may be configured to shift the values of input signals received from DAC 302 through elements Ei of shift register 306 according to a received clock signal. In the present example, elements Ei may comprise D flip-flops. For example, upon receiving a clock signal, each element Ei may store an input signal and output a signal that may have been stored upon receiving the previous clock signal. Accordingly, each element Ei may store and output previous values of the output signal such that each element Ei may be associated with an order number of sFIR filter 304. The input of shift register 306 and the output of each element Ei of shift register 306 may be coupled to a resistor Resistors Ri may also be coupled to the output of filter 304. For example, resistor R0 may be coupled to the input of shift register 306 at one end and the output of filter 304 at the other end, resistor R1 may be coupled to the output of element E1 at one end and the output of filter 304 at its other end, etc.
Each resistor Ri, and its associated element Ei, of filter 304 may be associated with a tap of filter 304 that may affect the analog corner frequency of filter 304. The number of taps of filter 304 and the resistors associated with the taps may affect the resistance associated with the analog corner frequency of filter 304. Therefore, by adding or subtracting taps of filter 304, the resistance associated with the analog corner frequency of filter 304 may be adjusted.
In the present example, filter 304 may also include “2×N” number of single element shift registers 308 (e.g., registers 3081-3082N) that may each include an element Ei (e.g., elements EM−N+1-EM+N) configured to store and shift previous values of an input signal received from each register's previous input. Similar to the elements Ei of shift register 306, each element Ei of shift registers 308 may be associated with a resistor Ri. Unlike the elements Ei of shift register 306, the output of elements Ei of each shift register 308 may be coupled to a switch 310 (e.g., switches 3101-3102N). Switches 310 may be configured to be opened or closed to couple or decouple the output of the element Ei of the shift register 308 with its associated resistor Ri. Thus, switches 310 may be configured to couple or decouple elements Ei of registers 308 to the output of filter 304 to adjust the number of taps of filter 304, which may affect the resistance of filter 304 associated with the analog corner frequency of filter 304.
For example, switch 3101 may be coupled between resistor RM−N+1 and the output of element EM−N+1 of register 3081. Accordingly, when closed, switch 3101 may couple the output of element EM−N+1 with resistor RM−N+1 such that a tap associated with resistor RM−N+1 may be added to filter 304 and the resistance of RM−N+1 may affect the analog corner frequency of filter 304. Similarly, when open, switch 3101 may decouple the output of element EM−N+1 from resistor RM−N+1 such that the tap associated with resistor RM−N+1 and EM−N+1 may not be included in filter 304 and the resistance of resistor RM−N+1 may not affect the corner frequency of filter 304.
Switches 310 may comprise any suitable switch configured to open and close according to a received control signal. In the present example, switches 310 may be coupled to a controller (e.g., controller 211 of
In the present example, the number of taps of filter 304 (and their associated elements Ei and resistors Ri) may be related to the desired corner frequency of filter 304 and the fabrication variations of filter 304. For example, in the present embodiment, it may be determined that filter 304 may substantially achieve the desired corner frequency if filter 304 has “M” number of taps and their associated elements Ei and “resistors Ri. However, in the present example, the fabrication process of filter 304 may have a variation of 10%. Therefore, in some instances of the present example, upon fabrication of filter 304, to achieve the desired corner frequency of filter 304, the number of taps of filter 304 may need to be adjusted by plus or minus 10% to compensate for the 10% fabrication tolerance.
In the present example, in order to substantially achieve the desired corner frequency of filter 304, filter 304 may be configured to adjust the number of taps of filter 304 by “N” such that the number of taps of filter 304 may be approximately equal to “M±N.” Therefore, in the present example, shift register 306 may include “M” minus “N” (“M−N”) elements Ei, that may be coupled at their output to their associated resistors Ri without a switch 310 coupled between the output of the elements Ei and the resistors Ri because “M−N” elements Ei and their associated resistors Ri may be used regardless of variations that may occur in the fabrication process.
Additionally, in the present example, filter 304 may include 2×N single element shift registers 308 that may each be associated with an element Ei, Ri and their associated taps. The output of each element Ei of each shift register 308 may be coupled to or decoupled from its associated resistor Ri by a switch 310 such that taps may be added to or subtracted from filter 304 by closing or opening, respectively, one or more switches 310. Therefore, depending on the variations that occur in the fabrication process, anywhere from zero to 2×N taps may be added to filter 304 to achieve the desired analog corner frequency of filter 304. The analog corner frequency of sFIR filter 304 may be measured upon fabricating filter 304 and the controller of the element associated with sFIR filter 304 (e.g., controller 211 of element 200 in
For example, if the process variation is such that filter 304 may substantially have the desired corner frequency with “M−N” taps, switches 3101 through 3102N may be opened such that the outputs of shift registers 3081 through 3082N are not coupled to the output of filter. Accordingly, filter 304 may comprise “M−N” taps to achieve the desired corner frequency based at least partially on the resistances associated with the taps.
As another example, in other instances, the process variation may be such that “M+N” taps of filter 304 (and their associated resistances based on resistors Ri) may achieve the desired analog corner frequency of filter 304. In such instances, every switch 310 may be closed such that each register 308 adds a tap to filter 304 to achieve “M+N” taps of sFIR filter 304 such that the corner frequency of filter 304 is substantially equal to the desired corner frequency.
Therefore, sFIR filter 304 may be configured to be tunable to account for potential variations in the actual analog corner frequency versus the desired analog corner frequency due to fabrication process variations. As such, the accuracy of signals generated by VCO module 310 may be improved to improve the performance of oscillator circuit 210. Additionally, the number of taps that may be added or subtracted from sFIR filter 304 (and their associated resistors Ri, elements Ei and switches 310) may at least be partially based on the fabrication process variations of the circuit. By basing the number of taps that may be added or subtracted in part, according to the fabrication process variations, the amount of chip space occupied by sFIR filter 304 may be reduced.
Modifications, additions and omissions may be made to
Although the present disclosure has been described with several embodiments, various changes and modifications may be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications as fall within the scope of the appended claims.
