System and method for validating program execution at run-time

Information

  • Patent Grant
  • 9767271
  • Patent Number
    9,767,271
  • Date Filed
    Monday, December 28, 2015
    9 years ago
  • Date Issued
    Tuesday, September 19, 2017
    7 years ago
Abstract
A pipelined processor comprising a cache memory system, fetching instructions for execution from a portion of said cache memory system, an instruction commencing processing before a digital signature of the cache line that contained the instruction is verified against a reference signature of the cache line, the verification being done at the point of decoding, dispatching, or committing execution of the instruction, the reference signature being stored in an encrypted form in the processor's memory, and the key for decrypting the said reference signature being stored in a secure storage location. The instruction processing proceeds when the two signatures exactly match and, where further instruction processing is suspended or processing modified on a mismatch of the two said signatures.
Description
FIELD OF THE INVENTION

The present invention relates to systems and methods for secure computing.


BACKGROUND OF THE INVENTION

Current computer systems are highly vulnerable to cyber attack. The number of attacks and the financial losses due to those attacks have risen exponentially. Despite significant investments, the situation continues to worsen; novel attacks appear with high frequency and employ increasingly sophisticated techniques. There are very few fundamental sources of the vulnerabilities exploited by cyber attackers. These attacks stem from the fact that current computer systems cannot enforce the intended semantics of their computations. In particular, they fail to systematically enforce: Memory safety, Type safety, The distinction between code and data, and Constraints on information flow and access. These properties are not systematically enforced today because they are not: Systematically captured during the design process; Formally analyzed or verified during design and implementation; Captured or enforced by common system programming languages (e.g., the C programming language); and Represented explicitly within the runtime environment of the system and therefore cannot be enforced dynamically by either hardware or software techniques.


DARPA (DARPA-BAA-10-70, Jun. 1, 2010) has therefore initiated the Clean-Slate Design of Resilient, Adaptive, Secure Hosts (CRASH) program. This program seeks designs for computing systems which are highly resistant to cyber-attack; can adapt after a successful attack in order to continue rendering useful services; can learn from previous attacks how to guard against and cope with future attacks; and can repair themselves after attacks have succeeded.


Current system software is large and complex. Hardware architectures provide mechanisms to protect the kernel from user code, but at the same time grant to the kernel unlimited privileges (at best, a few levels of increased privilege). Consequently, a single penetration into the kernel gives the attacker unlimited access. Since the cost of switching into kernel mode is high, there is a tendency for system programmers to move increasing amounts of functionality into the kernel, making it even less trustworthy and exposing an even larger attack surface. Likewise, programming flaws can result in unintended access to kernel or increased privilege level system access.


Current computer systems are not resilient to attacks. They lack the means to recover from attacks either by finding alternative methods for achieving their goals or by repairing the resources corrupted by the attack. They also typically lack the ability to diagnose the underlying problem and to fix the vulnerabilities that enabled the attack. Once a machine is corrupted, manual repairs by specialized personnel are required while the forensic information necessary to affect the repair is typically lacking. Finally, today's computer systems are nearly identical to one another, do not change appreciably over time, and share common vulnerabilities. A single network-based attack can therefore spread rapidly and affect a very large number of computers.


“Trusted Platform Module” is the name of a published specification detailing a secure cryptoprocessor that can store cryptographic keys that protect information, as well as the general name of implementations of that specification, often called the “TPM chip”. The TPM specification is the work of the Trusted Computing Group. The current version of the TPM specification is 1.2 Revision 103, published on Jul. 9, 2007.


The Trusted Platform Module offers facilities for the secure generation of cryptographic keys, and limitation of their use, in addition to a hardware pseudo-random number generator. It also includes capabilities such as remote attestation and sealed storage. “Remote attestation” creates a nearly unforgeable hash key summary of the hardware and software configuration. The extent of the summary of the software is decided by the program encrypting the data. This allows a third party to verify that the software has not been changed. “Binding” encrypts data using the TPM endorsement key, a unique RSA key burned into the chip during its production, or another trusted key descended from it. [3] “Sealing” encrypts data similar to binding, but in addition specifies a state in which the TPM must be in order for the data to be decrypted (unsealed).


A Trusted Platform Module can be used to authenticate hardware devices. Since each TPM chip has a unique and secret RSA key burned in as it is produced, it is capable of performing platform authentication. For example, it can be used to verify that a system seeking access is the expected system.


The Trusted Platform Module is typically part of the supporting chipset for a processor system, and thus its use typically delays execution of instructions by the processor until verification is completed. Likewise, verification occurs with respect to instructions before they are cached by the processor. Thus, while the TMP provides secure data processing, it does not address insecurities in moving instructions to the processor, and is susceptible to instruction injection type attaches, and likewise introduces significant latencies.


Generally, pushing the security down to the hardware level in conjunction with software provides more protection than a software-only solution that is more easily compromised by an attacker. However even where a TPM is used, a key is still vulnerable while a software application that has obtained it from the TPM is using it to perform encryption/decryption operations, as has been illustrated in the case of a cold boot attack.


The “Cerium” technology (Chen and Morris, “Certifying Program Execution with Secure Processors”, Proceedings of the 9th conference on Hot Topics in Operating Systems, USENIX, Volume 9, Pages: 133-138, 2003), expressly incorporated herein by reference, proposes a secure processor technology which validates cache line signature before commencement of processing. It provides a separate security co-processor, which is not integrated into main processing pipeline. Cerium computes signatures of the system software as it boots up, and uses these signatures to enforce copy protection. The software at each stage self checks its integrity against a reference signature stored in the co-processor's non-volatile memory. Each stage also authenticates the software for the next stage. Cerium assumes the existence and use of a cache where operating system and trusted code can be kept. See, also, Cliff Wang, Malware Detection, Advances in information security, Mihai Christodorescu, Somesh Jha, Douglas Maughan, Dawn Song, Cliff Wang, Editors, Springer, 2006.


Boneh et al., “Hardware Support for Tamper-Resistant and Copy-Resistant Software”, Technical Report: CS-TN-00-97, (Stanford University, 2000), expressly incorporated herein by reference, provides a description of a hardware prototype which supports software-only taper resistant computing, with an atomic decrypt-and-execute operation.


U.S. Pat. No. 7,730,312, expressly incorporated herein by reference, provides a tamper resistant module certification authority. Software applications may be securely loaded onto a tamper resistant module (TRM) and securely deleted from the TRM. A method for determining, based at least upon an encrypted personalization data block, whether a TRM is part of a qualified set of TRM's to accept loading of an application is also provided. Thereafter, the method provides for loading the application onto the TRM only after the first step determines that the TRM is qualified to accept the loading of the application. A method is also provided for determining, based at least upon an encrypted personalization data block, whether a TRM is part of a qualified set of TRM's to accept deleting of an application. Thereafter, the method provides for deleting the application from the TRM only when the first step determines that the TRM is qualified to accept the deleting of the application.


U.S. Pat. No. 7,590,869, expressly incorporated herein by reference, provides an on-chip multicore type tamper resistant microprocessor, which has a feature that, on the microprocessor package which has a plurality of instruction execution cores on an identical package and an ciphering processing function that can use a plurality of ciphering keys in correspondence to programs under a multi-task program execution environment, a key table for storing ciphering keys and the ciphering processing function are concentrated on a single location on the package, such that it is possible to provide a tamper resistant microprocessor in the multi-processor configuration that can realize the improved processing performance by hardware of a given size compared with the case of providing the key table and the ciphering processing function distributedly.


U.S. Pat. No. 7,739,517, expressly incorporated herein by reference, provides a secure hardware device which compares code image with a known good code image, using a co-processor separate from the processor, which halts execution of code until it is verified. Reference code or its signature is stored in secure, separate storage, but is not itself encrypted. The separate co-processor is not integrated into main processing pipeline to avoid significant delays.


U.S. Pat. No. 7,734,921, expressly incorporated herein by reference, provides a system and method for guaranteeing software integrity via combined hardware and software authentication. The system enables individual user devices to authenticate and validate a digital message sent by a distribution center, without requiring transmissions to the distribution center. The center transmits the message with an appended modulus that is the product of two specially selected primes. The transmission also includes an appended authentication value that is based on an original message hash value, a new message hash value, and the modulus. The new message hash value is designed to be the center's public RSA key; a corresponding private RSA key is also computed. Individual user devices combine a digital signet, a public modulus, preferably unique hardware-based numbers, and an original message hash to compute a unique integrity value K. Subsequent messages are similarly processed to determine new integrity values K′, which equal K if and only if new messages originated from the center and have not been corrupted.


U.S. Pat. No. 7,725,703, expressly incorporated herein by reference, provides Systems and methods for securely booting a computer with a trusted processing module (TPM). In a computer with a TPM, an expected hash value of a boot component may be placed into a platform configuration register (PCR), which allows a TPM to unseal a secret. The secret may then be used to decrypt the boot component. The hash of the decrypted boot component may then be calculated and the result can be placed in a PCR. The PCRs may then be compared. If they do not, access to the an important secret for system operation can be revoked. Also, a first secret may be accessible only when a first plurality of PCR values are extant, while a second secret is accessible only after one or more of the first plurality of PCR values has been replaced with a new value, thereby necessarily revoking further access to the first secret in order to grant access to the second secret.


U.S. Pat. No. 7,694,139, expressly incorporated herein by reference, provides a TPM for securing executable content. A software development system (SDS) executes on a computer having a TPM, and digitally signs software. The platform includes protected areas that store data and cannot be accessed by unauthorized modules. A code signing module executing in a protected area obtains a private/public key pair and a corresponding digital certificate. The SDS is configured to automatically and transparently utilize the code signing module to sign software produced by the system. End-user systems receive the certificate with the software and can use it to verify the signature. This verification will fail if a parasitic virus or other malicious code has altered the software.


U.S. Pat. No. 7,603,707, expressly incorporated herein by reference, provides a Tamper-aware virtual TPM, in which respective threads comprising a virtual TPM thread and a security-patrol threads are executed on a host processor. The host processor may be a multi-threaded processor having multiple logical processors, and the respective threads are executed on different logical processors. While the virtual TPM thread is used to perform various TPM functions, the security-patrol thread monitors for physical attacks on the processor by implementing various numerical calculation loops, wherein an erroneous calculation is indicative of a physical attack. In response to detection of such an attack, various actions can be taken in view of one or more predefined security policies, such as logging the event, shutting down the platform and/or informing a remote management entity.


U.S. Pat. No. 7,571,312, expressly incorporated herein by reference, provides methods and apparatus for generating endorsement credentials for software-based security coprocessors. A virtual manufacturer authority is launched in a protected portion of a processing system. A key for the virtual manufacturer authority is created. The key is protected by a security coprocessor of the processing system, such as a TPM. Also, the key is bound to a current state of the virtual manufacturer authority. A virtual security coprocessor is created in the processing system. A delegation request is transmitted from the processing system to an external processing system, such as a certificate authority (CA). After transmission of the delegation request, the key is used to attest to trustworthiness of the virtual security coprocessor.


U.S. Pat. No. 7,490,352, expressly incorporated herein by reference, provides systems and methods for verifying trust or integrity of executable files. The system determines that an executable file is being introduced into a path of execution, and then automatically evaluates it in view of multiple malware checks to detect if the executable file represents a type of malware. The multiple malware checks are integrated into an operating system trust verification process along the path of execution.


U.S. Pat. No. 7,490,250, expressly incorporated herein by reference, provides a system and method for detecting a tamper event in a trusted computing environment. The computer system has an embedded security system (ESS), a trusted operating system. A tamper signal is received and locked in the ESS. The trusted operating system is capable of detecting the tamper signal in the ESS.


U.S. Pat. No. 7,444,601, expressly incorporated herein by reference, provides a trusted computing platform, in which a trusted hardware device is added to the motherboard, and is configured to acquire an integrity metric, for example a hash of the BIOS memory of the computing platform. The trusted hardware device is tamper-resistant, difficult to forge and inaccessible to other functions of the platform. The hash can be used to convince users that that the operation of the platform (hardware or software) has not been subverted in some way, and is safe to interact with in local or remote applications. The main processing unit of the computing platform is directed to address the trusted hardware device, in advance of the BIOS memory, after release from ‘reset’. The trusted hardware device is configured to receive memory read signals from the main processing unit and, in response, return instructions, in the native language of the main processing unit, that instruct the main processing unit to establish the hash and return the value to be stored by the trusted hardware device. Since the hash is calculated in advance of any other system operations, this is a relatively strong method of verifying the integrity of the system. Once the hash has been returned, the final instruction calls the BIOS program and the system boot procedure continues as normal. Whenever a user wishes to interact with the computing platform, he first requests the integrity metric, which he compares with an authentic integrity metric that was measured by a trusted party. If the metrics are the same, the platform is verified and interactions can continue. Otherwise, interaction halts on the basis that the operation of the platform may have been subverted.


U.S. Pat. No. 6,938,164, expressly incorporated herein by reference, provides a system and method for allowing code to be securely initialized in a computer. A memory controller prevents CPUs and other I/O bus masters from accessing memory during a code (for example, trusted core) initialization process. The memory controller resets CPUs in the computer and allows a CPU to begin accessing memory at a particular location (identified to the CPU by the memory controller). Once an initialization process has been executed by that CPU, the code is operational and any other CPUs are allowed to access memory (after being reset), as are any other bus masters (subject to any controls imposed by the initiated code).


U.S. Pat. No. 6,070,239, expressly incorporated herein by reference, provides a system and method for executing verifiable programs with facility for using non-verifiable programs from trusted sources. The system has a class loader that prohibits the loading and execution of non-verifiable programs unless (A) the non-verifiable program resides in a trusted repository of such programs, or (B) the non-verifiable program is indirectly verifiable by way of a digital signature on the non-verifiable program that proves the program was produced by a trusted source. Verifiable architecture neutral programs are Java bytecode programs whose integrity is verified using a Java bytecode program verifier. The non-verifiable programs are generally architecture specific compiled programs generated with the assistance of a compiler. Each architecture specific program typically includes two signatures, including one by the compiling party and one by the compiler. Each digital signature includes a signing party identifier and an encrypted message. The encrypted message includes a message generated by a predefined procedure, and is encrypted using a private encryption key associated with the signing party. A digital signature verifier used by the class loader includes logic for processing each digital signature by obtaining a public key associated with the signing party, decrypting the encrypted message of the digital signature with that public key so as generate a decrypted message, generating a test message by executing the predefined procedure on the architecture specific program associated with the digital signature, comparing the test message with the decrypted message, and issuing a failure signal if the decrypted message digest and test message digest do not match.


U.S. Pat. No. 5,944,821, expressly incorporated herein by reference, provides a secure software registration and integrity assessment in a computer system. The method provides secure registration and integrity assessment of software in a computer system. A secure hash table is created containing a list of secure programs that the user wants to validate prior to execution. The table contains a secure hash value (i.e., a value generated by modification detection code) for each of these programs as originally installed on the computer system. This hash table is stored in protected memory that can only be accessed when the computer system is in system management mode. Following an attempt to execute a secured program, a system management interrupt is generated. An SMI handler then generates a current hash value for the program to be executed. In the event that the current hash value matches the stored hash value, the integrity of the program is guaranteed and it is loaded into memory and executed. If the two values do not match, the user is alerted to the discrepancy and may be given the option to update or override the stored hash value by entering an administrative password.


U.S. 2008/0215920, expressly incorporated herein by reference, provides a processor which generates a signature value indicating a sequence of executed instructions, and the signature value is compared to signature values calculated for two or more possible sequences of executed instructions to determine which instruction sequence was executed. The signature is generated via a signature generator during program execution, and is provided external to the processor via a signature message. There is, in this system, no encryption of a stored signature, nor use of a secret key. The trace message storage unit is operable to store instruction pointer trace messages and executed instruction signature messages. The trace message storage unit is also operable to store messages in at least one of an on-chip or an off-chip trace memory. The executed instruction signature unit is operable to generate a cache line content signature. The signature may be generated via a signature generator during program execution, and provided external to the processor via a signature message such as by using a trace memory or buffer and a tool scan port.



FIG. 1 (of U.S. Patent Application 2008/0215920) (prior art) is a block diagram of a computer system, as may be used to practice various embodiments of the invention. A computer system 100 is in some embodiments a general-purpose computer, such as the personal computer that has become a common tool in business and in homes. In other embodiments, the computer 100 is a special purpose computer system, such as an industrial process control computer, a car computer, a communication device, or a home entertainment device. The computer comprises a processor 101, which is operable to execute software instructions to perform various functions. The memory 102 and processor 101 in further embodiments include a smaller, faster cache memory which is used to store data that is recently used, or that is believed likely to be used in the near future. The software instructions and other data are stored in a memory 102 when the computer is in operation, and the memory is coupled to the processor by a bus 103. When the computer starts, data stored in nonvolatile storage such as a hard disk drive 104 or in other nonvolatile storage such as flash memory is loaded into the memory 102 for the processor's use.


In many general purpose computers, an operating system is loaded from the hard disk drive 104 into memory and is executed in the processor when the computer first starts, providing a computer user with an interface to the computer so that other programs can be run and other tasks performed. The operating system and other executing software are typically stored in nonvolatile storage when the computer is turned off, but are loaded into memory before the program instructions can be executed. Because memory 102 is significantly more expensive than most practical forms of nonvolatile storage, the hard disk drive or other nonvolatile storage in a computerized system often stores much more program data than can be loaded into the memory 102 at any given time. The result is that only some of the program data stored in nonvolatile memory for an executing program, operating system, or for other programs stored in nonvolatile memory can be loaded into memory at any one time. This often results in swapping pieces of program code into and out of memory 102 from the nonvolatile storage 104 during program execution, to make efficient use of the limited memory that is available.


Many modern computer systems use methods such as virtual memory addresses that are mapped to physical memory addresses and paged memory to manage the limited available physical memory 102. Virtual memory allows use of a larger number of memory address locations than are actually available in a physical memory 102, and relies on a memory management method to map virtual addresses to physical memory addresses as well as to ensure that the needed data is loaded into the physical memory. Needed data is swapped into and out of physical memory as needed by loading memory in pages, which are simply large segments of addressable memory that are moved together as a group. Memory management units within the processor or chipset architecture can also change the contents of memory or cache during program execution, such as where new data is needed in memory or is predicted to be needed and the memory or cache is already full.


An executing program may complete execution of all the needed program instructions in a particular page loaded into memory, and proceed to execute more instructions stored in another page. In a typical example, the previously executing page is swapped out of memory and the page containing the newly needed program code is loaded into memory in its place, enabling the processor to continue to execute program instructions from memory. This not only complicates memory management, but complicates debugging executing software as the program code stored in any particular physical memory location might be from any number of different pages with different virtual addresses. Further, program code loaded into memory need not be stored in the same physical memory location every time, and the actual physical address into which a program instruction is stored is not necessarily unique.


When tracing a program, the instruction flow is typically recorded according to the virtual addresses of the executed instructions. An example computer system block diagram is shown in FIG. 2 (of U.S. Patent Application 2008/0215920) (prior art), as may be used to practice some embodiments of the invention. Program code and other data is stored in storage 201, and are not directly associated with specific locations in system memory. The program code is loaded as needed by dynamic memory controller 202, which in various embodiments is an operating system task, a hardware memory controller, or another memory controller. Instructions are loaded as needed into instruction memory 203, which is in various embodiments any volatile or nonvolatile memory that is directly addressable by the processor. The instructions are provided to the processor for execution as shown at 204, and an instruction pointer referencing the currently executed program opcode is incremented at 205. If a branch or jump instruction is executed, the instruction pointer is not simply incremented but is changed to reflect the address of the branch or jump destination instruction. The instruction pointer address data is used to fetch the next instruction from memory as shown at 206, using physical or virtual addressing in various embodiments.


When using physical addresses, the memory management unit 207 need not be present, and the physical address referenced in the instruction pointer can be directly used to retrieve the next instruction from memory. When using virtual addressing, the MMU shown at 207 includes lookup tables built in communication with the dynamic memory controller 202 to convert the virtual address into a physical address. If the virtually addressed data is not physically stored in memory 203, it is loaded into physical memory and its physical memory location is associated with its virtual address in a process known as virtual memory management. In examples where the instruction pointer uses physical addresses, the execution unit 208 passes physical addresses for the executed instructions to a program trace module 209. When virtual addresses are used, the program trace unit receives the virtual address data. In either case, it can be difficult to later determine which program instructions from storage 201 were present in the virtual or physical address locations recorded, such as when a program has completed execution or has reached a breakpoint in the debugging process.


Breakpoints are often used to interrupt program execution at a predetermined point, at which the state of various data can be observed to determine what has happened up to that point in the program. Breakpoints are sometimes set by including them in the high-level language program, and are sometimes implemented as a comparator that looks for a specific instruction at a specific address that stops execution as a result of an address match. But, because the address is not necessarily unique to a particular program instruction, false breaks in program execution can occur before the desired breakpoint is reached when using such methods. Simply detecting false address matches can be performed by halting program execution and comparing the program content from memory to the various pages or memory contents that might possibly be located in that physical memory space. If the last instruction address's content matches the expected program code, the correct program code has been found. If the contents of the last executed address do not match the expected program code, then an exception (or false breakpoint) has been found. This solution is inconvenient if the program is relatively long, as several false program halts can occur before the desired breakpoint is reached. It remains problematic in applications where the program can't be stopped in certain points, such as in the engine control and industrial process control examples discussed earlier.


Another solution is to track loading various blocks of data into the memory, such as by tracing or recording the content of a specific marker location within the various pages or blocks that are swapped into and out of physical memory. This approach becomes impractical when relatively large numbers of pages are swapped in and out of memory, or when the size of data blocks swapped in and out of memory is relatively small. It is also problematic in that it requires additional logic and synchronization to track loading data into memory, particularly if the data is not loaded by the processor but is loaded by a direct memory access (DMA) controller or another such component.


U.S. Patent Application 2008/0215920 proposes identify the code actually executed during program execution. Although simply recording all instructions executed in order would reveal what code is actually executing, recording all executed instructions would require an undesirably large amount of storage space and is not a practical solution. The code is identified instead by use of a signature derived from the code, such as a hash value, a cyclic redundancy code (CRC), or an exclusive-or signature of the sequence of instructions that are actually executed. The length of the signature is selected to be sufficiently large that the odds of two different possible sequences of program instructions having the same signature is sufficiently low that it is not problematic. For example, a register in a processor is set to a zero value before the first instruction in a sequence of code is executed, and each executed instruction is XORed with the value of the register. The resulting value of the register when program execution is halted is therefore very likely unique to the particular sequence of instructions that were executed, enabling the programmer to calculate the signature of various possible code sequences and compare the signatures of the possible code sequences to the signature stored in the register to confirm a specific sequence of instructions. The programmer can therefore confirm the instruction sequence executed up to the point at which the break occurred.


The signature calculation may be restarted whenever a branch is taken, and the running value of the XOR signature value is recorded in a trace file after a certain number of instructions have been executed, such as every 16 instructions. The signature calculation may also be restarted on jump or branch instructions, such that the signature reflects the code sequence since the last jump or branch. In another example, crossing an address boundary triggers a restart in signature calculation, such that when the executed program code address changes from one block or page of memory to another, the signature counting restarts. The signature can also be calculated at any time, even after program halted. The program instructions may execute continuously, with a buffer holding the last four instructions, or a compressed version of the last four instructions executed, such as an 8-bit value derived from each of the last four instructions executed. These instructions are made available to the programmer such as by storing them in a special trace hardware register or by making the instructions available externally so that they can be buffered outside the processor. The signature identifying the program code then comprises the last four instructions executed, or some value derived from the last four instructions such as a signature value derived from XORing the last four instructions or their 8-bit derived values together. This signature can then be compared with the signatures of the possible code sequences that may have been stored in the memory and executed just before program halt.



FIG. 3 (of U.S. Patent Application 2008/0215920) (prior art), is a block diagram of a processor architecture supporting program trace functionality including executed program code signatures. A processor core 301 is operable to execute software instructions, such as are retrieved from memory 102 of FIG. 1 or from cache memory. The presently executing instruction is referenced by an instruction pointer or a program counter, which indicates the address of the currently pending instruction and is incremented as instructions are executed. The instruction pointer is also changed to reflect branch or jump points in the instruction flow. The instruction pointer's indicated address is traced and compressed for storage as part of a program trace record at 302, and the instruction pointer information is formed into a message via a message generator 303. The messages contain the instruction pointer information compressed at 302, and are eventually stored in a log that can be examined after program execution to determine which instructions have executed during the program execution. Compression of the instruction flow is often very beneficial, as the volume of instructions executed can be much larger than the memory available for storing trace information. In one example, instruction pointer messages are compressed by identifying starting instruction addresses and the addresses of the instructions taken at branches or jumps, but not necessarily every intermediate instruction if no branches or jumps are present in the code. In another example, the trace messages are compressed by compressing the address values of the instructions.


A signature generator 304 receives the processor instructions being executed and generates a signature, such as by starting with a zero value and exclusive-ORing the executed instructions to a running signature value. In other embodiments, the signature is derived from a portion of the executing instruction, such as the last eight bits of each instruction, or comprises some other signature calculation method. A variety of hash functions, error correction and checksum functions, and other mathematical or logical functions will be suitable for signature generation, and will allow a debugger to determine which instructions have been executed. The signature data is sent to a signature message generator 305, which takes the signature data from the signature generator logic 304 and periodically formats it into a message that is suitable for storage as part of a program execution trace record. The signature message generator in some embodiments generates a message periodically, such as every 16 instructions, or uses other message generation criteria in other embodiments to trigger generation of a message. The signature message generator may also wait for a specified number of instructions before creating a first signature message, so that the signature value is very likely unique.


Both the signature messages from the signature message generator 305 and the instruction pointer trace unit messages from message generator 303 are forwarded to the message sorter 306, which organizes the message in a standardized readable format. Once the messages are sorted and organized, they are stored in the on-chip trace memory at 307, or are exported via a trace pin interface for storage external to the processor. The stored messages therefore contain instruction address data as well as signature data, so that the addresses of executed instructions can be seen via the instruction address messages and the actual instruction flow can be confirmed via the signature message data. The signature generator 304 may include additional data, such as a separate signature indicating the cache line from which the current instructions are executed. This signature in some embodiments is formed via a similar method such as a hash value calculation or exclusive OR logical function, or in alternate embodiments is formed using other methods such as by using an error correction code word (ECC) of the cache line, and is the result of the cache line from which executing instructions have been retrieved. The signature stays the same as long as execution continues from within the same cache line, but changes when a new cache line is used. The cache line signature in further embodiments is reset periodically, such as at jumps or braches in program flow, similar to the processor instruction signature.


US 2009/0217050, expressly incorporated herein by reference, provides systems and methods to optimize signature verification time for a cryptographic cache. Time is reduced by eliminating at least some of the duplicative application of cryptographic primitives. In some embodiments, systems and methods for signature verification comprise obtaining a signature which was previously generated using an asymmetrical cryptographic scheme, and determining whether an identical signature has previously been stored in a signature cache. If an identical signature has been previously stored in the signature cache, retrieving previously generated results corresponding to the previously stored identical signature, the results a consequence of application of cryptographic primitives of the asymmetrical cryptographic scheme corresponding to the identical signature. The results are forwarded to a signature verifier. In at least some embodiments, at least one of these functions occurs in a secure execution environment. Examples of a secure execution environment, without limitation, include an ARM TRUSTZONE® architecture, a trusted platform module (TPM), Texas Instruments' M-SHIELD™ security technology, etc. Secure execution environment comprises signature cache and at least a portion of security logic. Security logic in turn comprises signature look-up, calculator, hash function and signature verifier, although it should be readily apparent that more or different functions and modules may form part of security for some embodiments. The device obtains the signature (and message) from unsecure environment and promptly presents them to security logic for vetting. Embodiments employ signature look-up to check signature cache to determine whether the specific signature has been presented before. If the specific signature has indeed been previously presented, signature look-up retrieves the corresponding results of the previous utilization of cryptographic primitives corresponding to the relevant digital signature scheme being employed, which results were previously stored at the identified location in signature cache, and forwards the results to signature verifier. Among those results is the hash value of the previous message that is part of the previous signature. Signature verifier calls hash function to perform a hash on newly obtained message, and compares the hash value of the newly obtained message with the hash value retrieved from signature cache. If there is a match, the signature is verified and the message is forwarded for further processing, e.g., uploading into NVM or RAM as the case may be, etc. Thus, execution is commenced after verification.


Vivek Haldar, Deepak Chandra and Michael Franz, “Semantic Remote Attestation—A Virtual Machine directed approach to Trusted Computing”, USENIX Virtual Machine Research and Technology Symposium, May 2004, provides a method for using language-based virtual machines which enables the remote attestation of complex, dynamic, and high-level program properties, in a platform-independent way.


Joshua N. Edmison, “Hardware Architectures for Software Security”, Ph.D Thesis, Virginia Polytechnic Institute and State University (2006), proposes that substantial, hardware-based software protection can be achieved, without trusting software or redesigning the processor, by augmenting existing processors with security management hardware placed outside of the processor boundary. Benefits of this approach include the ability to add security features to nearly any processor, update security features without redesigning the processor, and provide maximum transparency to the software development and distribution processes.


Bryan Parno Jonathan M. McCune Adrian Perrig, “Bootstrapping Trust in Commodity Computers”, IEEE Symposium on Security and Privacy, May 2010, provides a method for providing information about a computer's state, as part of an investigation of trustworthy computing.


SUMMARY OF THE INVENTION

According to a preferred embodiment of invention, the authenticity of instructions in a processor cache is verified within the processor, concurrent with initial execution of the instructions, and instruction processing is not delayed while a reference signature is accessed and is being verified. Thus, the verification proceeds in parallel with instruction execution. Advantageously, the execution pipeline for instructions is longer than the verification latency, so that in the event of a verification exception, instruction execution can be modified or preempted.


This differs from prior systems, e.g., Cerium, which provides strictly sequential order of operations, verification followed by initiation of processing of the instructions. Cerium thus does not lend itself to modern pipelined design, while the preferred embodiment of the present invention exploits modern processor architectures, permitting initial stages of program execution to speculatively execute, with a contingent subsequent exception or flushing occurring dependent on the verification status. If the code passes the verification, there is little or no delay in processing; if the verification fails, the pipeline is purged or other exception taken, thus providing the desired security.


In some embodiments, the verification need not merely flush the instruction pipeline, but in fact can provide a modification of instruction processing (similar to a vectored interrupt), such that the signature verification process can result in alternate execution results and/or pathways, rather than a simple go/nogo option for commitment of execution of an instruction.


In accordance with one embodiment, the verification employs preexisting speculative execution logic of a pipelined processor, in which the verification flag takes the place of a more traditional branch flag. Alternately, logic generally corresponding to, but distinct from, preexisting conditional execution logic may be employed. In the former case, the cache line verification logic is provided as a separate module, which, for example, completes verification within about 8 clock cycles, while the processor instruction decode and execution pipeline executes within about 20 clock cycles. Therefore, since the verification will generally be available before the end of the instruction pipeline, the processor can be better optimized to deal with verification exceptions.


In case of a verification exception, a typical response will be a flushing of the processor instruction decode and execution pipeline, along with a flag which is handled by trusted code, such as a microkernel within the processor, or a call to secure BIOS or operating system code. This general case permits use of the verification as a means to prevent execution of untrusted or malicious code. In other cases, the verification may be used as a means to identify a trust authority for code or a set of privileges, with the verification process used to implement restrictions, which need not be limited to execution per se. For example, a processor may have a set of secure registers, accessible only by code which verifies to a predetermined secure signature. Code which does not verify in accordance with the secure signature, may be blocked from the secure registers, and for example redirected to a different set of registers. A plurality of verification processes may be available, for example, with four different keys, permitting a verification and identification of processes, and contingent execution dependent on the verification.


According to a preferred embodiment, a cache line of instructions is fetched for execution by the processor, which itself is preferably a pipelined processor with a deep pipeline of greater than 5 stages. The processor may itself support parallel execution or parallel speculative execution, with multiple pipelines. As a cache line of instructions is available for processing, an encrypted signature (or set of signatures) putatively associated with the set of instructions is stored in the processor or fetched. Processing of the instructions is commenced, in advance of any result of a verification process. The reference signature is, in parallel with instruction execution, decrypted in the processor using a private key stored in secure memory. The signature of the cache line of instructions is calculated (or precalculated) and compared against the decrypted reference signature, to determine a verification. If the verification is successful, the execution of the instructions is committed, i.e., the results made available or changes in state made to registers. If the verification is unsuccessful, an exception is made, and for example, the instruction processing pipeline flushed before the instructions are committed. Other exception processing might include altering the processor to a “safe” state in which possibly malicious code is contained or prevented from altering other processes or memory, or triggering an operating system process to provide exception handling logic. Thus, the processor might be provided with an ability to handle verified code in a secure processing mode, and unverified code in an insecure or test processing mode.


An embodiment provides a system and method that validates that a program executing on a microprocessor is indeed the intended program. This validation is performed within the microprocessor, and while (concurrently with) the code is executing. In this case, it is possible to distinguish between different routines of verified code; that is, it is not sufficient that the code being executed is “verified”; it must be verified within the context of execution, for example by an operating system or by prior executed verified code. This prevents malicious use of verified code, and permits different levels of verification; an author or source verification, and a runtime verification. In some cases, a system may determine that certain instruction execution flows are incompatible or undesired, and therefore one instruction flow can permanently or temporarily revoke verification credentials for another instruction flow. As discussed above, the result of a failed verification need not be a bar to commitment of execution, and may result in a modification of execution. Thus, an incompatibility may arise because concurrent tasks seek to modify a common register. The verification arbitration may thus result in use of different and non-conflicting sets of registers.


A particular security risk is that programs can be modified by malicious code as they execute, for example in main memory or cache memory. A proposed mechanism detects such tampering as follows: As instructions that constitute the program are fetched into the lowest level cache, a signature Sg is generated for each of these cache lines within the microprocessor, based on techniques known to the art. For example, a hardware signature generator may be provided for the cache lines such that the signature is automatically generated without programmed processor intervention, for each such cache line. The expected signatures of the cache lines are pre-generated by a trusted authority, encrypted using a secret key S and stored in the RAM, along with the normal code. Therefore, in a typical case, the signatures will be created by a software author (in the case of a mass distributed private key), or by the operating system during a secure and trusted software installation process (in the case of a processor-specific private key). Of course, other options are possible for creating and using the expected signature Se, including hybrid schemes.


As instructions from the fetched line are decoded and executed, the encrypted expected signature of the cache line is fetched and decoded internally within the microprocessor using the secret key. This decoded expected signature Se is compared against the generated signature Sg and the result of the match is stored in a table within the microprocessor.


As instructions from the fetched line are committed (e.g., the instruction execution process is complete to the extent that changes to the processor or system state outside of the instruction processing pipeline are to be made), the stored result of comparing Sg and Se are consulted.


If the result indicates a match, instructions are committed normally.


If the result indicates a mismatch, further execution is halted and appropriate measures are invoked.


If, at the time of committing an instruction, a table entry exists but the results of the comparison are pending, instruction commitment may be held up momentarily.


If a matching entry does not exist at the time of commitment, the pipeline may be flushed, or other steps taken.


It is noted that it is also possible to include within the verification a partial execution result. That is, the verification is dependent on Se, Sg, and a processor register and/or pipeline state. In this way, security against both unverified instructions and certain types of data can be obtained. Of course, separate verification of data states and/or sequences may also be implemented.


Sg and Se need not be compared prior to processing the fetched instructions. This mitigates the delays in accessing the encoded expected signature Se and the delays of generating a new signature Sg and decoding the expected signature for comparison from affecting the microprocessor's instruction processing rate.


Assuming that code is executed in an expected manner, it is possible to predictively call Se, and begin decoding, in order to avoid delay. A set of Se may be cached in the processor, in volatile or non-volatile memory. Thus, a preferred embodiment provides that instruction verification and execution can concurrently occur, but that this need not be the case in all circumstances.


This scheme can be used for a number of purposes, including:


1. Detection of malicious attempts to modify code.


2. Ensure that only certified code can run and provides detection at run-time tampering of such code.


3. Permit trustworthy code to be distributed and used.


4. Detect instruction corruption due to faults—permanent or transient.


5. Execute instructions with results dependent on a signature verification.


Likewise, the present scheme can also serve the various purposes known for other secure processing platforms, and may generally be used in conjunction with other known security technologies. Thus, the present verification process is generally transparent to existing system architectures and execution paradigms, with the exception that the expected signatures must be available at runtime, and the small amount of overhead for calling the expected signatures and any delays from the verification process are tolerable. Since most modern computing platforms employing multilevel instruction cache and deep pipelines are non-deterministic, the expected overhead from the present verification processes, about 2% of processing capacity, is generally tolerable, and indeed, since the signature verification logic is somewhat functionally overlapping with error detection logic, in some cases the overhead may be abated. Likewise, verified code may avoid certain software implemented runtime tests. The processor itself is generally modified, for example to include hardware signature generation in the cache, hardware for verifying the instruction Sg against the expected signature Se, verification result processing (e.g., the table of verification results, contingent processing logic) and secure storage for the private key (or hardware for receipt of the private key). This amounts to less than about 20% die overhead, with the bulk of the excess consumed in cache line signature generation.


This technology is easy to retrofit to current designs, in feasible implementations would show little performance loss, and can use existing TPM support to implement processor-internal storage for secret keys. The design provides concurrent commencement of instruction execution and verification of code. A processor according to the present invention can result from modification of an existing design, which is compatible with pre-existing code, including well written code which runs in real-time, near real-time, or in time critical fashion. That is, the increased processing to verify the code signature against the expected code signature is, for the most part, an inherently parallel processing path which does not significantly increase processing latency.


A preferred embodiment of the invention employs a set-associative structure called a Cache line Signature Table (CST), to hold the entry for a lowest level cache line that was fetched on a level 1 instruction cache (L1 I-cache) miss. The entry may hold, for example, either the decrypted signature fetched from random access memory (RAM) or the generated signature, whatever is available earlier.


A signature is generated for each line by simply generating a digest function D on smaller chunks of each such line, for example at 16-bit or 32-bit boundaries.


In the event of a verification failure or signature mismatch, a rollback to a previous checkpoint may be implemented. Typically, this will be a desired result if the signatures are used for detecting software errors, or for secure control systems which are relatively intolerant of unavailability. On the other hand, in systems where a continued execution or attempted continuation after a fault is not required, or is undesired, an exception may be triggered, to address the mismatch, or even take countermeasures against a presumed attack. These countermeasures may be directed from code stored within the processor, and thus presumed secure, or from outside, in which case heightened scrutiny may be implemented.


According to one embodiment, a plurality of private keys may be stored within the processor, representing different stages of security. If a “first line” key becomes compromised, the processor may revoke that key, and thereafter employ and rely on a different key, which may have a greater key length or rely on a different algorithm. The presumption of security compromise may come from a certificate revocation list, or behavioral analysis of software with respect to prohibited functionality and/or malicious activity.


In like manner, in some embodiments, it may be possible to add a new certificate to the processor memory, which may exploit a hardware lock (presuming that malicious attacks are by software only), or using an authenticated key transfer technique. Note that if the keys are changed, any signatures created whose verification is dependent on the key will be invalid, and will have to be resupplied or recalculated.


According to one embodiment, the system is responsive to codes, e.g., program instructions or other signals, to deactivate some or all of the security features, and thereby allow exceptions to the normal prohibitions and control mechanisms. Preferably, these codes are provided by the operating system or some other trusted entity, in order to provide authentication of the exception. For example, during normal booting of an operating system, files may be modified, and this exception mechanism permits such modifications. After the operating system has completed these modifications, the security features may be re-enabled. According to another embodiment, multiple alternate authentication mechanisms are provided, which are selectively applied under control of authenticated processes and instructions. Therefore, the system may employ multiple parallel or alternate instruction authentication schemes, and optionally operate for periods without an instruction authentication processes active.


It is therefore an object of the invention to provide a processor comprising: a cache memory, configured to store instructions; an instruction processing pipeline, configured to receive a stored instruction from the cache memory for processing, having a pipeline latency between commencement of instruction processing and commitment of execution of the instruction; a cache memory signature generator, configured to generate a distinctive signature of at least one cache line stored in the cache memory; a memory configured to store an encrypted reference signature corresponding to the at least one cache line stored in the cache memory; a secure storage location configured to store a key adapted to decrypt the encrypted reference signature; decryption logic configured to decrypt the encrypted reference signature in dependence on the stored key; verification logic configured to verify the decrypted reference signature against the generated distinctive signature; and authorization logic configured to selectively permit the instruction processing pipeline to contingently proceed with processing of the instruction to a stage prior to commitment, in dependence on an output of the verification logic, and only if the generated distinctive signature is verified against the reference signature, authorizing commitment of the instruction from the cache line.


It is also an object of the invention to provide a processing method, comprising: receiving a stored instruction from a cache line in a cache memory for processing into an instruction processing pipeline, having a pipeline latency between commencement of instruction processing and commitment of execution of the instruction; generating a distinctive signature of the cache line; storing an encrypted reference signature corresponding to the cache line; securely storing a key adapted to decrypt the encrypted reference signature; decrypting the encrypted reference signature in dependence on the stored key; verifying the decrypted reference signature against the generated distinctive signature; and initiating processing of an instruction, and thereafter selectively permitting the instruction processing pipeline to contingently proceed to a stage prior to commitment, in dependence on the verifying, and only if the generated distinctive signature is verified against the reference signature, authorizing commitment of the instruction from the cache line.


It is a further object of the invention to provide a system and method in which a processor commences processing of an instruction in an instruction processing pipeline and proceeds to a stage before commitment of execution, wherein the commitment of execution is contingent on a verification of a cache line that includes the instruction by a verification process that proceeds concurrently with the instruction processing, in which a unique or distinctive signature is generated for the cache line, and compared against a reference signature which is received by the processor in encrypted form, and decrypted using a secret key stored in the processor, such that the instruction processing proceeds to commitment of execution if and only if the decrypted reference signature matches the generated signature of the cache line. The verification is available for all instructions in the same cache line, reducing potential delays. The processor preferably includes hardware enhancements such that the minimum time to decrypt an encrypted reference signature stored in the cache and verify it against the generated signature is less than the minimum time for commitment of execution of an instruction. Likewise, the cache line signatures are also preferably generated by specially provided hardware in the processor. Thus, if the reference signatures are available in cache memory, a verification latency beyond the normal pipeline processing latency is avoided. If the verification is not available in time, the pipeline may be stalled. If the verification fails, various embodiments provide that the processor may revert to a state defined by a known good checkpoint, or execute a secure exception process.


The cache memory signature generator may generate a distinctive signature of at least one instruction stored in the cache memory during the pipeline latency.


The memory may be configured to store an encrypted reference signature corresponding to the at least one instruction stored in the cache memory, receives the encrypted reference signature before the commitment of the said instruction.


The decryption logic may decrypt the encrypted reference signature during a period prior to at least one of decode, dispatch, or issue of the instruction.


The authorization logic may be configured to selectively permit the instruction processing pipeline to contingently proceed in dependence on an output of the verification logic.


The verification logic may verify the decrypted reference signature against the generated distinctive signature prior to the commitment of the instruction.


An instruction is preferably allowed to commence advancement through the instruction processing pipeline before the generated distinctive signature of a cache line that contained the instruction is verified against a reference signature of the cache line.


An instruction may be advanced through the instruction processing pipeline to a stage immediately prior to at least one of a decoding, a dispatch, and a commitment, and thereafter contingently processed in dependence on the verification logic.


The verification may be optionally disabled, to selectively permit processing of instructions for which the signature does not, or is not expected to, match.


The instruction processing pipeline may be configured to selectively commit execution of an instruction independent of the output of the verification logic, and subject to alternate instruction authentication logic.


The processor may comprise an integrated circuit.


The secure storage location may be on a common integrated circuit with at least the instruction processing pipeline. The secure storage location may also be on a different integrated circuit from at least the decryption logic, the system further comprising logic configured to securely communicate information corresponding to the key to the decryption logic.


The authorization logic may selectively permit the instruction processing pipeline to contingently proceed only if the decrypted reference signature exactly matches the generated distinctive signature.


The authorization logic may selectively control the instruction processing pipeline to provide at least two alternate results in dependence on the verification logic.


A table may be provided, configured to store a plurality of outputs of the verification logic for a plurality of different reference signatures.


The authorization logic may selectively suspend (e.g., stall) processing of an instruction in the instruction pipeline, prior to contingently proceeding, in dependence on an output of the verification logic.


The processor may further comprise decryption logic configured to decrypt instructions stored in the cache memory.


The processor may further comprise: a second memory configured to store a second encrypted reference signature corresponding to at least one second instruction stored in the cache memory; and second verification logic configured to verify a decrypted second encrypted reference signature against a generated distinctive signature of the at least one second instruction stored in the cache memory, wherein the verification logic and the second verification logic are concurrently operative to verify a generated distinctive signature against a reference signature.


The processor may further comprise an interface configured to receive at least the instructions and the encrypted reference signature from a memory external to the processor.


The authorization logic may be configured to initiate processing of an instruction, and to thereafter selectively permit the instruction processing pipeline to contingently proceed in dependence on an output of the verification logic.


The processor may comprise a memory representing a defined state, and wherein in dependence on an output of the verification logic, the processor may assume the defined state, without completing execution of the instruction. That is, if the processing of the instruction does not lead to commitment of execution, the processor may revert to a checkpoint or other state not selectively dependent on the content of the instruction, to thereby block malicious or corrupted instructions from executing or controlling the processor.


If the verification logic indicates a failure of verification of the decrypted reference signature against the generated distinctive signature, the processor may roll back to a predefined checkpoint state. The processor or memory may therefore sequentially store, using hardware or software, a checkpoint or known good (verified) state. This is particularly useful to assist in correction of instruction corruption events. The checkpoint state may be defined by hardware or software logic. In the case of software, preferably the checkpoint state is defined by instruction codes whose execution has been previously verified.


The cache memory signature generator may compute a distinctive digest function of at least a portion of a cache line, a signature in dependence on a cache line virtual address and a cache line content, a distinctive signature in which an incremental change in cache line content results in a non-incremental change in the generated distinctive signature, and/or a distinctive signature in dependence on a memory content and a memory virtual address, wherein generated distinctive signatures for memory locations having identical content at sequential virtual addresses results in an a difficult to predict change in the generated distinctive signature, and wherein the generated distinctive signature has a digital size smaller than a size of the cache line from which it is derived.


The instruction processing pipeline may comprise branch prediction logic and speculative processing logic, wherein the verification logic generates a signal corresponding to a branch misprediction with a rollback to a processor state prior to commencement of processing of an instruction whose verification failed.


The instruction processing pipeline may contingently proceed in dependence on the verifying, and may support an instruction processing pipeline stall if the verifying is delayed.


The decrypting and verifying are preferably capable of completing faster that the pipeline latency.


The verifying may determine an exact match between the generated distinctive signature and the decrypted reference signature. In some cases, a mask may be applied to permit verification of portions of a cache line, while permitting runtime variation or data-dependent instructions to be verified.


The system may also be used to generate execution flow control, in which a plurality of verifications may be employed, and the processor executes in accordance with a respective verification. A plurality of verifications may proceed concurrently. A plurality of verification results may be stored in a table for a plurality of different instructions.


In event of a failure of verification, the instruction processing pipeline may be flushed, and subsequent commitment of execution of the instruction preempted.


The distinctive signature may be a cryptographic digest of the cache line, in which it is statistically unlikely that two different cache lines assume the same signature, and wherein there is low predictability, absent a secret key, on what signature might correspond with a particular cache line content. Thus, a secret key is required to generate the cryptographic digest of the cache line, and a corresponding secret key is required to decrypt the reference signatures for comparison with the generated signatures.


The hardware for implementing the processor enhancements preferably makes use of processor instruction processing pipeline logic found in modern processors, with respect to branch prediction, speculative processing, and pipeline flushing, and thus preferably does not require substantial redesign of existing processor pipelines. On the other hand, in order to avoid, to the extent reasonable, added processing latency, assistive hardware which executes concurrently with the instruction processing pipeline is provided to calculate a cache line signature, decrypt the reference signature, and determine a correspondence thereof. Further supplemental hardware might include a table for storing the verification results, a content associative memory, and fetch logic to call reference signatures as or before needed, possibly in a speculative manner.


It is a further object to provide a processor system comprising a cache line signature generator, configured to generate a dynamic signature for a cache line of an instruction cache; verification logic configured to securely verify a reference signature for a respective cache line content against the dynamic signature; and an instruction processing pipeline having a plurality of sequential stages, configured to load an instruction from the cache line, speculatively execute the instruction in the plurality of stages prior to commitment, and selectively flush the pipeline in dependence on a signal prior to instruction commitment or permit instruction commitment, in dependence on a signal from the verification logic.


It is also an object to provide a processor comprising: an instruction processing pipeline, having at least one pipeline phase between receipt of an instruction for processing and commitment of the instruction, being responsive to at least one control flow instruction; a signature generator, configured to generate a signature of at least one instruction cache line storing at least one instruction; a secure storage location configured to store a key adapted to decrypt an encrypted reference signature for the at least one instruction; verification logic configured to verify a decrypted reference signature against the signature; and authentication logic configured to permit commitment of the at least one instruction, selectively based on a signal from the verification logic.


Another object provides a processing method, comprising: generating a signature of at least one instruction cache line storing at least one instruction; storing a key adapted to decrypt an encrypted reference signature for the at least one instruction; verifying a decrypted reference signature against the signature; and selectively permit commitment of the at least one instruction in an instruction processing pipeline responsive to at least one control flow instruction and having a latency between receipt of an instruction for processing and commitment of the instruction, based on said verification.


The processor may further comprise a cache, having the cache line, configured to store instructions; the instruction processing pipeline being configured to receive a stored instruction from the cache for processing; a memory configured to store the encrypted reference signature corresponding to the at least one cache line stored; and decryption logic configured to decrypt the encrypted reference signature in dependence on the stored key, wherein the authorization logic is configured to selectively permit the instruction processing pipeline to contingently proceed with processing of the at least one instruction to a stage prior to commitment, in dependence on the signal from the verification logic, and only if the generated signature is successfully verified against the reference signature, authorizing commitment of the at least one instruction from the cache line.


The pipeline may have a latency between commencement of instruction processing and commitment of the instruction, and for at least one cache line content, the signature generator generates the signature of the at least one instruction in the cache line, the encrypted reference signature is decrypted, and the decrypted reference signature verified against the signature during the pipeline latency substantially without stalling the pipeline waiting for the signal from the verification logic. Logic may also be provided configured to, if the verification logic fails to communicate a signal indicating permitted commitment of the at least one instruction, generate a fail signal, flush the pipeline of the at least one instruction from the cache line, and prevent the at least one instruction in the pipeline from commitment. An instruction may be advanced through the instruction processing pipeline to a stage immediately prior to at least one of a decoding, a dispatch, and a commitment, and is thereafter contingently at least one of decoded, dispatched and committed, in dependence on the signal. The at least one instruction may have an execution which is dependent on associated data present in the cache line, and the signature is dependent on the at least one instruction but not the data. The authorization logic may selectively control the instruction processing pipeline to provide at least two alternate results of instruction commitment in dependence on the signal.


A table may be provided, configured to store a plurality of outputs of the verification logic for a plurality of different reference signatures.


A second memory may be provided, configured to store a second encrypted reference signature corresponding to at least one second instruction stored in the cache; and second verification logic provided configured to verify a decrypted second encrypted reference signature against a generated signature of the at least one second instruction stored in the cache, wherein the verification logic and the second verification logic are concurrently operative to verify the generated signature against the reference signature and the second generated reference signature against the second reference signature.


The processor may comprises a memory representing a defined state or checkpoint state, and wherein selectively in dependence on the signal indicating a no permission for commitment of the at least one instruction, the processor may assume the defined state or rolls back to the checkpoint state, and does not complete execution of the instruction.


The signature generator preferably computes a distinctive digest function of the cache line. Preferably, the signature generator selectively generates the signature in dependence on at least a cache line virtual address and a cache line content. The signature generator may also produce a signature in which an incremental change in a cache line content results in a non-incremental change in the generated signature. The signature generator may produce a signature in dependence on at least a cache line memory location content and an associated virtual address, wherein generated signatures for memory locations having identical content at sequential virtual addresses are generated by a secret algorithm configured to result in an a difficult to predict change in the generated signature, and wherein the generated signature has a digital size smaller than a size of the cache line from which it is derived.


The instruction processing pipeline may include at least branch prediction logic and speculative processing logic. Advantageously, the effect of a failed verification can be similar to the effect of a branch misprediction or speculative processing failure, that is, the pipeline is flushed without completion of instruction processing, e.g., commitment of the instruction. Thus the signal corresponds to a branch misprediction, the processor being configured to initiate a rollback to a processor state prior to commencement of processing of an instruction whose verification failed.


According to one embodiment, a mode is provided wherein the instruction processing pipeline is configured to selectively commit an instruction independent of the output of the verification logic. That is, the particular security may be bypassed, for example during trusted startup procedures, system upgrades, and/or testing. The instruction processing pipeline may have a mode which selectively permits commitment of an instruction independent of a relation of the decrypted reference signature and the generated signature. Likewise, the instruction processing pipeline may be configured to selectively commit an instruction independent of the output of the verification logic, and subject to alternate instruction authentication logic.


The processor may be further configured to store a state of at least one of the verification logic and the authentication logic in a storage location when a context is switched out, and to restore the state of the at least one of the verification logic and the authentication logic from the storage location when the context is resumed.


According to another embodiment, the change in state effected by an instruction subject to verification may be outside of the instruction processing pipeline. For example, in a memory write operation, the data must be transferred to the memory before changing the state of the memory based on that data. Therefore, if the operation cannot be verified before the instruction which proposes the memory write is ready for commitment in the instruction processing pipeline, the implementation of the authentication processes may be distributed from the processor core, and to memory operation processing logic. Thus, under such circumstances where a substantial, and perhaps disadvantageous permanent change in the system state does not occur formally at the time of commitment of the instruction in the instruction processing pipeline per se, then the signal may be targeted at the external logic rather than the pipeline. This permits fewer stalls in the pipeline, but may impose administrative burdens on extra-processor communications. Thus, the system may be configured to process at least one instruction to compute a proposed change in state of an external memory, and further comprise logic configured to signal a permitted change in the state of external memory selectively based on the signal from the verification logic.


The method may further comprise storing an encrypted reference signature corresponding to the cache line; decrypting the encrypted reference signature in dependence on the stored key; and initiating processing of an instruction from the cache line, and thereafter permitting the instruction processing pipeline to proceed to a stage prior to commitment, and only if the generated distinctive signature is verified against the reference signature, authorizing commitment of the instruction. For at least one cache line content, the generated signature of the at least one instruction may be generated, the encrypted reference signature decrypted, and the decrypted reference signature verified against the signature, during the pipeline latency substantially without stalling the pipeline waiting for the verification. Correspondingly, for at least one cache line content, the instruction processing pipeline may support an instruction processing pipeline stall if the verification is delayed.


The verification may permit commitment of the at least one instruction in the pipeline based on a partial match of the generated signature of the cache line with the decrypted reference signature. For example, a value in the cache line may be dynamically generated or updated during program execution, and the reference signature calculated and/or presented to be independent of the variable data component.


A second encrypted reference signature corresponding to at least one second instruction may be stored in the cache; and a decrypted second encrypted reference signature verified against a generated signature of the at least one second instruction stored in the cache memory, wherein the verifying of the instruction and the verifying of the second instruction proceed concurrently. For example, in a multicore processor, a plurality of pipelines may be present. Likewise, the values in a plurality of cache lines may be verified concurrently, for a single pipeline.


A predefined or checkpoint processor state may be stored in a memory, and the predefined processor state or the processor state rolled back to the prior checkpoint state, preempting completion of execution of the at least one instruction in the instruction processing pipeline, in dependence on a result of said verifying.


The cache line signature may be selectively generated in dependence on a cache line virtual address and a cache line content.


The instruction processing pipeline may comprise branch prediction logic and speculative processing logic, wherein the verifying generates a signal corresponding to a branch misprediction, resulting in a rollback to a state prior to commencement of processing of an instruction whose verification failed. Likewise, other synergies with existing processor technologies may be exploited. For example, the signature and verification process is a type of error detection, and therefore processor logic which implements error detection may be reduced to the extent redundant with the verification of cache line signatures against reference signatures.


The method may provide a mode in which the instruction processing pipeline selectively commits an instruction independent of the verifying. The instruction processing pipeline may selectively commits an instruction independent of the verifying, and subject to alternate instruction authentication.


A state of at least one of the verification logic and the authentication logic may be stored in a storage location when a context is switched out, and the state of the at least one of the verification logic and the authentication logic restored from the storage location when the context is resumed.


The instruction processing pipeline may process at least one instruction to compute a proposed change in state of an external memory, and selectively permit a change in the external memory based on the verification logic. Therefore, in the case of, for example, a memory write, the instruction processing pipeline may be virtually extended to encompass cooperative pipelines which also incur latencies prior to making a substantially persistent change to the system, thus avoiding a stalled pipeline in a microprocessor core.





BRIEF DESCRIPTION OF THE DRAWINGS

For a detailed description of exemplary embodiments of the invention, reference will be made to the accompanying drawings in which:



FIG. 1 illustrates a prior art network with a transmitter and a plurality of receivers;



FIG. 2 illustrates a prior art device;



FIG. 3 illustrates is a block diagram of a processor comprising a signature generator and an instruction pointer trace unit of a prior art device; and



FIG. 4 illustrates a block diagram of an embodiment of the invention.





DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A. Dynamic Authentication of Executions Using Cache Line Signatures


An approach for authenticating program execution dynamically is to detect if the binaries of the executables are compromised during the execution. One way to do this is to detect that the instructions that are fetched and executed, as the program is running, are indeed the same instructions that are supposed to be fetched and executed.


One way to do this is as follows:


The executable code is broken down into contiguous chunks at the boundaries of the cache lines (say, of size L) at the lowermost on-chip cache level. If necessary, padding can be used at the end of the code to round its size up to a multiple of the cache line size at the lowest level cache. A signature is generated for each such line by simply generating a digest function D on smaller chunks of each such line, for example at 16-bit or 32-bit boundaries. Thus, for each lowest level cache line's worth of code (say, Li), a specific signature (say Si, where Si=D (Li)) is generated for that line.


The signature Si for each line Li of the program's authentic binary is then encoded using a secret key and stored in a separate array. This secret key can be stored within the TPM storage or, alternatively, a secure storage for such keys can be constructed using the TPM module (which provides the root of trust).


As the program execution is started, on-chip cache misses are triggered in the course of fetching instructions. As each line holding the instruction that triggered the L1 I-cache miss is fetched into the lowest level cache, the corresponding encrypted signature is also retrieved. A digest for the line fetched, say Lf, is then generated by applying the digest function, D, that is Sf=D(Lf) is computed.


The encrypted signature of Lf is then decoded and compared with the computed signature Sf. If the decrypted signature matches Sf, then we conclude that the original binaries were not tampered with, and are thus deemed verified. If the computed signature and decrypted signatures mismatch, an exception can be triggered or actions similar to that taken with the control flow validation mechanism can be triggered. In reality, as described in the implementation details below, the validation of the contents of a line will be deferred until an instruction located within that line commits.


A.1 Assumptions


The security of this mechanism for authenticating a program execution at run-time makes the following implicit assumptions:


1. Once an instruction is fetched, it cannot be modified or replaced within the processor's caches.


2. The digest function D is sufficiently strong in generating a fairly unique signature for each lowest level cache line. Put in other words, two different cache lines, containing two different sets of instructions cannot accidentally have the same signature except in rare circumstances, and preferably in a highly unpredictable manner. One way to do this is to combine the line's virtual address with the cache line's contents in deriving the unique signature for that cache line, while taking into account the predictability of the cache line address—such as consecutive line addresses differ by one, higher order bits in a line address are going to be similar or close, etc.


3. If the contents of the cache lines are unaltered, control flow proceeds on expected paths.


4. There is a secure mechanism for storing the key used for decrypting the cache line signatures. The various existing TPM infrastructures provide this ability.


The performance overhead of the present mechanism is dependent on a number of things. First, hardware support is needed to compute the signature of a lowest level cache line as it is fetched. Using a simple one-time pad, where the one time key is XORed with the encrypted signature to decrypt it, can be a very efficient solution but the mechanism is open to all the vagaries of using a one-time pad. Alternative mechanisms, albeit with a higher overhead, can be employed. Any delay in decrypting the signatures can be avoided by fetching the signatures of a number of consecutive lower-level lines into the processor and decrypting them in advance, for example using a cryptographic or authentication coprocessor separate from the normal instruction processing flow of the main processor, but which may be integrated on the same chip. Second, the signatures have to be stored in a manner that permits them to be fetched quickly as the cache lines themselves are being fetched.


We now describe implementation details that takes into account the delays in both generating a signature from a line fetched into the lowest level cache as well as the delay involved in decrypting a precomputed encrypted signature for the cache line.


A.2 Implementation


Assume that the lowest level cache line size is B bytes and the digest to be computed over Q byte chunks of each such line, where B is an integer multiple of Q and the digest of a line is also Q bytes long. Assume further that the executable module is N bytes long, starting at virtual address A and, for the sake of simplicity, that N is an integer multiple of B. The number of encrypted digests that we need to store for the executable is thus M=(N/B)*Q. Assume that these encrypted digests are stored contiguously in the order of the line addresses, starting at virtual memory address Z. The virtual address of the encrypted digest for the memory line with the address X that is fetched into the lower level cache on a L1 I-cache miss is: a=((X−A)/B)*Q+Z. Thus, given the address of a line, the address of its encoded digest can be easily located.


The cache based dynamic authentication mechanism is implemented as shown in FIG. 4. The implementation takes into account two constraints. First, it takes into account the fact that the both the generation of the signature of the fetched cache line and the decryption of the stored signature for comparison against the decrypted signature are potentially slow operations that take multiple pipeline cycles. Second, the signature of the line being fetched into the lowest level cache cannot be generated or generated and verified before that line is inserted into the cache and delivered to the fetch stage, as the time it takes to generate the signature or to fetch the encrypted signature from the signature table stored in the RAM and decrypt it for comparison against the signature generated of the fetched cache line will prolong the effective cache miss handling time and adversely impact the instruction fetch and decode rate.


According to an embodiment of the present technology, a set-associative structure called the Cache line Signature Table (CST) is used to hold the entry for a lowest level cache line that was fetched on an L1 I-cache miss. This entry holds either the decrypted signature fetched from the RAM or the generated signature, whatever is available earlier. Additionally, this entry holds status information that indicates:


(a) the status of the entry—allocated or de-allocated;


(b) what is currently held in the entry—a generated signature or a decrypted signature;


(c) if the stored entity is a generated signature (or a decrypted signature) was compared against the decrypted signature (or a generated signature); and


(d) the outcome of a match comparing the generated signature against a stored signature.


These four states can be easily encoded using 2 bits. If the generated signature or the stored signatures are S bits long, each entry in the signature table is (S+2) bits wide.


When either a generated signature or a decrypted signature arrives at the CST, and if the other entity being compared (the decrypted signature or the generated signature, respectively) is not available in the CST entry (as seen from the status bits), the first entity targeting the CST entry is simply stored within the CST and the status bits updated appropriately. Otherwise, the comparison of the decrypted and generated signatures can be performed, and the result of the match stored in the status field.


When an instruction is being committed, the signature table is probed to look for a matching entry. If a matching entry is found (CST hit), the instruction is committed as usual only if the matching entry indicates that the comparison of the decrypted signature and the stored signature was successful. If the signature comparison was performed and the generated signature did not match the decrypted signature, an exception is generated and the instruction is not committed. For all other conditions on a CST hit, the instruction commitment is held up, and this may result in a stall elsewhere in the pipeline. If at the time of committing an instruction, a CST miss occurred, the pipeline is flushed, treating the instruction being committed as a mispredicted branch. This is done to ensure that instructions from a lowest level cache whose signature may have been potentially unverified cannot be committed.


Two additional pipeline stages (labeled A1 and A2) are added at the tail end of the pipeline, following the last pipeline stage that handles commitment (labeled C) to handle the CST lookup and associated activities described above. The normal commitment is delayed until the instructions are exiting from A2. Additional stages may be added if the CST lookup and activities require more than two cycles. These added stages, obviously, do not affect the instruction pipeline commitment stage in any way as they follow the stages that would perform commitment in a normal pipeline. On a miss at the lowest on-chip cache level that was triggered by a L1 I-cache miss, the missing line is fetched and handled as usual to satisfy the L1 I-cache miss.


The following actions are then undertaken simultaneously:


The signature table is probed to locate any matching entry in the table. If a matching entry is not found, it is allocated and initialized and pinned down until either the generated signature or the decrypted signature is written to the CST entry. Note that in the worst case, if an entry cannot be allocated in the CST on a lowest level cache miss, because all the ways in the matching set within the CST are pinned, the cache miss handling stalls. If a matching entry is found, three cases arise: if the matching entry indicates that a match was performed and it resulted in a mismatch, the entry is left untouched. This is done to ensure that uncommitted instructions from the cache line will trigger an exception at the time of commitment. If the CST entry indicates that a match occurred, it is marked as a pending match to ensure that instructions from the version of the lowest level cache line that will now be fetched are also authenticated properly. If the matching entry in the CST indicates a pending match, no further actions are taken until the missing cache line is fetched. At that time, the CST is probed again and if the CST entry is still found as match pending, instruction dispatching is stalled until the pipeline drains. After the pipeline has drained, the CST entry is completely reset and instruction issue resumes with other activities that corresponded to a CST miss. The pipeline draining step assures that that the proposed authentication scheme detects if the newly fetched version of the cache line was altered since it was last fetched and used. Another obvious way of altogether avoiding this corner case is to flush matching entries in the CST when corresponding lines are evicted from the lowest level cache, but this approach requires additional probes of the CST and takes a performance toll.


On setting up a new CST entry (or after marking an existing CST entry as match pending), the signature of the fetched cache line is generated immediately after fetching the line.


A memory request to fetch the encrypted signature is generated. In general, memory requests for handling cache misses take a precedence over memory requests for fetching encrypted signatures, but queued up memory requests for fetching encrypted signatures are given precedence over normal memory requests periodically to avoid livelocks.


A.3 Extensions


A.3.1 Signature Generation, Etc.:


The size of the signature, the generating function, etc. can be programmable. These can be generated by a trusted authority and appropriate header extensions can be added to the binary of the executed code to:


(a) convey location of encoded signature table;


(b) DLLs and their secret key (see below),


(c) other relevant info (will spell this out later).


A.3.2 Handling Dynamically Linked Libraries:


Each library has its own signature and perhaps a separate secret key for decoding. As a control flow occurs, information is provided to the code (or through the hardware) to locate the dedicated secret key for the library. This mechanism could also be implemented as a software trap on attempts to branch to DLLs.


A.3.3 Handling Computed Branches


The handling of computer branches works the generally same way as DLLs or branching within the same module. The signature of cache lines that contain the executed instructions can be verified.


Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that achieve the same purpose, structure, or function may be substituted for the specific embodiments shown. This application is intended to cover any adaptations or variations of the example embodiments of the invention described herein. It is intended that this invention be limited only by the claims, and the full scope of equivalents thereof.


REFERENCES (INCORPORATED HEREIN BY REFERENCE)



  • [1] SETI@home. setiathome.ssl.berkeley.edu/.

  • [2] TCPA. www.trustedcomputing.org/.

  • [3] A. Carroll, M. Juarez, J. Polk, and T. Leininger. Microsoft Palladium: A business overview, August 2002. Microsoft Press Release.

  • [4] B. Gassend, D. Clarke, M. Van Dijk, and S. Devadas. Controlled physical random functions. In Proceedings of the 18th Annual Computer Security Applications Conference, December 2002.

  • [5] D. Lie, C. A. Thekkath, M. Mitchell, P. Lincoln, D. Boneh, J. C. Mitchell, and M. Horowitz. Architectural support for copy and tamper resistant software. In Proceedings of Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 168-177, 2000.

  • [6] U. Maheshwari, R. Vingralek, and W. Shapiro. How to build a trusted database system on untrusted storage. In Proceedings of the 4th USENIX Symposium on Operating Systems Design and Implementation, pages 135-150, October 2000.

  • [7] S. W. Smith and S. H. Weingart. Building a high performance, programmable secure coprocessor. In Computer Networks (Special Issue on Computer Network Security), volume 31, pages 831-860, April 1999.

  • [8] E. Suh, D. Clarke, B. Gassend, M. van Dijk, and S. Devadas. The AEGIS processor architecture for tamper evident and tamper resistant processing. Technical Report LCS-TM-461, Massachusetts Institute of Technology, February 2003.

  • [9] E. Suh, D. Clarke, B. Gassend, M. van Dijk, and S. Devadas. Hardware mechanisms for memory authentication. Technical Report LCS-TM-460, Massachusetts Institute of Technology, February 2003.

  • [10] S. Weingart. Physical security for the μABYSS system. In Proceedings of the IEEE Computer Society Conference on Security and Privacy, pages 38-51, 1987.

  • [11] S. White, S. Weingart, W. Arnold, and E. Palmer. Introduction to the Citadel architecture: security in physically exposed environments. Technical Report RC16672, IBM Thomas J. Watson Research Center, March 1991.

  • [12] B. Yee. Using secure coprocessors. PhD thesis, Carnegie Mellon University, May 1994.


Claims
  • 1. A microprocessor comprising: a multistage instruction processing pipeline, comprising at least one of branch prediction logic elements and speculative execution logic elements, and having a minimum pipeline latency between receipt of a first instruction of a sequence of instructions and readiness for commitment of execution of the first instruction, configured to: receive a sequence of instructions for processing,concurrently decode the received instructions during the pipeline latency,dispatch the instructions,advance respective instructions of the sequence of instructions to a stage prior to commitment of instruction execution,commit execution of the sequence of instructions to produce at least one execution result comprising alteration of at least one register of the microprocessor external to the instruction processing pipeline in response to execution of at least one instruction and an availability of a verification signal, andrespond to at least one of a misprediction signal and failure of availability of the verification signal, to cause a rollback of the instruction processing pipeline to a state prior to an error which caused the at least one of the misprediction signal and the failure of availability of the verification signal;a memory configured to store at least a predetermined encrypted reference digital signature;decryption logic elements configured to decrypt the encrypted reference digital signature in dependence on a decryption key securely stored in, and received from a secure hardware environment to produce a reference digital signature corresponding to an expected digital signature of an authentic sequence of instructions;verification logic elements configured to match the reference digital signature with a digital signature of the received sequence of instructions; andauthorization logic elements configured, within a first mode of operation, to generate the verification signal within the minimum pipeline latency, contingent upon verifying that the reference digital signature matches the digital signature.
  • 2. The microprocessor according to claim 1, further comprising a cache memory signature generator configured to receive the sequence of instructions from a cache memory, and to calculate the digital signature of the received sequence of instructions from a line of the cache memory before receipt of the sequence of instructions by the instruction processing pipeline.
  • 3. The microprocessor according to claim 2, wherein the cache memory is within the microprocessor.
  • 4. The microprocessor according to claim 1, further comprising a memory from which the predetermined encrypted reference digital signature is fetched together with an associated sequence of instructions from a memory.
  • 5. The microprocessor according to claim 1, wherein the secure hardware environment comprises a trusted platform module.
  • 6. The microprocessor according to claim 1, wherein the microprocessor has a second mode of operation in which the verification signal is generated independent of the authorization logic elements.
  • 7. The microprocessor according to claim 1, wherein the decryption logic elements are further configured to decrypt the encrypted reference signature associated with a respective instruction during a period prior to dispatch of the respective instruction.
  • 8. The microprocessor according to claim 1, wherein the authorization logic elements are further configured to permit the instruction processing pipeline to contingently proceed only if the reference digital signature matches the digital signature.
  • 9. The microprocessor according to claim 1, further comprising a table stored in a memory configured to store a plurality of outputs of the verification logic elements corresponding to a plurality of respective reference digital signatures.
  • 10. The microprocessor according to claim 1, wherein the instruction processing pipeline is further configured to suspend processing of a respective instruction of the sequence of instructions until receipt of the verification signal.
  • 11. The microprocessor according to claim 1, further comprising: an interface to a memory storing a checkpoint state representing a predetermined verified state; andcheckpoint logic configured to cause the microprocessor to assume the checkpoint state upon failure of the verification authorization signal.
  • 12. The microprocessor according to claim 1, further comprising: an interface to a memory storing a checkpoint state representing a prior verified state; andcheckpoint logic configured to cause the microprocessor to roll back to the checkpoint state if the selective generation of the authorization upon failure of the verification signal.
  • 13. A method for verifying instructions executed by a microprocessor, comprising: receiving a sequence of instructions for processing by a multistage instruction processing pipeline having a minimum pipeline latency between receiving a first instruction of the sequence of instructions and readiness to commit execution of the first instruction, and comprising at least one of branch prediction logic elements and speculative execution logic elements responsive to at least one of a misprediction signal and failure of an availability of a verification signal to cause a rollback of the multistage instruction processing pipeline to a state prior to an error which caused the at least one of the misprediction signal and the failure of availability of the verification signal;concurrently decoding, and dispatching a plurality of the sequence of instructions to a stage prior to commitment of instruction execution during the pipeline latency;committing execution of the sequence of instructions to produce at least one execution result comprising alteration of at least one register of the microprocessor external to the instruction processing pipeline, in response to execution of at least one instruction and the availability of the verification signal;storing at least a predetermined encrypted reference digital signature in a memory;decrypting the encrypted reference signature in dependence on a securely received decryption key in a secure hardware environment, to produce a reference digital signature corresponding to an expected digital signature of an authentic sequence of instructions; andverifying that the reference digital signature matches a digital signature of the received sequence of instructions and generating the verification signal, contingent upon verifying that the reference digital signature matches the digital signature, in a secure hardware environment that generates the verification signal within the minimum pipeline latency.
  • 14. The method according to claim 13, further comprising: receiving the sequence of instructions from a cache memory; andcalculating the digital signature of the received sequence of instructions from a line of the cache memory by a cache memory signature generator.
  • 15. The microprocessor according to claim 1, wherein the digital signature of the received sequence of instructions is calculated from the cache memory line by a cache memory signature generator during execution of the sequence of instructions by the instruction processing pipeline.
  • 16. The microprocessor according to claim 1, wherein a plurality of predetermined encrypted reference digital signatures are fetched together in advance of associated sequences of instructions from a memory.
  • 17. The microprocessor according to claim 1, further comprising a cache line signature table, configured to store an entry representing the earlier available of the generated signature of the received sequence of instructions and the reference digital signature.
  • 18. The microprocessor according to claim 17, wherein the entry further comprises: (a) an allocation status of the entry;(b) a type of entry status, selected from the group consisting of the generated signature of the received sequence of instructions and the reference digital signature;(c) a matching status of whether the generated signature of the received sequence of instructions has been matched to the reference digital signature; and(d) a verification outcome status of the match of the generated signature of the received sequence of instructions and the reference digital signature.
  • 19. The microprocessor according to claim 1, further comprising a signature generator configured to generate the digital signature of the received sequence of instructions.
  • 20. The microprocessor according to claim 19, wherein the received sequence of instructions are accompanied by the encrypted reference digital signature, which are concurrently fed to the multistage instruction processing pipeline, the decryption logic elements, and the signature generator.
CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a Continuation of U.S. patent application Ser. No. 14/330,441, filed Jul. 14, 2014, issued Dec. 29, 2015 as U.S. Pat. No. 9,223,967, which is a Continuation of U.S. patent application Ser. No. 13/183,857, filed Jul. 15, 2011, issued Jul. 15, 2014 as U.S. Pat. No. 8,782,434, which is a non-provisional application of, and claims benefit of priority from, U.S. Provisional Patent Application Ser. No. 61/364,795, filed Jul. 15, 2010, the entirety of which are expressly incorporated herein by reference in their entirety.

US Referenced Citations (2456)
Number Name Date Kind
4247892 Lawrence Jan 1981 A
4514846 Federico et al. Apr 1985 A
4584639 Hardy Apr 1986 A
4625081 Lotito et al. Nov 1986 A
4665520 Strom et al. May 1987 A
4674038 Brelsford et al. Jun 1987 A
4916605 Beardsley et al. Apr 1990 A
4987532 Noguchi Jan 1991 A
5165031 Pruul et al. Nov 1992 A
5170340 Prokop et al. Dec 1992 A
5175679 Allen et al. Dec 1992 A
5179702 Spix et al. Jan 1993 A
5191651 Halim et al. Mar 1993 A
5222217 Blount et al. Jun 1993 A
5237684 Record et al. Aug 1993 A
5261089 Coleman et al. Nov 1993 A
5276876 Coleman et al. Jan 1994 A
5305056 Salgado et al. Apr 1994 A
5305454 Record et al. Apr 1994 A
5319773 Britton et al. Jun 1994 A
5319774 Ainsworth et al. Jun 1994 A
5327532 Ainsworth et al. Jul 1994 A
5347632 Filepp et al. Sep 1994 A
5355484 Record et al. Oct 1994 A
5363505 Maslak et al. Nov 1994 A
5410684 Ainsworth et al. Apr 1995 A
5410700 Fecteau et al. Apr 1995 A
5421012 Khoyi et al. May 1995 A
5446904 Belt et al. Aug 1995 A
5530868 Record et al. Jun 1996 A
5551033 Foster et al. Aug 1996 A
5592670 Pletcher Jan 1997 A
5606668 Shwed Feb 1997 A
5608720 Biegel et al. Mar 1997 A
5613060 Britton et al. Mar 1997 A
5625821 Record et al. Apr 1997 A
5758072 Filepp et al. May 1998 A
5765004 Foster et al. Jun 1998 A
5822564 Chilton et al. Oct 1998 A
5903766 Walker et al. May 1999 A
5905855 Klaiber et al. May 1999 A
5944821 Angelo Aug 1999 A
6016500 Waldo et al. Jan 2000 A
6070239 McManis May 2000 A
6075938 Bugnion et al. Jun 2000 A
6094528 Jordan Jul 2000 A
6112304 Clawson Aug 2000 A
6115712 Islam et al. Sep 2000 A
6178504 Fieres et al. Jan 2001 B1
6186677 Angel et al. Feb 2001 B1
6195676 Spix et al. Feb 2001 B1
6199100 Filepp et al. Mar 2001 B1
6199198 Graham Mar 2001 B1
6217165 Silverbrook Apr 2001 B1
6223293 Foster et al. Apr 2001 B1
6233565 Lewis et al. May 2001 B1
6243716 Waldo et al. Jun 2001 B1
6247027 Chaudhry et al. Jun 2001 B1
6275852 Filepp et al. Aug 2001 B1
6289382 Bowman-Amuah Sep 2001 B1
6301673 Foster et al. Oct 2001 B1
6304915 Nguyen et al. Oct 2001 B1
6315200 Silverbrook et al. Nov 2001 B1
6317192 Silverbrook et al. Nov 2001 B1
6317438 Trebes, Jr. Nov 2001 B1
6321366 Tseng et al. Nov 2001 B1
6332163 Bowman-Amuah Dec 2001 B1
6339832 Bowman-Amuah Jan 2002 B1
6353881 Chaudhry et al. Mar 2002 B1
6356715 Silverbrook Mar 2002 B1
6360193 Stoyen Mar 2002 B1
6362868 Silverbrook Mar 2002 B1
6362869 Silverbrook Mar 2002 B1
6378068 Foster et al. Apr 2002 B1
6397379 Yates, Jr. et al. May 2002 B1
6415054 Silverbrook et al. Jul 2002 B1
6416154 Silverbrook Jul 2002 B1
6421739 Holiday Jul 2002 B1
6430570 Judge et al. Aug 2002 B1
6430649 Chaudhry et al. Aug 2002 B1
6431669 Silverbrook Aug 2002 B1
6434568 Bowman-Amuah Aug 2002 B1
6434628 Bowman-Amuah Aug 2002 B1
6438594 Bowman-Amuah Aug 2002 B1
6438677 Chaudhry et al. Aug 2002 B1
6442525 Silverbrook et al. Aug 2002 B1
6442663 Sun et al. Aug 2002 B1
6442748 Bowman-Amuah Aug 2002 B1
6453463 Chaudhry et al. Sep 2002 B1
6459495 Silverbrook Oct 2002 B1
6460067 Chaudhry et al. Oct 2002 B1
6463457 Armentrout et al. Oct 2002 B1
6463526 Chaudhry et al. Oct 2002 B1
6463582 Lethin et al. Oct 2002 B1
6476863 Silverbrook Nov 2002 B1
6477580 Bowman-Amuah Nov 2002 B1
6477665 Bowman-Amuah Nov 2002 B1
6493730 Lewis et al. Dec 2002 B1
6496850 Bowman-Amuah Dec 2002 B1
6502102 Haswell et al. Dec 2002 B1
6502135 Munger et al. Dec 2002 B1
6502213 Bowman-Amuah Dec 2002 B1
6510352 Badavas et al. Jan 2003 B1
6523027 Underwood Feb 2003 B1
6523059 Schmidt Feb 2003 B1
6529909 Bowman-Amuah Mar 2003 B1
6529948 Bowman-Amuah Mar 2003 B1
6539396 Bowman-Amuah Mar 2003 B1
6542645 Silverbrook et al. Apr 2003 B1
6546397 Rempell Apr 2003 B1
6547364 Silverbrook Apr 2003 B2
6549949 Bowman-Amuah Apr 2003 B1
6549959 Yates et al. Apr 2003 B1
6550057 Bowman-Amuah Apr 2003 B1
6565181 Silverbrook May 2003 B2
6571282 Bowman-Amuah May 2003 B1
6578068 Bowman-Amuah Jun 2003 B1
6601192 Bowman-Amuah Jul 2003 B1
6601233 Underwood Jul 2003 B1
6601234 Bowman-Amuah Jul 2003 B1
6606660 Bowman-Amuah Aug 2003 B1
6606744 Mikurak Aug 2003 B1
6609128 Underwood Aug 2003 B1
6615199 Bowman-Amuah Sep 2003 B1
6615253 Bowman-Amuah Sep 2003 B1
6618117 Silverbrook Sep 2003 B2
6618761 Munger et al. Sep 2003 B2
6625751 Starovic et al. Sep 2003 B1
6633878 Underwood Oct 2003 B1
6636216 Silverbrook et al. Oct 2003 B1
6636242 Bowman-Amuah Oct 2003 B2
6640238 Bowman-Amuah Oct 2003 B1
6640244 Bowman-Amuah Oct 2003 B1
6640249 Bowman-Amuah Oct 2003 B1
6643650 Slaughter et al. Nov 2003 B1
6644771 Silverbrook Nov 2003 B1
6658451 Chaudhry et al. Dec 2003 B1
6665454 Silverbrook et al. Dec 2003 B1
6671818 Mikurak Dec 2003 B1
6674769 Viswanath Jan 2004 B1
6684398 Chaudhry et al. Jan 2004 B2
6691250 Chandiramani et al. Feb 2004 B1
6701514 Haswell et al. Mar 2004 B1
6702417 Silverbrook Mar 2004 B2
6704862 Chaudhry et al. Mar 2004 B1
6704871 Kaplan et al. Mar 2004 B1
6704873 Underwood Mar 2004 B1
6708273 Ober et al. Mar 2004 B1
6715145 Bowman-Amuah Mar 2004 B1
6718438 Lewis et al. Apr 2004 B2
6718486 Roselli et al. Apr 2004 B1
6718535 Underwood Apr 2004 B1
6718538 Mathiske Apr 2004 B1
6721944 Chaudhry et al. Apr 2004 B2
6732363 Chaudhry et al. May 2004 B1
6742015 Bowman-Amuah May 2004 B1
6742123 Foote May 2004 B1
6750901 Silverbrook Jun 2004 B1
6750944 Silverbrook et al. Jun 2004 B2
6754855 Denninghoff et al. Jun 2004 B1
6760736 Waldo et al. Jul 2004 B2
6760815 Traversat et al. Jul 2004 B1
6760825 Sexton et al. Jul 2004 B1
6763440 Traversat et al. Jul 2004 B1
6763452 Hohensee et al. Jul 2004 B1
6772296 Mathiske Aug 2004 B1
6779107 Yates Aug 2004 B1
6786420 Silverbrook Sep 2004 B1
6788336 Silverbrook Sep 2004 B1
6788688 Trebes, Jr. Sep 2004 B2
6788980 Johnson Sep 2004 B1
6789077 Slaughter et al. Sep 2004 B1
6789126 Saulpaugh et al. Sep 2004 B1
6789181 Yates et al. Sep 2004 B1
6792466 Saulpaugh et al. Sep 2004 B1
6795966 Lim et al. Sep 2004 B1
6803989 Silverbrook Oct 2004 B2
6826616 Larson et al. Nov 2004 B2
6826748 Hohensee et al. Nov 2004 B1
6831681 Silverbrook Dec 2004 B1
6832367 Choi et al. Dec 2004 B1
6834310 Munger et al. Dec 2004 B2
6837427 Overhultz et al. Jan 2005 B2
6839759 Larson et al. Jan 2005 B2
6842906 Bowman-Amuah Jan 2005 B1
6850274 Silverbrook et al. Feb 2005 B1
6850979 Saulpaugh et al. Feb 2005 B1
6854115 Traversat et al. Feb 2005 B1
6857719 Silverbrook Feb 2005 B2
6862594 Saulpaugh et al. Mar 2005 B1
6865657 Traversat et al. Mar 2005 B1
6868447 Slaughter et al. Mar 2005 B1
6874066 Traversat et al. Mar 2005 B2
6879341 Silverbrook Apr 2005 B1
6895460 Desoli et al. May 2005 B2
6898618 Slaughter et al. May 2005 B1
6898791 Chandy et al. May 2005 B1
6907473 Schmidt et al. Jun 2005 B2
6907546 Haswell et al. Jun 2005 B1
6912708 Wallman et al. Jun 2005 B2
6917976 Slaughter et al. Jul 2005 B1
6918084 Slaughter et al. Jul 2005 B1
6918542 Silverbrook et al. Jul 2005 B2
6934755 Saulpaugh et al. Aug 2005 B1
6934832 Van Dyke et al. Aug 2005 B1
6938130 Jacobson et al. Aug 2005 B2
6938164 England et al. Aug 2005 B1
6941410 Traversat et al. Sep 2005 B1
6941545 Reese et al. Sep 2005 B1
6948661 Silverbrook et al. Sep 2005 B2
6950875 Slaughter et al. Sep 2005 B1
6953235 Silverbrook Oct 2005 B2
6954254 Silverbrook Oct 2005 B2
6954923 Yates, Jr. et al. Oct 2005 B1
6957237 Traversat et al. Oct 2005 B1
6970869 Slaughter et al. Nov 2005 B1
6973493 Slaughter et al. Dec 2005 B1
6973646 Bordawekar et al. Dec 2005 B1
6978462 Adler et al. Dec 2005 B1
6986052 Mittal Jan 2006 B1
6986562 Silverbrook Jan 2006 B2
6988025 Ransom et al. Jan 2006 B2
6990395 Ransom et al. Jan 2006 B2
7003770 Pang et al. Feb 2006 B1
7007852 Silverbrook et al. Mar 2006 B2
7010573 Saulpaugh et al. Mar 2006 B1
7013456 Van Dyke et al. Mar 2006 B1
7016966 Saulpaugh et al. Mar 2006 B1
7020532 Johnson et al. Mar 2006 B2
7020697 Goodman et al. Mar 2006 B1
7021535 Overhultz et al. Apr 2006 B2
7028306 Boloker et al. Apr 2006 B2
7044589 Silverbrook May 2006 B2
7047394 Van Dyke et al. May 2006 B1
7050143 Silverbrook et al. May 2006 B1
7051192 Chaudhry et al. May 2006 B2
7052103 Silverbrook May 2006 B2
7055927 Silverbrook Jun 2006 B2
7065549 Sun et al. Jun 2006 B2
7065574 Saulpaugh et al. Jun 2006 B1
7065633 Yates, Jr. et al. Jun 2006 B1
7069421 Yates, Jr. et al. Jun 2006 B1
7072967 Saulpaugh et al. Jul 2006 B1
7073713 Silverbrook et al. Jul 2006 B2
7080078 Slaughter et al. Jul 2006 B1
7083108 Silverbrook et al. Aug 2006 B2
7084951 Silverbrook Aug 2006 B2
7089374 Tremblay et al. Aug 2006 B2
7092011 Silverbrook et al. Aug 2006 B2
7093004 Bernardin et al. Aug 2006 B2
7093086 van Rietschote Aug 2006 B1
7093989 Walmsley et al. Aug 2006 B2
7096137 Shipton et al. Aug 2006 B2
7097104 Silverbrook et al. Aug 2006 B2
7100195 Underwood Aug 2006 B1
7100834 Silverbrook et al. Sep 2006 B2
7110139 Silverbrook Sep 2006 B2
7111290 Yates, Jr. et al. Sep 2006 B1
7119836 Silverbrook Oct 2006 B2
7121639 Plunkett Oct 2006 B2
7124101 Mikurak Oct 2006 B1
7128386 Silverbrook Oct 2006 B2
7130807 Mikurak Oct 2006 B1
7131026 Denninghoff et al. Oct 2006 B2
7137016 Nalawadi et al. Nov 2006 B2
7137110 Reese et al. Nov 2006 B1
7140726 Silverbrook Nov 2006 B2
7146305 van der Made Dec 2006 B2
7152939 Silverbrook Dec 2006 B2
7152942 Walmsley et al. Dec 2006 B2
7155395 Silverbrook Dec 2006 B2
7159211 Jalan et al. Jan 2007 B2
7163273 Silverbrook Jan 2007 B2
7163345 Walmsley et al. Jan 2007 B2
7165824 Walmsley et al. Jan 2007 B2
7168076 Chaudhry et al. Jan 2007 B2
7171323 Shipton et al. Jan 2007 B2
7181572 Walmsley Feb 2007 B2
7181613 Boebert et al. Feb 2007 B2
7185319 Kaler et al. Feb 2007 B2
7185323 Nair et al. Feb 2007 B2
7187404 Silverbrook et al. Mar 2007 B2
7188180 Larson et al. Mar 2007 B2
7188251 Slaughter et al. Mar 2007 B1
7188282 Walmsley Mar 2007 B2
7188928 Walmsley et al. Mar 2007 B2
7191440 Cota-Robles et al. Mar 2007 B2
7191441 Abbott et al. Mar 2007 B2
7193482 Silverbrook Mar 2007 B2
7200705 Santos et al. Apr 2007 B2
7200848 Slaughter et al. Apr 2007 B1
7201319 Silverbrook et al. Apr 2007 B2
7203477 Coppinger et al. Apr 2007 B2
7203485 Coppinger et al. Apr 2007 B2
7206805 McLaughlin, Jr. Apr 2007 B1
7206903 Moir et al. Apr 2007 B1
7213047 Yeager et May 2007 B2
7213246 van Rietschote et al. May 2007 B1
7228404 Patel et al. Jun 2007 B1
7233421 Silverbrook Jun 2007 B2
7234076 Daynes et al. Jun 2007 B2
7234645 Silverbrook et al. Jun 2007 B2
7234801 Silverbrook Jun 2007 B2
7237140 Nakamura et al. Jun 2007 B2
7243193 Walmsley Jul 2007 B2
7243267 Klemm et al. Jul 2007 B2
7243356 Saulpaugh et al. Jul 2007 B1
7249280 Lamport et al. Jul 2007 B2
7252353 Silverbrook et al. Aug 2007 B2
7254390 Coppinger et al. Aug 2007 B2
7254608 Yeager et al. Aug 2007 B2
7254806 Yates, Jr. et al. Aug 2007 B1
7255414 Silverbrook Aug 2007 B2
7260543 Saulpaugh et al. Aug 2007 B1
7266661 Walmsley Sep 2007 B2
7267417 Silverbrook et al. Sep 2007 B2
7269693 Tremblay et al. Sep 2007 B2
7269694 Tremblay et al. Sep 2007 B2
7275183 Santos et al. Sep 2007 B2
7275246 Yates, Jr. et al. Sep 2007 B1
7275800 Silverbrook Oct 2007 B2
7275805 Jackson Pulver et al. Oct 2007 B2
7278034 Shipton Oct 2007 B2
7278697 Plunkett Oct 2007 B2
7278723 Silverbrook Oct 2007 B2
7281330 Silverbrook et al. Oct 2007 B2
7281777 Silverbrook et al. Oct 2007 B2
7281786 Silverbrook Oct 2007 B2
7283162 Silverbrook et al. Oct 2007 B2
7286815 Coppinger et al. Oct 2007 B2
7287702 Silverbrook et al. Oct 2007 B2
7289142 Silverbrook Oct 2007 B2
7289156 Silverbrook et al. Oct 2007 B2
7289964 Bowman-Amuah Oct 2007 B1
7290852 Jackson Pulver et al. Nov 2007 B2
7293267 Fresko Nov 2007 B1
7302592 Shipton et al. Nov 2007 B2
7302609 Matena et al. Nov 2007 B2
7307526 Rajapakse et al. Dec 2007 B2
7311257 Silverbrook Dec 2007 B2
7312845 Silverbrook Dec 2007 B2
7314261 Jackson Pulver et al. Jan 2008 B2
7320142 Kasper et al. Jan 2008 B1
7325897 Silverbrook Feb 2008 B2
7328195 Willis Feb 2008 B2
7328243 Yeager et al. Feb 2008 B2
7328956 Silverbrook et al. Feb 2008 B2
7330844 Stoyen Feb 2008 B2
7334154 Lorch et al. Feb 2008 B2
7337291 Abadi et al. Feb 2008 B2
7356679 Le et al. Apr 2008 B1
7362971 Silverbrook et al. Apr 2008 B2
7363288 Santos et al. Apr 2008 B2
7366880 Chaudhry et al. Apr 2008 B2
7370064 Yousefi'zadeh May 2008 B2
7370091 Slaughter et al. May 2008 B1
7370360 van der Made May 2008 B2
7373083 Silverbrook et al. May 2008 B2
7373451 Lam et al. May 2008 B2
7374096 Overhultz et al. May 2008 B2
7374266 Walmsley et al. May 2008 B2
7376755 Pandya May 2008 B2
7377608 Walmsley et al. May 2008 B2
7377609 Walmsley et al. May 2008 B2
7377706 Silverbrook et al. May 2008 B2
7380039 Miloushev et al. May 2008 B2
7380051 Birrell et al. May 2008 B2
7382264 Rajapakse et al. Jun 2008 B2
7389383 Tremblay et al. Jun 2008 B2
7390071 Walmsley et al. Jun 2008 B2
7391435 Silverbrook Jun 2008 B2
7395333 Saulpaugh et al. Jul 2008 B1
7395536 Verbeke et al. Jul 2008 B2
7398349 Birrell et al. Jul 2008 B2
7398533 Slaughter et al. Jul 2008 B1
7399043 Walmsley et al. Jul 2008 B2
7409584 Denninghoff et al. Aug 2008 B2
7409719 Armstrong et al. Aug 2008 B2
7412518 Duigou et al. Aug 2008 B1
7412520 Sun Aug 2008 B2
7415723 Pandya Aug 2008 B2
7418504 Larson et al. Aug 2008 B2
7421698 Fresko Sep 2008 B2
7426721 Saulpaugh et al. Sep 2008 B1
7427117 Jackson Pulver et al. Sep 2008 B2
7430670 Horning et al. Sep 2008 B1
7437606 Janakiraman et al. Oct 2008 B2
7437614 Haswell et al. Oct 2008 B2
7443434 Silverbrook Oct 2008 B2
7444601 Proudler et al. Oct 2008 B2
7444644 Slaughter et al. Oct 2008 B1
7448079 Tremain Nov 2008 B2
7448707 Jackson Pulver et al. Nov 2008 B2
7452048 Silverbrook Nov 2008 B2
7453492 Silverbrook Nov 2008 B2
7456861 Silverbrook Nov 2008 B2
7458082 Slaughter et al. Nov 2008 B1
7460152 Silverbrook et al. Dec 2008 B2
7461931 Silverbrook Dec 2008 B2
7467198 Goodman et al. Dec 2008 B2
7467202 Savchuk Dec 2008 B2
7467333 Keeton et al. Dec 2008 B2
7475825 Silverbrook et al. Jan 2009 B2
7478278 Archer et al. Jan 2009 B2
7480761 Birrell et al. Jan 2009 B2
7483050 Silverbrook et al. Jan 2009 B2
7483053 Silverbrook Jan 2009 B2
7484208 Nelson Jan 2009 B1
7484831 Walmsley et al. Feb 2009 B2
7487264 Pandya Feb 2009 B2
7490151 Munger et al. Feb 2009 B2
7490250 Cromer et al. Feb 2009 B2
7490352 Kramer et al. Feb 2009 B2
7492490 Silverbrook Feb 2009 B2
7505068 Silverbrook Mar 2009 B2
7511744 Silverbrook et al. Mar 2009 B2
7512769 Lowell et al. Mar 2009 B1
7516365 Lev Apr 2009 B2
7516366 Lev et al. Apr 2009 B2
7517036 Walmsley et al. Apr 2009 B2
7517071 Silverbrook Apr 2009 B2
7523111 Walmsley Apr 2009 B2
7524045 Silverbrook et al. Apr 2009 B2
7524047 Silverbrook Apr 2009 B2
7527209 Silverbrook May 2009 B2
7529897 Waldspurger et al. May 2009 B1
7533141 Nadgir et al. May 2009 B2
7533229 van Rietschote May 2009 B1
7536462 Pandya May 2009 B2
7539602 Willis May 2009 B2
7546600 Tumer et al. Jun 2009 B2
7548946 Saulpaugh et al. Jun 2009 B1
7549167 Huang et al. Jun 2009 B1
7549579 Overhultz et al. Jun 2009 B2
7549715 Walmsley et al. Jun 2009 B2
7549718 Silverbrook et al. Jun 2009 B2
7552312 Archer et al. Jun 2009 B2
7552434 Turner et al. Jun 2009 B2
7557941 Walmsley Jul 2009 B2
7559472 Silverbrook et al. Jul 2009 B2
7562369 Salamone et al. Jul 2009 B1
7568025 Vasudeva Jul 2009 B2
7571312 Scarlata et al. Aug 2009 B2
7574588 Chaudhry et al. Aug 2009 B2
7574692 Herscu Aug 2009 B2
7575313 Silverbrook Aug 2009 B2
7577834 Traversat et al. Aug 2009 B1
7581826 Silverbrook Sep 2009 B2
7590869 Hashimoto Sep 2009 B2
7590972 Axelrod et al. Sep 2009 B2
7592829 Walmsley et al. Sep 2009 B2
7594168 Rempell Sep 2009 B2
7596790 Moakley Sep 2009 B2
7600843 Silverbrook et al. Oct 2009 B2
7602423 Silverbrook Oct 2009 B2
7603392 Ben-Yehuda et al. Oct 2009 B2
7603440 Grabowski et al. Oct 2009 B1
7603707 Seifert et al. Oct 2009 B2
7607129 Rosu et al. Oct 2009 B2
7607757 Silverbrook et al. Oct 2009 B2
7610510 Agarwal et al. Oct 2009 B2
7613749 Flynn, Jr. et al. Nov 2009 B2
7613929 Cohen et al. Nov 2009 B2
7620821 Grohoski et al. Nov 2009 B1
7621607 Silverbrook Nov 2009 B2
7624383 Barr et al. Nov 2009 B2
7627693 Pandya Dec 2009 B2
7629999 Silverbrook Dec 2009 B2
7631107 Pandya Dec 2009 B2
7631190 Walmsley Dec 2009 B2
7631966 Silverbrook et al. Dec 2009 B2
7636940 Yim Dec 2009 B2
7653833 Miller et al. Jan 2010 B1
7654626 Silverbrook et al. Feb 2010 B2
7657419 van der Made Feb 2010 B2
7660998 Walmsley Feb 2010 B2
7663502 Breed Feb 2010 B2
7665834 Silverbrook Feb 2010 B2
7669040 Dice Feb 2010 B2
7669081 Lett et al. Feb 2010 B2
7676456 Suganuma et al. Mar 2010 B2
7680919 Nelson Mar 2010 B2
7681075 Havemose et al. Mar 2010 B2
7685251 Houlihan et al. Mar 2010 B2
7685254 Pandya Mar 2010 B2
7689676 Vinberg et al. Mar 2010 B2
7689859 Westenberg Mar 2010 B2
7694139 Nachenberg et al. Apr 2010 B2
7698465 Lamport Apr 2010 B2
7701506 Silverbrook Apr 2010 B2
7702660 Chan et al. Apr 2010 B2
7707583 Schmidt et al. Apr 2010 B2
7707621 Walmsley Apr 2010 B2
7716077 Mikurak May 2010 B1
7716492 Saulpaugh et al. May 2010 B1
7721138 Lyadvinsky et al. May 2010 B1
7721139 Castro et al. May 2010 B2
7722172 Silverbrook May 2010 B2
7725703 Hunter et al. May 2010 B2
7730299 Boebert et al. Jun 2010 B2
7730312 Everett et al. Jun 2010 B2
7730364 Chang et al. Jun 2010 B2
7734607 Grinstein et al. Jun 2010 B2
7734859 Daniel et al. Jun 2010 B2
7734921 Lotspiech Jun 2010 B2
7735944 Silverbrook et al. Jun 2010 B2
7739517 Sahita et al. Jun 2010 B2
7743126 Russell Jun 2010 B2
7743389 Mahalingam et al. Jun 2010 B2
7747154 Silverbrook Jun 2010 B2
7747730 Harlow Jun 2010 B1
7747814 Green Jun 2010 B2
7747887 Shipton et al. Jun 2010 B2
7750971 Silverbrook Jul 2010 B2
7752459 Cowan et al. Jul 2010 B2
7757086 Walmsley Jul 2010 B2
7758143 Silverbrook et al. Jul 2010 B2
7760743 Shokri et al. Jul 2010 B2
7770008 Walmsley Aug 2010 B2
7779270 Horning et al. Aug 2010 B2
7779298 Challenger et al. Aug 2010 B2
7779394 Homing et al. Aug 2010 B2
7783779 Scales et al. Aug 2010 B1
7783886 Walmsley Aug 2010 B2
7783914 Havemose Aug 2010 B1
7789501 Silverbrook Sep 2010 B2
7793853 Silverbrook et al. Sep 2010 B2
7805626 Shipton Sep 2010 B2
7805761 Ray et al. Sep 2010 B2
7808610 Silverbrook Oct 2010 B2
7810081 Dickenson et al. Oct 2010 B2
7814142 Mamou et al. Oct 2010 B2
7814295 Inglett et al. Oct 2010 B2
7814470 Mamou et al. Oct 2010 B2
7817981 Coppinger et al. Oct 2010 B2
7818510 Tremblay et al. Oct 2010 B2
7818519 Plunkett Oct 2010 B2
7822410 Coppinger et al. Oct 2010 B2
7822979 Mittal Oct 2010 B2
7823135 Horning et al. Oct 2010 B2
7826088 Silverbrook Nov 2010 B2
7831787 Yueh Nov 2010 B1
7831827 Walmsley Nov 2010 B2
7832842 Jackson Pulver et al. Nov 2010 B2
7836215 Fuente Nov 2010 B2
7836303 Levy et al. Nov 2010 B2
7837115 Silverbrook et al. Nov 2010 B2
7839803 Snelgrove et al. Nov 2010 B1
7840787 De Pauw et al. Nov 2010 B2
7844954 Venkitachalam et al. Nov 2010 B2
7849450 Rydh et al. Dec 2010 B1
7849624 Holt et al. Dec 2010 B2
7865608 Schuba et al. Jan 2011 B1
7865872 Chamieh et al. Jan 2011 B2
7865893 Omelyanchuk et al. Jan 2011 B1
7866778 Silverbrook et al. Jan 2011 B2
7870217 Pandya Jan 2011 B2
7870424 Okabe Jan 2011 B2
7873869 Darrington et al. Jan 2011 B2
7877436 Arimilli et al. Jan 2011 B2
7882216 Houlihan et al. Feb 2011 B2
7890689 Lam et al. Feb 2011 B2
7899788 Chandhok et al. Mar 2011 B2
7899915 Reisman Mar 2011 B2
7900003 Ben-Yehuda et al. Mar 2011 B2
7904664 Tremblay et al. Mar 2011 B2
7904746 Nakamura et al. Mar 2011 B2
7908255 Detlefs et al. Mar 2011 B2
7908653 Brickell et al. Mar 2011 B2
7917469 Bernhard et al. Mar 2011 B2
7917596 Chan et al. Mar 2011 B2
7921211 Larson et al. Apr 2011 B2
7921686 Bagepalli et al. Apr 2011 B2
7924313 Silverbrook et al. Apr 2011 B2
7925791 Ellis et al. Apr 2011 B2
7925850 Waldspurger et al. Apr 2011 B1
7930733 Iftode et al. Apr 2011 B1
7931200 Silverbrook et al. Apr 2011 B2
7933990 Munger et al. Apr 2011 B2
7934020 Xu et al. Apr 2011 B1
7934035 Miloushev et al. Apr 2011 B2
7936395 Silverbrook May 2011 B2
7937547 Liu et al. May 2011 B2
7937618 Dorai et al. May 2011 B2
7941402 Smits May 2011 B2
7941647 Yates, Jr. et al. May 2011 B2
7941664 Wheeler et al. May 2011 B2
7941698 Aggarwal et al. May 2011 B1
7941799 Easton et al. May 2011 B2
7942332 Silverbrook et al. May 2011 B2
7944920 Pandya May 2011 B2
7945654 Larson et al. May 2011 B2
7953588 Altman et al. May 2011 B2
7957009 Silverbrook Jun 2011 B2
7957991 Mikurak Jun 2011 B2
7958558 Leake et al. Jun 2011 B1
7962137 Coppinger et al. Jun 2011 B2
7962545 Knauerhase et al. Jun 2011 B2
7962620 Safari et al. Jun 2011 B2
7962703 Shah et al. Jun 2011 B1
7962798 Locasto et al. Jun 2011 B2
7962909 Klaiber Jun 2011 B1
7965425 Silverbrook Jun 2011 B2
7966519 Aggarwal et al. Jun 2011 B1
7966614 Chodroff et al. Jun 2011 B2
7970736 Ben-Yehuda et al. Jun 2011 B2
7971015 Waldspurger et al. Jun 2011 B2
7975138 Andrade Jul 2011 B2
7975165 Shneorson et al. Jul 2011 B2
7975176 Bak et al. Jul 2011 B2
7979846 Grechanik et al. Jul 2011 B2
7984304 Waldspurger et al. Jul 2011 B1
7984965 Silverbrook et al. Jul 2011 B2
7987274 Larson et al. Jul 2011 B2
7987491 Reisman Jul 2011 B2
8001232 Saulpaugh et al. Aug 2011 B1
8001342 Armstrong et al. Aug 2011 B2
8001505 Bist et al. Aug 2011 B2
8005966 Pandya Aug 2011 B2
8006079 Goodson et al. Aug 2011 B2
8010495 Kuznetzov et al. Aug 2011 B1
8011010 Michael et al. Aug 2011 B2
8011747 Walmsley et al. Sep 2011 B2
8016400 Silverbrook Sep 2011 B2
8019964 Greiner et al. Sep 2011 B2
8020099 Lu Sep 2011 B1
8020979 Silverbrook Sep 2011 B2
8028071 Mahalingam et al. Sep 2011 B1
8032409 Mikurak Oct 2011 B1
8037112 Nath et al. Oct 2011 B2
8037202 Yeager et al. Oct 2011 B2
8037278 Greiner et al. Oct 2011 B2
8037350 Aggarwal et al. Oct 2011 B1
8038239 Walmsley et al. Oct 2011 B2
8041760 Mamou et al. Oct 2011 B2
8041922 Greiner et al. Oct 2011 B2
8041923 Greiner et al. Oct 2011 B2
8046579 Kresina Oct 2011 B2
8051181 Larson et al. Nov 2011 B2
8055886 Tashiro et al. Nov 2011 B2
8055940 Ellis et al. Nov 2011 B2
8060553 Mamou et al. Nov 2011 B2
8061828 Silverbrook Nov 2011 B2
8065240 Jung et al. Nov 2011 B2
8065504 Yates, Jr. et al. Nov 2011 B2
8065722 Barford et al. Nov 2011 B2
8068151 Silverbrook et al. Nov 2011 B2
8069218 Tormasov et al. Nov 2011 B1
8069374 Panigrahy et al. Nov 2011 B2
8074055 Yates, Jr. et al. Dec 2011 B1
8077207 Silverbrook Dec 2011 B2
8078854 Vick et al. Dec 2011 B2
8078910 Backensto et al. Dec 2011 B1
8082405 Greiner et al. Dec 2011 B2
8082468 Backensto et al. Dec 2011 B1
8082481 Casper et al. Dec 2011 B2
8082491 Abdelaziz et al. Dec 2011 B1
8086811 Gainey, Jr. et al. Dec 2011 B2
8090452 Johnson et al. Jan 2012 B2
8098285 Silverbrook Jan 2012 B2
8102071 Catlin Jan 2012 B2
8103674 de Moura et al. Jan 2012 B2
8103851 Greiner et al. Jan 2012 B2
8108455 Yeager et al. Jan 2012 B2
8108662 Darrington et al. Jan 2012 B2
8108722 Havemose et al. Jan 2012 B1
8108855 Dias et al. Jan 2012 B2
8112423 Bernhard et al. Feb 2012 B2
8117372 Daniel et al. Feb 2012 B2
8117417 Greiner et al. Feb 2012 B2
8117496 Bashir et al. Feb 2012 B2
8117554 Grechishkin et al. Feb 2012 B1
8121828 Yates, Jr. et al. Feb 2012 B2
8122434 Kostadinov et al. Feb 2012 B2
8127060 Doll et al. Feb 2012 B2
8127121 Yates, Jr. et al. Feb 2012 B2
8127412 Gleichauf et al. Mar 2012 B2
8131845 Vasudeva Mar 2012 B1
8131851 Harlow Mar 2012 B2
8135796 Slaughter et al. Mar 2012 B1
8140565 D'Angelo et al. Mar 2012 B2
8140905 Beaty et al. Mar 2012 B2
8140907 Beaty et al. Mar 2012 B2
8145945 Lee Mar 2012 B2
8151083 Greiner et al. Apr 2012 B2
8156373 Zheng et al. Apr 2012 B2
8161172 Reisman Apr 2012 B2
8161321 Zheng et al. Apr 2012 B2
8161479 Sedukhin et al. Apr 2012 B2
8165286 Ciet et al. Apr 2012 B2
8166477 Tormasov Apr 2012 B1
8166693 Hughes et al. May 2012 B2
8171301 Seguin et al. May 2012 B2
8171338 Agesen et al. May 2012 B2
8171554 Elovici et al. May 2012 B2
8176364 Havemose May 2012 B1
8181150 Szpak et al. May 2012 B2
8181182 Martin May 2012 B1
8181239 Pandya May 2012 B2
8185502 Irisawa et al. May 2012 B2
8190574 Barnes et al. May 2012 B2
8195722 Havemose et al. Jun 2012 B1
8195739 Bernardin et al. Jun 2012 B2
8195774 Lambeth et al. Jun 2012 B2
8195984 Alberi et al. Jun 2012 B2
8196139 Easton et al. Jun 2012 B2
8196205 Gribble et al. Jun 2012 B2
8200771 Ganesh et al. Jun 2012 B2
8201169 Venkitachalam et al. Jun 2012 B2
8204082 Jungck et al. Jun 2012 B2
8205120 Heidasch et al. Jun 2012 B2
8205194 Fries et al. Jun 2012 B2
8209524 Ferren et al. Jun 2012 B2
8209680 Le et al. Jun 2012 B1
8214191 Ferren et al. Jul 2012 B2
8214367 Baratto et al. Jul 2012 B2
8214622 Blandy et al. Jul 2012 B2
8214686 Ueda Jul 2012 B2
8214829 Neogi et al. Jul 2012 B2
8219063 Rogel et al. Jul 2012 B2
8219947 Bist et al. Jul 2012 B2
8225314 Martins et al. Jul 2012 B2
8233882 Rogel Jul 2012 B2
8239340 Hanson Aug 2012 B2
8239633 Wood et al. Aug 2012 B2
8239646 Colbert et al. Aug 2012 B2
8239649 Gainey, Jr. et al. Aug 2012 B2
8244954 Ganesh et al. Aug 2012 B2
8245013 Ganesh et al. Aug 2012 B2
8245083 Van Der Merwe et al. Aug 2012 B2
8250405 Elnozahy Aug 2012 B2
8255651 Liu et al. Aug 2012 B2
8260904 Nelson Sep 2012 B2
8261233 Szpak et al. Sep 2012 B2
8266125 Wester et al. Sep 2012 B2
8266275 Xu et al. Sep 2012 B2
8266276 Vasudeva Sep 2012 B1
8266404 Waldspurger et al. Sep 2012 B2
8266607 Burka et al. Sep 2012 B2
8271336 Mikurak Sep 2012 B2
8271950 Bharadwaj Sep 2012 B2
8271990 De et al. Sep 2012 B2
8274665 Silverbrook Sep 2012 B2
8276127 Rydh et al. Sep 2012 B2
8280944 Laadan et al. Oct 2012 B2
8280974 Herington Oct 2012 B2
8281317 Backensto et al. Oct 2012 B1
8281318 Chanda et al. Oct 2012 B2
8285999 Ghose et al. Oct 2012 B1
8286174 Schmidt et al. Oct 2012 B1
8295834 Coppinger et al. Oct 2012 B2
8295835 Coppinger et al. Oct 2012 B2
8296419 Khanna et al. Oct 2012 B1
8296551 Bugnion Oct 2012 B2
8296759 Hutchins et al. Oct 2012 B1
8301672 Jiva et al. Oct 2012 B2
8301700 Havemose Oct 2012 B1
8302094 Rogel et al. Oct 2012 B2
8307187 Chawla et al. Nov 2012 B2
8312224 Elnozahy Nov 2012 B2
8315991 Mandagere et al. Nov 2012 B2
8321558 Sirota et al. Nov 2012 B1
8321643 Vaghani et al. Nov 2012 B1
8321948 Robinson et al. Nov 2012 B2
8326449 Hartz et al. Dec 2012 B2
8327350 Chess et al. Dec 2012 B2
8328101 Silverbrook et al. Dec 2012 B2
8332632 Iftode et al. Dec 2012 B2
8332649 Yokota et al. Dec 2012 B2
8332689 Timashev et al. Dec 2012 B2
8332824 Shemenzon et al. Dec 2012 B2
8335906 Greiner et al. Dec 2012 B2
8341749 Rogel Dec 2012 B2
8346726 Liu et al. Jan 2013 B2
8346891 Safari et al. Jan 2013 B2
8347072 Mittal Jan 2013 B2
8347140 Backensto et al. Jan 2013 B1
8347288 Brandwine Jan 2013 B1
8352801 Van Der Merwe et al. Jan 2013 B2
8356314 Sprunk Jan 2013 B2
8370493 Sirota et al. Feb 2013 B2
8370530 Tripathi et al. Feb 2013 B2
8370609 Favor et al. Feb 2013 B1
8370802 Pacifici et al. Feb 2013 B2
8370811 Grechanik et al. Feb 2013 B2
8370814 Grechanik et al. Feb 2013 B2
8370837 Emelianov et al. Feb 2013 B2
8370838 Omelyanchuk et al. Feb 2013 B1
8375188 Shah et al. Feb 2013 B1
8381028 Elnozahy Feb 2013 B2
8381032 Burn et al. Feb 2013 B2
8381224 Huetter et al. Feb 2013 B2
8386428 Kuznetzov et al. Feb 2013 B2
8386594 Underwood et al. Feb 2013 B2
8386838 Byan Feb 2013 B1
8386853 Alberi et al. Feb 2013 B2
8387022 Horning et al. Feb 2013 B2
8392838 Chawla et al. Mar 2013 B2
8397032 Elnozahy Mar 2013 B2
8397088 Ghose Mar 2013 B1
8401940 Havemose Mar 2013 B1
8401941 Havemose Mar 2013 B1
8402305 Havemose Mar 2013 B1
8402318 Nieh et al. Mar 2013 B2
8402464 Dice et al. Mar 2013 B2
8407428 Cheriton et al. Mar 2013 B2
8407455 Christie et al. Mar 2013 B2
8407518 Nelson et al. Mar 2013 B2
8413145 Chou et al. Apr 2013 B2
8417885 Chou et al. Apr 2013 B2
8417916 Greiner et al. Apr 2013 B2
8423959 Petras Apr 2013 B1
8423961 Byers et al. Apr 2013 B2
8424005 Strom et al. Apr 2013 B2
8429362 Natanzon et al. Apr 2013 B1
8433682 Ngo Apr 2013 B2
8433951 Havemose et al. Apr 2013 B1
8434093 Larimore et al. Apr 2013 B2
8438256 Rogel et al. May 2013 B2
8438360 Youngworth May 2013 B2
8438609 Cohen et al. May 2013 B2
8442955 Al Kiswany et al. May 2013 B2
8443069 Bagepalli et al. May 2013 B2
8443367 Taylor et al. May 2013 B1
8446224 Cortadella et al. May 2013 B2
8448022 Scott May 2013 B1
8453120 Ceze et al. May 2013 B2
8458341 Larson et al. Jun 2013 B2
8458517 Vermeulen et al. Jun 2013 B1
8458696 Park et al. Jun 2013 B2
8463825 Harty et al. Jun 2013 B1
8464256 Havemose Jun 2013 B1
8468310 Colbert et al. Jun 2013 B2
8468521 Pawlowski Jun 2013 B2
8473594 Astete et al. Jun 2013 B2
8473627 Astete et al. Jun 2013 B2
8473900 Frost Jun 2013 B2
8484732 Chen et al. Jul 2013 B1
8489699 Goggin et al. Jul 2013 B2
8489853 Greiner et al. Jul 2013 B2
8489939 Hiltunen et al. Jul 2013 B2
8495326 Gainey, Jr. et al. Jul 2013 B2
8495633 Easton et al. Jul 2013 B2
8495708 Cohen et al. Jul 2013 B2
8498966 Waghole Jul 2013 B1
8499297 Chen et al. Jul 2013 B2
8504670 Wu et al. Aug 2013 B2
8504696 Larson et al. Aug 2013 B2
8504697 Larson et al. Aug 2013 B2
8504791 Cheriton et al. Aug 2013 B2
8510596 Gupta et al. Aug 2013 B1
8510827 Leake et al. Aug 2013 B1
8516117 Munger et al. Aug 2013 B2
8516131 Larson et al. Aug 2013 B2
8520002 Stambaugh Aug 2013 B2
8521888 Larson et al. Aug 2013 B2
8527462 Talius et al. Sep 2013 B1
8527640 Reisman Sep 2013 B2
8527809 Backensto et al. Sep 2013 B1
8527990 Marathe et al. Sep 2013 B1
8533382 Scales et al. Sep 2013 B2
8533390 Dong et al. Sep 2013 B2
8533663 Moir et al. Sep 2013 B2
8533713 Dong Sep 2013 B2
8539066 Vasudeva Sep 2013 B1
8539137 Protassov et al. Sep 2013 B1
8539262 Huang et al. Sep 2013 B2
8539434 Vertes Sep 2013 B2
8539488 Havemose Sep 2013 B1
8548146 Soo et al. Oct 2013 B2
8548790 Tylutki Oct 2013 B2
8549210 Hunter et al. Oct 2013 B2
8549241 Scales et al. Oct 2013 B2
8549275 Mittal Oct 2013 B2
8549313 Seguin et al. Oct 2013 B2
8549646 Stavrou et al. Oct 2013 B2
8554899 Larson et al. Oct 2013 B2
8554900 Nelson Oct 2013 B2
8554981 Schmidt et al. Oct 2013 B2
8560366 Mikurak Oct 2013 B2
8560705 Larson et al. Oct 2013 B2
8560772 Piszczek et al. Oct 2013 B1
8560816 Moir et al. Oct 2013 B2
8561045 Porras et al. Oct 2013 B2
8561046 Song et al. Oct 2013 B2
8566640 Timashev et al. Oct 2013 B2
8572247 Larson et al. Oct 2013 B2
8572613 Brandwine Oct 2013 B1
8572735 Ghosh et al. Oct 2013 B2
8572876 Shekarri et al. Nov 2013 B2
8576881 Jungck et al. Nov 2013 B2
8577845 Nguyen et al. Nov 2013 B2
8578000 Van Wie et al. Nov 2013 B2
8584101 Moon et al. Nov 2013 B2
8584127 Yoshida Nov 2013 B2
8588179 Fujino Nov 2013 B2
8589406 Lillibridge Nov 2013 B2
8595191 Prahlad et al. Nov 2013 B2
8601086 Pandya Dec 2013 B2
8601483 He et al. Dec 2013 B2
8601498 Laurich et al. Dec 2013 B2
8607039 Filali-Adib et al. Dec 2013 B2
8607242 Clarke Dec 2013 B2
8612802 Havemose Dec 2013 B1
8621180 Greiner et al. Dec 2013 B2
8621183 Hohmuth et al. Dec 2013 B2
8621275 Havemose Dec 2013 B1
8621283 Van Der Merwe et al. Dec 2013 B2
8621496 Madampath Dec 2013 B2
8622839 McKenzie et al. Jan 2014 B1
8627000 Green et al. Jan 2014 B2
8627053 Mittal Jan 2014 B2
8627143 Ranganathan et al. Jan 2014 B2
8631066 Lim et al. Jan 2014 B2
8631216 Greiner et al. Jan 2014 B2
8631248 Cowan et al. Jan 2014 B2
8631411 Ghose Jan 2014 B1
8631456 Reisman Jan 2014 B2
8639599 Havemose Jan 2014 B1
8645240 Havemose Feb 2014 B1
8645754 Backensto et al. Feb 2014 B1
8645958 Huetter et al. Feb 2014 B2
8656077 Miloushev et al. Feb 2014 B2
8656412 Kashyap Feb 2014 B2
8661457 Kashyap Feb 2014 B2
8667066 Havemose Mar 2014 B1
8671085 Dhamankar et al. Mar 2014 B2
8677352 Hiltgen et al. Mar 2014 B2
8682795 Lenkov et al. Mar 2014 B2
8683004 Bauer Mar 2014 B2
8694821 Griffith et al. Apr 2014 B2
8694828 Nelson et al. Apr 2014 B2
8706992 Liu et al. Apr 2014 B2
8713268 Dillow et al. Apr 2014 B2
8713273 Waldspurger et al. Apr 2014 B2
8713293 Tashiro et al. Apr 2014 B2
8713362 Griffith et al. Apr 2014 B2
8719520 Piszczek et al. May 2014 B1
8719849 Madampath May 2014 B1
8725782 Starks et al. May 2014 B2
8726078 Havemose May 2014 B1
8726251 Kalogeropulos et al. May 2014 B2
8732023 Mikurak May 2014 B2
8739164 Chung et al. May 2014 B2
8745098 Havemose et al. Jun 2014 B1
8745442 Havemose Jun 2014 B1
8745601 Carlson et al. Jun 2014 B1
8752048 Backensto et al. Jun 2014 B1
8752049 Backensto et al. Jun 2014 B1
8769127 Selimis et al. Jul 2014 B2
8775871 Backensto et al. Jul 2014 B1
8776038 Larimore et al. Jul 2014 B2
8782365 Mooring et al. Jul 2014 B1
8782434 Ghose Jul 2014 B1
8782435 Ghose Jul 2014 B1
8782632 Chigurapati et al. Jul 2014 B1
8788792 Yates, Jr. et al. Jul 2014 B2
8789034 Emelyanov et al. Jul 2014 B1
8799119 Havemose Aug 2014 B1
8805788 Gross, IV et al. Aug 2014 B2
8806266 Qu et al. Aug 2014 B1
8818886 Havemose Aug 2014 B1
8825830 Newton et al. Sep 2014 B2
8826070 Havemose et al. Sep 2014 B1
8826273 Chen Sep 2014 B1
8832682 Xu et al. Sep 2014 B2
8839426 Brueckner et al. Sep 2014 B1
8843643 Larson et al. Sep 2014 B2
8850009 Larson et al. Sep 2014 B2
8850583 Nelson et al. Sep 2014 B1
8856473 van Riel Oct 2014 B2
8856767 Jalan et al. Oct 2014 B2
8862538 Patil et al. Oct 2014 B2
8862861 Olson et al. Oct 2014 B2
8868506 Bhargava et al. Oct 2014 B1
8868705 Larson et al. Oct 2014 B2
8869139 Le et al. Oct 2014 B2
8875160 Hunt et al. Oct 2014 B2
8880473 Havemose et al. Nov 2014 B1
8880866 Doerr et al. Nov 2014 B2
8881171 Backensto et al. Nov 2014 B1
8893129 Havemose Nov 2014 B1
8893147 Yin et al. Nov 2014 B2
8902340 Silverbrook Dec 2014 B2
8903705 Douceur et al. Dec 2014 B2
8904189 Ghose Dec 2014 B1
8904516 Larson et al. Dec 2014 B2
8908051 Silverbrook Dec 2014 B2
8908069 Silverbrook Dec 2014 B2
8913137 Silverbrook Dec 2014 B2
8918879 Li et al. Dec 2014 B1
8922791 Silverbrook Dec 2014 B2
8928897 Silverbrook Jan 2015 B2
8930705 Ghose et al. Jan 2015 B1
8936196 Silverbrook et al. Jan 2015 B2
8937727 Silverbrook Jan 2015 B2
8943201 Larson et al. Jan 2015 B2
8943501 Havemose Jan 2015 B1
8945605 Boucher et al. Feb 2015 B2
8947592 Silverbrook Feb 2015 B2
8947679 Silverbrook Feb 2015 B2
8949585 Hiltgen et al. Feb 2015 B2
8953178 Silverbrook Feb 2015 B2
8955111 Glew et al. Feb 2015 B2
8966312 Gupta et al. Feb 2015 B1
8966315 Burn et al. Feb 2015 B2
8977736 Nelson Mar 2015 B2
8996912 Havemose et al. Mar 2015 B1
9003229 Havemose Apr 2015 B1
9009212 Sankararaman Apr 2015 B2
9026849 Patterson et al. May 2015 B2
9027003 Weissman et al. May 2015 B2
9027022 Huetter et al. May 2015 B2
9027115 Larson et al. May 2015 B2
9032170 Vaghani et al. May 2015 B2
9032249 Havemose May 2015 B1
9037713 Larson et al. May 2015 B2
9037883 Huang et al. May 2015 B2
9038163 Larson et al. May 2015 B2
9043640 Havemose May 2015 B1
9047178 Talagala et al. Jun 2015 B2
9058599 Havemose Jun 2015 B1
9058600 Havemose Jun 2015 B1
9063721 Ghose Jun 2015 B2
9063821 Emelyanov et al. Jun 2015 B1
9064099 Horning et al. Jun 2015 B2
9065706 Koinuma et al. Jun 2015 B2
9069782 Yang et al. Jun 2015 B2
9071526 Avdanin et al. Jun 2015 B2
9077694 Larson et al. Jul 2015 B2
9077695 Larson et al. Jul 2015 B2
9081602 Omelyanchuk et al. Jul 2015 B1
9086969 Bekiroglu et al. Jul 2015 B2
9092837 Bala et al. Jul 2015 B2
9094399 Larson et al. Jul 2015 B2
9094449 Brueckner et al. Jul 2015 B2
9098347 Hiltgen et al. Aug 2015 B2
9098700 Sethumadhavan et al. Aug 2015 B2
9100371 Bagepalli et al. Aug 2015 B2
9100375 Larson et al. Aug 2015 B2
9104624 Timashev et al. Aug 2015 B2
9110722 Adams et al. Aug 2015 B2
9116812 Joshi et al. Aug 2015 B2
9116847 Liu et al. Aug 2015 B2
9117087 Tan et al. Aug 2015 B2
9122765 Chen Sep 2015 B1
9122873 Ghose Sep 2015 B2
9135063 Ghose Sep 2015 B1
9135667 Drees et al. Sep 2015 B2
9137397 Silverbrook Sep 2015 B2
9141502 Havemose Sep 2015 B2
9141786 Edery et al. Sep 2015 B2
9146764 Wagner Sep 2015 B1
9146819 Banikazemi et al. Sep 2015 B2
9148530 Silverbrook Sep 2015 B2
9152508 Barnes et al. Oct 2015 B1
9152610 Drees et al. Oct 2015 B2
9154433 Koponen et al. Oct 2015 B2
9158626 Havemose et al. Oct 2015 B1
9158810 Aingaran et al. Oct 2015 B2
9164566 Ghose Oct 2015 B2
9164843 Havemose Oct 2015 B1
9164847 Havemose et al. Oct 2015 B1
9178833 Koponen et al. Nov 2015 B2
9179020 Silverbrook Nov 2015 B2
9183089 Havemose Nov 2015 B1
9185125 Varsanyi et al. Nov 2015 B2
9185246 Silverbrook Nov 2015 B2
9189233 Sasanka et al. Nov 2015 B2
9189265 Hiltgen et al. Nov 2015 B2
9189621 Touboul Nov 2015 B2
9195519 Tan et al. Nov 2015 B2
9201737 Backensto et al. Dec 2015 B1
9207934 Larimore et al. Dec 2015 B2
9208030 Mooring et al. Dec 2015 B1
9218278 Talagala et al. Dec 2015 B2
9219747 Amoroso et al. Dec 2015 B2
9219755 Touboul Dec 2015 B2
9219832 Silverbrook Dec 2015 B2
9223967 Ghose Dec 2015 B2
9229758 Ammons et al. Jan 2016 B2
9230122 Ghose Jan 2016 B2
9231882 Fulton et al. Jan 2016 B2
9237244 Silverbrook Jan 2016 B2
9239765 Block et al. Jan 2016 B2
9246833 Koponen et al. Jan 2016 B2
9251004 Havemose Feb 2016 B1
9251098 Haid et al. Feb 2016 B2
9253109 Koponen et al. Feb 2016 B2
9256496 Havemose Feb 2016 B1
9262194 Sudhakar Feb 2016 B2
9268602 Prahlad et al. Feb 2016 B2
9268702 Bilas et al. Feb 2016 B2
9280393 Bird et al. Mar 2016 B2
9282166 Markley et al. Mar 2016 B2
9286109 Backensto et al. Mar 2016 B1
9286703 Brumer et al. Mar 2016 B2
9292330 Bonilla et al. Mar 2016 B2
9294282 Potlapally et al. Mar 2016 B1
9304869 Backensto et al. Apr 2016 B1
9311140 Raghu et al. Apr 2016 B2
9311313 Le et al. Apr 2016 B2
9317315 Mehta Apr 2016 B2
9317326 Ramanathan et al. Apr 2016 B2
9323550 Lim et al. Apr 2016 B2
9323556 Wagner Apr 2016 B2
9323623 Havemose Apr 2016 B1
9323921 Hunt et al. Apr 2016 B2
9329894 Raghu May 2016 B2
9336040 Dong et al. May 2016 B2
9336099 Havemose May 2016 B1
9348652 Raghu May 2016 B2
9354921 Nelson May 2016 B2
9354927 Hiltgen et al. May 2016 B2
9354977 Backensto et al. May 2016 B1
9355161 Havemose May 2016 B1
9356962 Ilieva et al. May 2016 B2
9372732 Adams et al. Jun 2016 B2
9374346 Larson et al. Jun 2016 B2
9378059 Huetter et al. Jun 2016 B2
9384347 Havemose Jul 2016 B1
9386000 Larson et al. Jul 2016 B2
9389893 Raghu Jul 2016 B2
9389933 Baumann et al. Jul 2016 B2
9389959 Backensto et al. Jul 2016 B1
9391801 Raghu Jul 2016 B2
20020002706 Sprunk Jan 2002 A1
20020003884 Sprunk Jan 2002 A1
20020019844 Kurowski et al. Feb 2002 A1
20020030712 Silverbrook Mar 2002 A1
20020030713 Silverbrook Mar 2002 A1
20020032903 Sprunk Mar 2002 A1
20020033854 Silverbrook Mar 2002 A1
20020065776 Calder et al. May 2002 A1
20020065869 Calder et al. May 2002 A1
20020065874 Chien et al. May 2002 A1
20020065876 Chien et al. May 2002 A1
20020065912 Catchpole et al. May 2002 A1
20020065945 Calder et al. May 2002 A1
20020066021 Chien et al. May 2002 A1
20020066022 Calder et al. May 2002 A1
20020069369 Tremain Jun 2002 A1
20020071104 Silverbrook Jun 2002 A1
20020073101 Stoyen Jun 2002 A1
20020073283 Lewis et al. Jun 2002 A1
20020080335 Silverbrook Jun 2002 A1
20020092003 Calder et al. Jul 2002 A1
20020092015 Sprunk et al. Jul 2002 A1
20020093980 Trebes Jul 2002 A1
20020094084 Wasilewski et al. Jul 2002 A1
20020095665 Chaudhry et al. Jul 2002 A1
20020147969 Lethin et al. Oct 2002 A1
20020161884 Munger et al. Oct 2002 A1
20020161925 Munger et al. Oct 2002 A1
20020188653 Sun Dec 2002 A1
20020194388 Boloker et al. Dec 2002 A1
20030005102 Russell Jan 2003 A1
20030018826 Chaudhry et al. Jan 2003 A1
20030028861 Wallman et al. Feb 2003 A1
20030037142 Munger et al. Feb 2003 A1
20030058277 Bowman-Amuah Mar 2003 A1
20030068185 Silverbrook Apr 2003 A1
20030079116 Chaudlhry et al. Apr 2003 A1
20030092972 Mantilla et al. May 2003 A1
20030097278 Mantilla et al. May 2003 A1
20030112419 Silverbrook Jun 2003 A1
20030117496 Silverbrook Jun 2003 A1
20030149962 Willis et al. Aug 2003 A1
20030154061 Willis Aug 2003 A1
20030154284 Bernardin et al. Aug 2003 A1
20030158960 Engberg Aug 2003 A1
20030167307 Filepp et al. Sep 2003 A1
20030167342 Munger et al. Sep 2003 A1
20030167421 Klemm Sep 2003 A1
20030182572 Cowan et al. Sep 2003 A1
20030187911 Abd-El-Malek et al. Oct 2003 A1
20030188141 Chaudhry et al. Oct 2003 A1
20030191795 Bernardin et al. Oct 2003 A1
20030208500 Daynes et al. Nov 2003 A1
20030208673 Chaudhry et al. Nov 2003 A1
20030212987 Demuth et al. Nov 2003 A1
20030229900 Reisman Dec 2003 A1
20040004129 Silverbrook Jan 2004 A1
20040004651 Silverbrook Jan 2004 A1
20040004698 Silverbrook et al. Jan 2004 A1
20040007121 Graves et al. Jan 2004 A1
20040008261 Silverbrook Jan 2004 A1
20040008262 Silverbrook et al. Jan 2004 A1
20040008327 Silverbrook Jan 2004 A1
20040010545 Pandya Jan 2004 A1
20040010612 Pandya Jan 2004 A1
20040015627 Desoli et al. Jan 2004 A1
20040030739 Yousefi'zadeh Feb 2004 A1
20040030757 Pandya Feb 2004 A1
20040030770 Pandya Feb 2004 A1
20040030806 Pandya Feb 2004 A1
20040031058 Reisman Feb 2004 A1
20040037299 Pandya Feb 2004 A1
20040037319 Pandya Feb 2004 A1
20040041018 Silverbrook et al. Mar 2004 A1
20040051753 Silverbrook Mar 2004 A1
20040055004 Sun et al. Mar 2004 A1
20040056105 Silverbrook et al. Mar 2004 A1
20040061734 Silverbrook Apr 2004 A1
20040064351 Mikurak Apr 2004 A1
20040065738 Silverbrook et al. Apr 2004 A1
20040075747 Silverbrook Apr 2004 A1
20040075821 Silverbrook Apr 2004 A1
20040080620 Silverbrook Apr 2004 A1
20040088347 Yeager et al. May 2004 A1
20040088348 Yeager et al. May 2004 A1
20040088369 Yeager et al. May 2004 A1
20040088646 Yeager et al. May 2004 A1
20040090553 Silverbrook May 2004 A1
20040098154 McCarthy May 2004 A1
20040098447 Verbeke et al. May 2004 A1
20040098485 Larson et al. May 2004 A1
20040103205 Larson et al. May 2004 A1
20040107025 Ransom et al. Jun 2004 A1
20040107285 Larson et al. Jun 2004 A1
20040107286 Larson et al. Jun 2004 A1
20040119827 Silverbrook et al. Jun 2004 A1
20040125209 Silverbrook et al. Jul 2004 A1
20040125212 Silverbrook et al. Jul 2004 A1
20040128670 Robinson et al. Jul 2004 A1
20040129789 Silverbrook et al. Jul 2004 A1
20040133640 Yeager et al. Jul 2004 A1
20040138787 Ransom et al. Jul 2004 A1
20040141061 Silverbrook Jul 2004 A1
20040143710 Walmsley Jul 2004 A1
20040148307 Rempell Jul 2004 A1
20040153558 Gunduc et al. Aug 2004 A1
20040158549 Matena et al. Aug 2004 A1
20040162951 Jacobson et al. Aug 2004 A1
20040162989 Kirovski Aug 2004 A1
20040165588 Pandya Aug 2004 A1
20040168030 Traversat et al. Aug 2004 A1
20040172626 Jalan et al. Sep 2004 A1
20040174570 Plunkett et al. Sep 2004 A1
20040179072 Silverbrook Sep 2004 A1
20040181303 Walmsley Sep 2004 A1
20040183843 Walmsley et al. Sep 2004 A1
20040183914 Silverbrook Sep 2004 A1
20040187115 Tremblay et al. Sep 2004 A1
20040187116 Tremblay et al. Sep 2004 A1
20040187123 Tremblay et al. Sep 2004 A1
20040189355 Walmsley Sep 2004 A1
20040189731 Robert Walmsley et al. Sep 2004 A1
20040193880 Walmsley Sep 2004 A1
20040196320 Walmsley et al. Oct 2004 A1
20040196513 Silverbrook Oct 2004 A1
20040199786 Walmsley et al. Oct 2004 A1
20040201647 Jackson Pulver et al. Oct 2004 A1
20040201939 Shipton et al. Oct 2004 A1
20040205377 Nakamura et al. Oct 2004 A1
20040205414 Roselli et al. Oct 2004 A1
20040210320 Pandya Oct 2004 A1
20040212652 Silverbrook Oct 2004 A1
20040213482 Silverbrook Oct 2004 A1
20040213613 Silverbrook Oct 2004 A1
20040218048 Silverbrook Nov 2004 A1
20040218049 Silverbrook Nov 2004 A1
20040218934 Silverbrook Nov 2004 A1
20040221194 Denninghoff et al. Nov 2004 A1
20040221287 Walmsley Nov 2004 A1
20040223010 Plunkett Nov 2004 A1
20040225881 Walmsley et al. Nov 2004 A1
20040227205 Walmsley Nov 2004 A1
20040230960 Nair et al. Nov 2004 A1
20040243978 Walmsley Dec 2004 A1
20040243986 Nishiyama Dec 2004 A1
20040246503 Silverbrook Dec 2004 A1
20040249757 Walmsley et al. Dec 2004 A1
20040254648 Johnson et al. Dec 2004 A1
20040254962 Kodama et al. Dec 2004 A1
20040254964 Kodama et al. Dec 2004 A1
20040267691 Vasudeva Dec 2004 A1
20050005200 Matena et al. Jan 2005 A1
20050015781 Brown et al. Jan 2005 A1
20050027870 Trebes Feb 2005 A1
20050050545 Moakley Mar 2005 A1
20050055399 Savchuk Mar 2005 A1
20050055588 Nalawadi et al. Mar 2005 A1
20050064849 Coppinger et al. Mar 2005 A1
20050064857 Coppinger et al. Mar 2005 A1
20050064868 Coppinger et al. Mar 2005 A1
20050076331 Das et al. Apr 2005 A1
20050086211 Mayer Apr 2005 A1
20050086451 Yates, Jr. et al. Apr 2005 A1
20050086520 Dharmapurikar et al. Apr 2005 A1
20050086650 Yates, Jr. et al. Apr 2005 A1
20050090258 Coppinger et al. Apr 2005 A1
20050091545 Soppera Apr 2005 A1
20050092849 Silverbrook May 2005 A1
20050093909 Silverbrook May 2005 A1
20050094166 Silverbrook May 2005 A1
20050099445 Silverbrook May 2005 A1
20050108518 Pandya May 2005 A1
20050113092 Coppinger et al. May 2005 A1
20050122399 Silverbrook et al. Jun 2005 A1
20050125513 Sin-Ling Lam et al. Jun 2005 A1
20050127181 Silverbrook Jun 2005 A1
20050145701 Silverbrook et al. Jul 2005 A1
20050146583 Silverbrook Jul 2005 A1
20050146613 Silverbrook et al. Jul 2005 A1
20050146614 Silverbrook Jul 2005 A1
20050151777 Silverbrook Jul 2005 A1
20050151819 Silverbrook Jul 2005 A1
20050152596 Walmsley Jul 2005 A1
20050156736 Rajapakse et al. Jul 2005 A1
20050158043 Silverbrook Jul 2005 A1
20050160316 Shipton Jul 2005 A1
20050160423 Bantz et al. Jul 2005 A1
20050162455 Silverbrook Jul 2005 A1
20050162456 Silverbrook Jul 2005 A1
20050166040 Walmsley Jul 2005 A1
20050172018 Devine et al. Aug 2005 A1
20050177633 Plunkett Aug 2005 A1
20050177635 Schmidt et al. Aug 2005 A1
20050179781 Silverbrook Aug 2005 A1
20050182985 Shipton et al. Aug 2005 A1
20050183072 Horning et al. Aug 2005 A1
20050185198 Silverbrook Aug 2005 A1
20050185461 Silverbrook et al. Aug 2005 A1
20050188218 Walmsley et al. Aug 2005 A1
20050193269 Haswell et al. Sep 2005 A1
20050198303 Knauerhase et al. Sep 2005 A1
20050204348 Horning et al. Sep 2005 A1
20050209930 Coppinger et al. Sep 2005 A1
20050210179 Walmsley et al. Sep 2005 A1
20050210275 Homing et al. Sep 2005 A1
20050213761 Walmsley et al. Sep 2005 A1
20050218236 Silverbrook et al. Oct 2005 A1
20050222931 Mamou et al. Oct 2005 A1
20050223109 Mamou et al. Oct 2005 A1
20050228808 Mamou et al. Oct 2005 A1
20050232046 Mamou et al. Oct 2005 A1
20050234969 Mamou et al. Oct 2005 A1
20050235274 Mamou et al. Oct 2005 A1
20050240354 Mamou et al. Oct 2005 A1
20050240592 Mamou et al. Oct 2005 A1
20050246708 Turner et al. Nov 2005 A1
20050247793 Silverbrook et al. Nov 2005 A1
20050251803 Turner et al. Nov 2005 A1
20050256843 Santos et al. Nov 2005 A1
20050257080 Santos et al. Nov 2005 A1
20050257090 Santos et al. Nov 2005 A1
20050258248 Silverbrook et al. Nov 2005 A1
20050262188 Mamou et al. Nov 2005 A1
20050262189 Mamou et al. Nov 2005 A1
20050262190 Mamou et al. Nov 2005 A1
20050262191 Mamou et al. Nov 2005 A1
20050262192 Mamou et al. Nov 2005 A1
20050262193 Mamou et al. Nov 2005 A1
20050262194 Mamou et al. Nov 2005 A1
20050262301 Jacobson et al. Nov 2005 A1
20050268071 Blandy et al. Dec 2005 A1
20050268290 Cognigni et al. Dec 2005 A1
20050275815 Silverbrook Dec 2005 A1
20050283644 Lorch et al. Dec 2005 A1
20050283659 Lamport et al. Dec 2005 A1
20050289246 Easton et al. Dec 2005 A1
20060007261 Silverbrook Jan 2006 A1
20060010195 Mamou et al. Jan 2006 A1
20060012652 Silverbrook Jan 2006 A1
20060015749 Mittal Jan 2006 A1
20060020790 Sprunk Jan 2006 A1
20060021029 Brickell et al. Jan 2006 A1
20060028516 Silverbrook Feb 2006 A1
20060036426 Barr et al. Feb 2006 A1
20060040667 Coppinger et al. Feb 2006 A9
20060041786 Janakiraman et al. Feb 2006 A1
20060050286 Silverbrook et al. Mar 2006 A1
20060052962 Shipton et al. Mar 2006 A1
20060053439 Sprunk Mar 2006 A1
20060055782 Silverbrook et al. Mar 2006 A1
20060056728 Silverbrook et al. Mar 2006 A1
20060059253 Goodman et al. Mar 2006 A1
20060061795 Walmsley Mar 2006 A1
20060067592 Walmsley et al. Mar 2006 A1
20060069717 Mamou et al. Mar 2006 A1
20060071951 Walmsley et al. Apr 2006 A1
20060071981 Plunkett Apr 2006 A1
20060072030 Silverbrook Apr 2006 A1
20060072952 Walmsley et al. Apr 2006 A1
20060074994 Smits Apr 2006 A1
20060076423 Silverbrook et al. Apr 2006 A1
20060077248 Silverbrook Apr 2006 A1
20060082609 Walmsley et al. Apr 2006 A1
20060087525 Jackson Pulver et al. Apr 2006 A1
20060092205 Jackson Pulver et al. May 2006 A1
20060092222 Jackson Pulver et al. May 2006 A1
20060095276 Axelrod et al. May 2006 A1
20060098042 Silverbrook et al. May 2006 A1
20060098044 Jackson Pulver et al. May 2006 A1
20060110011 Cohen et al. May 2006 A1
20060110199 Walmsley et al. May 2006 A1
20060112278 Cohen et al. May 2006 A1
20060112279 Cohen et al. May 2006 A1
20060112280 Cohen et al. May 2006 A1
20060122939 Cohen et al. Jun 2006 A1
20060123010 Landry et al. Jun 2006 A1
20060125854 Jackson Pulver et al. Jun 2006 A1
20060125855 Silverbrook et al. Jun 2006 A1
20060125857 Silverbrook et al. Jun 2006 A1
20060125858 Silverbrook et al. Jun 2006 A1
20060125859 Walmsley et al. Jun 2006 A1
20060125861 Silverbrook et al. Jun 2006 A1
20060125863 Silverbrook et al. Jun 2006 A1
20060125876 Walmsley et al. Jun 2006 A1
20060129806 Walmsley Jun 2006 A1
20060132512 Walmsley et al. Jun 2006 A1
20060132516 Walmsley et al. Jun 2006 A1
20060132518 Jackson Pulver et al. Jun 2006 A1
20060132521 Walmsley et al. Jun 2006 A1
20060132525 Walmsley et al. Jun 2006 A1
20060132822 Walmsley Jun 2006 A1
20060136570 Pandya Jun 2006 A1
20060136720 Armstrong et al. Jun 2006 A1
20060136725 Walmsley Jun 2006 A1
20060136781 Lamport Jun 2006 A1
20060139380 Walmsley et al. Jun 2006 A1
20060139386 Silverbrook et al. Jun 2006 A1
20060139387 Silverbrook et al. Jun 2006 A1
20060139388 Silverbrook et al. Jun 2006 A1
20060139681 Walmsley Jun 2006 A1
20060143350 Miloushev et al. Jun 2006 A1
20060143454 Walmsley Jun 2006 A1
20060143517 Douceur et al. Jun 2006 A1
20060146101 Silverbrook Jul 2006 A1
20060149945 Chaudhry et al. Jul 2006 A1
20060149946 Chaudhry et al. Jul 2006 A1
20060155930 Birrell et al. Jul 2006 A1
20060155931 Birrell et al. Jul 2006 A1
20060158519 Silverbrook Jul 2006 A1
20060164451 Pulver et al. Jul 2006 A1
20060164452 Walmsley et al. Jul 2006 A1
20060164453 Silverbrook et al. Jul 2006 A1
20060164454 Walmsley et al. Jul 2006 A1
20060164455 Silverbrook et al. Jul 2006 A1
20060164462 Silverbrook et al. Jul 2006 A1
20060178918 Mikurak Aug 2006 A1
20060181558 Walmsley et al. Aug 2006 A1
20060184935 Abels et al. Aug 2006 A1
20060184936 Abels et al. Aug 2006 A1
20060184937 Abels et al. Aug 2006 A1
20060187251 Pulver et al. Aug 2006 A1
20060195508 Bernardin et al. Aug 2006 A1
20060200632 Tremblay et al. Sep 2006 A1
20060212146 Johnson et al. Sep 2006 A1
20060212750 Denninghoff et al. Sep 2006 A1
20060214012 Silverbrook et al. Sep 2006 A1
20060218563 Grinstein et al. Sep 2006 A1
20060225065 Chandhok et al. Oct 2006 A1
20060230216 Fuente Oct 2006 A1
20060230407 Rosu et al. Oct 2006 A1
20060231627 Silverbrook et al. Oct 2006 A1
20060233367 Birrell et al. Oct 2006 A1
20060241921 Willis Oct 2006 A1
20060256944 Silverbrook Nov 2006 A1
20060259818 Howell et al. Nov 2006 A1
20060265508 Angel et al. Nov 2006 A1
20060274112 Jackson Pulver et al. Dec 2006 A1
20060274114 Silverbrook et al. Dec 2006 A1
20060282681 Scheidt et al. Dec 2006 A1
20060294312 Walmsley Dec 2006 A1
20070005919 van Riel Jan 2007 A1
20070006150 Walmsley Jan 2007 A9
20070011023 Silverbrook Jan 2007 A1
20070011650 Hage et al. Jan 2007 A1
20070019016 Silverbrook et al. Jan 2007 A1
20070035566 Silverbrook Feb 2007 A1
20070040856 Silverbrook Feb 2007 A1
20070046955 Silverbrook Mar 2007 A1
20070050367 Suganuma et al. Mar 2007 A1
20070050686 Keeton et al. Mar 2007 A1
20070055753 Robb Mar 2007 A1
20070067590 Savagaonkar et al. Mar 2007 A1
20070067630 Lenkov et al. Mar 2007 A1
20070074258 Wood et al. Mar 2007 A1
20070083491 Walmsley et al. Apr 2007 A1
20070088939 Baumberger et al. Apr 2007 A1
20070099683 Panther Trice et al. May 2007 A1
20070100834 Landry et al. May 2007 A1
20070120673 Rajapakse et al. May 2007 A1
20070128899 Mayer Jun 2007 A1
20070136579 Levy et al. Jun 2007 A1
20070174750 Borin Jul 2007 A1
20070174910 Zachman et al. Jul 2007 A1
20070174915 Gribble et al. Jul 2007 A1
20070180509 Swartz et al. Aug 2007 A1
20070200890 Silverbrook Aug 2007 A1
20070201845 Silverbrook et al. Aug 2007 A1
20070201846 Silverbrook et al. Aug 2007 A1
20070206611 Shokri et al. Sep 2007 A1
20070211285 Shipton Sep 2007 A1
20070226359 Gunduc et al. Sep 2007 A1
20070233880 Nieh et al. Oct 2007 A1
20070234070 Horning et al. Oct 2007 A1
20070234302 Suzuki et al. Oct 2007 A1
20070234337 Suzuki et al. Oct 2007 A1
20070234342 Flynn et al. Oct 2007 A1
20070234356 Martins et al. Oct 2007 A1
20070239804 Armstrong et al. Oct 2007 A1
20070240171 Biro et al. Oct 2007 A1
20070244937 Flynn et al. Oct 2007 A1
20070244962 Laadan et al. Oct 2007 A1
20070245334 Nieh et al. Oct 2007 A1
20070249320 Coppinger et al. Oct 2007 A1
20070254638 Coppinger et al. Nov 2007 A1
20070260733 Havemose et al. Nov 2007 A1
20070266368 Szpak et al. Nov 2007 A1
20070271445 Tremblay et al. Nov 2007 A1
20070271830 Holt et al. Nov 2007 A1
20070276879 Rothman et al. Nov 2007 A1
20070282926 Ben-Yehuda et al. Dec 2007 A1
20070282951 Selimis et al. Dec 2007 A1
20070283353 Tremblay et al. Dec 2007 A1
20070288247 Mackay Dec 2007 A1
20080005792 Larson et al. Jan 2008 A1
20080016249 Ellis et al. Jan 2008 A1
20080022276 Coppinger et al. Jan 2008 A1
20080022874 Silverbrook Jan 2008 A1
20080024642 Silverbrook et al. Jan 2008 A1
20080034201 Munger et al. Feb 2008 A1
20080034350 Conti Feb 2008 A1
20080040279 Coppinger et al. Feb 2008 A1
20080040477 Johnson et al. Feb 2008 A1
20080040783 Larson et al. Feb 2008 A1
20080040791 Munger et al. Feb 2008 A1
20080040792 Larson et al. Feb 2008 A1
20080046598 Johnson et al. Feb 2008 A1
20080046699 Pauw et al. Feb 2008 A1
20080052386 Johnson et al. Feb 2008 A1
20080052695 Dickenson et al. Feb 2008 A1
20080059214 Vinberg et al. Mar 2008 A1
20080060077 Cowan et al. Mar 2008 A1
20080062232 Silverbrook Mar 2008 A1
20080085107 Silverbrook Apr 2008 A1
20080087736 Silverbrook Apr 2008 A1
20080104531 Stambaugh May 2008 A1
20080104532 Stambaugh May 2008 A1
20080109756 Stambaugh May 2008 A1
20080109757 Stambaugh May 2008 A1
20080109758 Stambaugh May 2008 A1
20080109759 Stambaugh May 2008 A1
20080109760 Stambaugh May 2008 A1
20080109761 Stambaugh May 2008 A1
20080111818 Stambaugh May 2008 A1
20080120350 Grabowski et al. May 2008 A1
20080120620 Lett et al. May 2008 A1
20080126502 Holt May 2008 A1
20080126505 Holt May 2008 A1
20080126506 Holt May 2008 A1
20080129725 Stambaugh Jun 2008 A1
20080133688 Holt Jun 2008 A1
20080133692 Holt Jun 2008 A1
20080133694 Holt Jun 2008 A1
20080133869 Holt Jun 2008 A1
20080134161 Chamieh et al. Jun 2008 A1
20080140801 Holt Jun 2008 A1
20080140982 Holt Jun 2008 A1
20080141065 Okabe Jun 2008 A1
20080148262 Dice Jun 2008 A1
20080150963 Stambaugh Jun 2008 A1
20080155169 Hiltgen et al. Jun 2008 A1
20080155208 Hiltgen et al. Jun 2008 A1
20080155223 Hiltgen et al. Jun 2008 A1
20080162889 Cascaval et al. Jul 2008 A1
20080165253 Silverbrook Jul 2008 A9
20080165254 Silverbrook et al. Jul 2008 A1
20080172632 Stambaugh Jul 2008 A1
20080177994 Mayer Jul 2008 A1
20080183882 Flynn et al. Jul 2008 A1
20080184229 Rosu et al. Jul 2008 A1
20080189432 Abali et al. Aug 2008 A1
20080189468 Schmidt et al. Aug 2008 A1
20080189700 Schmidt et al. Aug 2008 A1
20080189769 Casado et al. Aug 2008 A1
20080195840 Archer et al. Aug 2008 A1
20080196026 Azagury et al. Aug 2008 A1
20080201602 Agarwal et al. Aug 2008 A1
20080215796 Lam et al. Sep 2008 A1
20080215920 Mayer et al. Sep 2008 A1
20080216073 Yates et al. Sep 2008 A1
20080216168 Larson et al. Sep 2008 A1
20080222415 Munger et al. Sep 2008 A1
20080222604 Murphy Sep 2008 A1
20080234998 Cohen et al. Sep 2008 A1
20080234999 Cohen et al. Sep 2008 A1
20080235000 Cohen et al. Sep 2008 A1
20080235001 Cohen et al. Sep 2008 A1
20080235002 Cohen et al. Sep 2008 A1
20080235711 Cohen et al. Sep 2008 A1
20080235756 Cohen et al. Sep 2008 A1
20080235764 Cohen et al. Sep 2008 A1
20080243935 Castro et al. Oct 2008 A1
20080244535 Nelson et al. Oct 2008 A1
20080244544 Neelakantam et al. Oct 2008 A1
20080244747 Gleichauf et al. Oct 2008 A1
20080250051 Grechanik et al. Oct 2008 A1
20080250265 Chang et al. Oct 2008 A1
20080253395 Pandya Oct 2008 A1
20080259711 Shipton et al. Oct 2008 A1
20080263114 Nath et al. Oct 2008 A1
20080263658 Michael et al. Oct 2008 A1
20080270199 Chess et al. Oct 2008 A1
20080270838 Dorai et al. Oct 2008 A1
20080288558 De Pauw et al. Nov 2008 A1
20080288747 Inglett et al. Nov 2008 A1
20080294937 Ueda Nov 2008 A1
20080295114 Argade et al. Nov 2008 A1
20080307258 Challenger et al. Dec 2008 A1
20080307414 Alpern et al. Dec 2008 A1
20080313345 Bernardin et al. Dec 2008 A1
20080313364 Flynn et al. Dec 2008 A1
20080320122 Houlihan et al. Dec 2008 A1
20080320123 Houlihan et al. Dec 2008 A1
20080320269 Houlihan et al. Dec 2008 A1
20080320594 Jiang Dec 2008 A1
20090006445 Shemenzon et al. Jan 2009 A1
20090006621 Ellis et al. Jan 2009 A1
20090006710 Daniel et al. Jan 2009 A1
20090006888 Bernhard et al. Jan 2009 A1
20090007063 Szpak et al. Jan 2009 A1
20090007105 Fries et al. Jan 2009 A1
20090007106 Araujo, Jr. et al. Jan 2009 A1
20090007111 Nelson et al. Jan 2009 A1
20090019262 Tashiro et al. Jan 2009 A1
20090019538 Pandya Jan 2009 A1
20090024851 Andrade Jan 2009 A1
20090031307 Chodroff et al. Jan 2009 A1
20090031309 Lev Jan 2009 A1
20090031310 Lev et al. Jan 2009 A1
20090036125 Coppinger et al. Feb 2009 A1
20090037329 Coppinger et al. Feb 2009 A1
20090037330 Coppinger et al. Feb 2009 A1
20090037585 Miloushev et al. Feb 2009 A1
20090037672 Colbert et al. Feb 2009 A1
20090037680 Colbert et al. Feb 2009 A1
20090042552 Coppinger et al. Feb 2009 A1
20090043700 Coppinger et al. Feb 2009 A1
20090044186 Biro Feb 2009 A1
20090044265 Ghosh et al. Feb 2009 A1
20090063665 Bagepalli et al. Mar 2009 A1
20090064094 Burka et al. Mar 2009 A1
20090064557 Hughes et al. Mar 2009 A1
20090077329 Wood et al. Mar 2009 A1
20090094603 Hiltgen et al. Apr 2009 A1
20090094673 Seguin et al. Apr 2009 A1
20090106256 Safari et al. Apr 2009 A1
20090106424 Safari et al. Apr 2009 A1
20090112616 Jung et al. Apr 2009 A1
20090112617 Jung et al. Apr 2009 A1
20090112620 Jung et al. Apr 2009 A1
20090112621 Jung et al. Apr 2009 A1
20090113109 Nelson et al. Apr 2009 A1
20090113420 Pawlowski Apr 2009 A1
20090113423 Hiltgen et al. Apr 2009 A1
20090113528 Ananda et al. Apr 2009 A1
20090118593 Jung et al. May 2009 A1
20090119154 Jung et al. May 2009 A1
20090119493 Venkitachalam et al. May 2009 A1
20090119684 Mahalingam et al. May 2009 A1
20090125904 Nelson May 2009 A1
20090132275 Jung et al. May 2009 A1
20090135215 Silverbrook et al. May 2009 A1
20090135232 Silverbrook et al. May 2009 A1
20090138945 Savchuk May 2009 A1
20090150883 Tripathi et al. Jun 2009 A1
20090150885 Safari et al. Jun 2009 A1
20090157882 Kashyap Jun 2009 A1
20090158260 Moon et al. Jun 2009 A1
20090164031 Johnson et al. Jun 2009 A1
20090164501 de Moura et al. Jun 2009 A1
20090164848 Heidasch et al. Jun 2009 A1
20090164981 Heidasch et al. Jun 2009 A1
20090165139 Yerazunis et al. Jun 2009 A1
20090182964 Greiner et al. Jul 2009 A1
20090182966 Greiner et al. Jul 2009 A1
20090182971 Greiner et al. Jul 2009 A1
20090182972 Greiner et al. Jul 2009 A1
20090182973 Greiner et al. Jul 2009 A1
20090182974 Greiner et al. Jul 2009 A1
20090182975 Greiner et al. Jul 2009 A1
20090185014 Silverbrook Jul 2009 A1
20090187724 Greiner et al. Jul 2009 A1
20090187728 Greiner et al. Jul 2009 A1
20090187732 Greiner et al. Jul 2009 A1
20090193214 Greiner et al. Jul 2009 A1
20090198762 Arimilli et al. Aug 2009 A1
20090198949 Kuligowski et al. Aug 2009 A1
20090204785 Yates, Jr. et al. Aug 2009 A1
20090204964 Foley et al. Aug 2009 A1
20090204966 Johnson et al. Aug 2009 A1
20090207255 Silverbrook Aug 2009 A1
20090208910 Brueckner et al. Aug 2009 A1
20090210769 Casper et al. Aug 2009 A1
20090213150 Silverbrook Aug 2009 A1
20090216910 Duchesneau Aug 2009 A1
20090216984 Gainey, Jr. et al. Aug 2009 A1
20090217021 Goodson et al. Aug 2009 A1
20090217050 Amiel et al. Aug 2009 A1
20090222496 Liu et al. Sep 2009 A1
20090222558 Xu et al. Sep 2009 A1
20090228889 Yoshida Sep 2009 A1
20090230686 Catlin Sep 2009 A1
20090242636 Silverbrook Oct 2009 A1
20090244215 Silverbrook et al. Oct 2009 A1
20090244292 Silverbrook et al. Oct 2009 A1
20090248611 Xu et al. Oct 2009 A1
20090249049 Weissman et al. Oct 2009 A1
20090249357 Chanda et al. Oct 2009 A1
20090249488 Robinson et al. Oct 2009 A1
20090251737 Silverbrook Oct 2009 A1
20090257102 Silverbrook Oct 2009 A1
20090259612 Hanson Oct 2009 A1
20090262149 Silverbrook Oct 2009 A1
20090262741 Jungck et al. Oct 2009 A1
20090262929 Walmsley Oct 2009 A1
20090278901 Silverbrook Nov 2009 A1
20090282101 Lim et al. Nov 2009 A1
20090282386 Moir et al. Nov 2009 A1
20090284279 Walmsley et al. Nov 2009 A1
20090288075 Song et al. Nov 2009 A1
20090288084 Astete et al. Nov 2009 A1
20090292858 Lambeth et al. Nov 2009 A1
20090300528 Stambaugh Dec 2009 A1
20090307528 Byers et al. Dec 2009 A1
20090313620 Sedukhin et al. Dec 2009 A1
20090316581 Kashyap et al. Dec 2009 A1
20090319672 Reisman Dec 2009 A1
20090319738 Ben-Yehuda et al. Dec 2009 A1
20090320073 Reisman Dec 2009 A1
20090327471 Astete et al. Dec 2009 A1
20100005258 Westenberg Jan 2010 A1
20100010968 Redlich et al. Jan 2010 A1
20100011127 Johnson et al. Jan 2010 A1
20100011238 Nakamura et al. Jan 2010 A1
20100011243 Locasto et al. Jan 2010 A1
20100011446 Klucher et al. Jan 2010 A1
20100023308 Willis et al. Jan 2010 A1
20100023703 Christie et al. Jan 2010 A1
20100023704 Christie et al. Jan 2010 A1
20100023706 Christie et al. Jan 2010 A1
20100023707 Hohmuth et al. Jan 2010 A1
20100030878 Grabowski et al. Feb 2010 A1
20100031358 Elovici et al. Feb 2010 A1
20100037096 Bum et al. Feb 2010 A1
20100037206 Larimore et al. Feb 2010 A1
20100037235 Larimore et al. Feb 2010 A1
20100042846 Trotter et al. Feb 2010 A1
20100047760 Best et al. Feb 2010 A1
20100063613 Popp Mar 2010 A1
20100070678 Zhang et al. Mar 2010 A1
20100070935 Bist et al. Mar 2010 A1
20100070940 Bist et al. Mar 2010 A1
20100070978 Chawla et al. Mar 2010 A1
20100071068 Bauschert et al. Mar 2010 A1
20100076604 Johnson et al. Mar 2010 A1
20100077160 Liu et al. Mar 2010 A1
20100079600 Silverbrook Apr 2010 A1
20100082922 George et al. Apr 2010 A1
20100091116 Silverbrook et al. Apr 2010 A1
20100094948 Ganesh et al. Apr 2010 A1
20100095074 Ganesh et al. Apr 2010 A1
20100095075 Ganesh et al. Apr 2010 A1
20100095100 Darrington et al. Apr 2010 A1
20100095152 Darrington et al. Apr 2010 A1
20100103837 Jungck et al. Apr 2010 A1
20100107113 Innes et al. Apr 2010 A1
20100107158 Chen et al. Apr 2010 A1
20100122052 Waldspurger et al. May 2010 A1
20100122073 Narayanaswamy et al. May 2010 A1
20100138830 Astete et al. Jun 2010 A1
20100138841 Dice et al. Jun 2010 A1
20100153662 Vick et al. Jun 2010 A1
20100153674 Park et al. Jun 2010 A1
20100153690 Vick et al. Jun 2010 A1
20100153776 Vick et al. Jun 2010 A1
20100154051 Bauer Jun 2010 A1
20100161559 Patil et al. Jun 2010 A1
20100161750 Pandya Jun 2010 A1
20100162249 Shpeisman et al. Jun 2010 A1
20100162250 Adl-Tabatabai et al. Jun 2010 A1
20100169537 Nelson Jul 2010 A1
20100169894 Sheaffer et al. Jul 2010 A1
20100170951 Silverbrook et al. Jul 2010 A1
20100174770 Pandya Jul 2010 A1
20100174802 Chan et al. Jul 2010 A1
20100180275 Neogi et al. Jul 2010 A1
20100185590 D'Angelo et al. Jul 2010 A1
20100192220 Heizmann et al. Jul 2010 A1
20100211663 Barboy et al. Aug 2010 A1
20100211681 Chan et al. Aug 2010 A1
20100223499 Panigrahy et al. Sep 2010 A1
20100223616 De et al. Sep 2010 A1
20100235647 Buer Sep 2010 A1
20100241673 Wu et al. Sep 2010 A1
20100241726 Wu Sep 2010 A1
20100241807 Wu et al. Sep 2010 A1
20100251018 Tamura Sep 2010 A1
20100251031 Nieh et al. Sep 2010 A1
20100251363 Todorovic Sep 2010 A1
20100268691 Grinstein et al. Oct 2010 A1
20100274767 Irisawa et al. Oct 2010 A1
20100274890 Patel et al. Oct 2010 A1
20100280996 Gross et al. Nov 2010 A1
20100281195 Daniel et al. Nov 2010 A1
20100281239 Sudhakar Nov 2010 A1
20100287280 Sivan Nov 2010 A1
20100305720 Doll et al. Dec 2010 A1
20100305721 Kostadinov et al. Dec 2010 A1
20100306773 Lee et al. Dec 2010 A1
20100315516 Silverbrook et al. Dec 2010 A1
20100318991 Venkitachalam et al. Dec 2010 A1
20100322071 Avdanin et al. Dec 2010 A1
20100328064 Rogel Dec 2010 A1
20100330953 Rogel et al. Dec 2010 A1
20100330961 Rogel Dec 2010 A1
20100332630 Harlow Dec 2010 A1
20100332635 Rogel et al. Dec 2010 A1
20100332889 Shneorson et al. Dec 2010 A1
20100333088 Rogel et al. Dec 2010 A1
20110004868 Bharadwaj Jan 2011 A1
20110004935 Moffie et al. Jan 2011 A1
20110010711 Patwardhan Jan 2011 A1
20110016453 Grechanik et al. Jan 2011 A1
20110019647 Fujino Jan 2011 A1
20110023050 Strom et al. Jan 2011 A1
20110029970 Arasaratnam Feb 2011 A1
20110032830 Merwe et al. Feb 2011 A1
20110035358 Naik Feb 2011 A1
20110035513 Jevans et al. Feb 2011 A1
20110035733 Horning et al. Feb 2011 A1
20110041006 Fowler Feb 2011 A1
20110047376 Mittal Feb 2011 A1
20110047618 Evans et al. Feb 2011 A1
20110061043 Rydh et al. Mar 2011 A1
20110066786 Colbert Mar 2011 A1
20110067014 Song et al. Mar 2011 A1
20110072430 Mani Mar 2011 A1
20110074850 Walmsley et al. Mar 2011 A1
20110082996 Wester et al. Apr 2011 A1
20110087779 Martin et al. Apr 2011 A1
20110093700 Mittal Apr 2011 A1
20110096930 Walmsley Apr 2011 A1
20110113208 Jouppi et al. May 2011 A1
20110122261 Silverbrook May 2011 A1
20110125951 Youngworth May 2011 A1
20110131183 Chandhok et al. Jun 2011 A1
20110131402 Mittal Jun 2011 A1
20110153992 Srinivas et al. Jun 2011 A1
20110156914 Sheharri et al. Jun 2011 A1
20110161730 Van Der Merwe et al. Jun 2011 A1
20110161988 Kashyap Jun 2011 A1
20110162076 Song et al. Jun 2011 A1
20110167087 Larson et al. Jul 2011 A1
20110167194 Scales et al. Jul 2011 A1
20110167195 Scales et al. Jul 2011 A1
20110167196 Scales et al. Jul 2011 A1
20110167298 Lee Jul 2011 A1
20110167416 Sager et al. Jul 2011 A1
20110173441 Bagepalli et al. Jul 2011 A1
20110173615 Easton et al. Jul 2011 A1
20110173698 Polyakov et al. Jul 2011 A1
20110178983 Bernhard et al. Jul 2011 A1
20110179399 Bekiroglu et al. Jul 2011 A1
20110184993 Chawla et al. Jul 2011 A1
20110185053 Larson et al. Jul 2011 A1
20110185169 Munger et al. Jul 2011 A1
20110185292 Chawla et al. Jul 2011 A1
20110185355 Chawla et al. Jul 2011 A1
20110197022 Green et al. Aug 2011 A1
20110197097 Beaty et al. Aug 2011 A1
20110202927 Miloushev et al. Aug 2011 A1
20110208908 Chou et al. Aug 2011 A1
20110209151 Chung et al. Aug 2011 A1
20110211080 Silverbrook Sep 2011 A1
20110214050 Stambaugh Sep 2011 A1
20110218966 Barnes et al. Sep 2011 A1
20110218968 Liu et al. Sep 2011 A1
20110219419 Reisman Sep 2011 A1
20110225419 Munger et al. Sep 2011 A1
20110231825 Grechanik et al. Sep 2011 A1
20110238775 Wu et al. Sep 2011 A1
20110251868 Mikurak Oct 2011 A1
20110258625 Waldspurger et al. Oct 2011 A1
20110258692 Morrison et al. Oct 2011 A1
20110264729 Kulgavin Oct 2011 A1
20110270998 Larson et al. Nov 2011 A1
20110271136 Abbot et al. Nov 2011 A1
20110276962 Chambers et al. Nov 2011 A1
20110278355 Silverbrook et al. Nov 2011 A1
20110280387 Soo et al. Nov 2011 A1
20110283246 Bist et al. Nov 2011 A1
20110283262 Ceze et al. Nov 2011 A1
20110289345 Agesen et al. Nov 2011 A1
20110289507 Khan et al. Nov 2011 A1
20110296113 Elnozahy Dec 2011 A1
20110296241 Elnozahy Dec 2011 A1
20110296245 Alberi et al. Dec 2011 A1
20110296440 Laurich et al. Dec 2011 A1
20110307897 Atterbury et al. Dec 2011 A1
20110310209 Silverbrook Dec 2011 A1
20110320882 Beaty et al. Dec 2011 A1
20120005461 Moir et al. Jan 2012 A1
20120005672 Cervantes et al. Jan 2012 A1
20120011341 Greiner et al. Jan 2012 A1
20120011401 Ranganathan et al. Jan 2012 A1
20120011504 Ahmad et al. Jan 2012 A1
20120011508 Ahmad Jan 2012 A1
20120013408 Cortadella et al. Jan 2012 A1
20120017213 Hunt et al. Jan 2012 A1
20120023209 Fletcher et al. Jan 2012 A1
20120023313 Tashiro et al. Jan 2012 A1
20120030653 Porras et al. Feb 2012 A1
20120030659 Porras et al. Feb 2012 A1
20120030661 Porras et al. Feb 2012 A1
20120042034 Goggin et al. Feb 2012 A1
20120042086 Larson et al. Feb 2012 A1
20120054332 Sahu et al. Mar 2012 A1
20120054345 Sahu et al. Mar 2012 A1
20120054408 Dong et al. Mar 2012 A1
20120054409 Block et al. Mar 2012 A1
20120054412 Gainey, Jr. et al. Mar 2012 A1
20120060165 Clarke Mar 2012 A1
20120066676 Dong et al. Mar 2012 A1
20120069131 Abelow Mar 2012 A1
20120079368 Abdelaziz et al. Mar 2012 A1
20120084393 Williams et al. Apr 2012 A1
20120084520 Chou et al. Apr 2012 A1
20120084782 Chou et al. Apr 2012 A1
20120089410 Mikurak Apr 2012 A1
20120089485 Williams et al. Apr 2012 A1
20120089694 Pandya Apr 2012 A1
20120089971 Williams et al. Apr 2012 A1
20120096134 Suit Apr 2012 A1
20120096158 Astete et al. Apr 2012 A1
20120096282 Henry et al. Apr 2012 A1
20120096541 Larson et al. Apr 2012 A1
20120102204 Larson et al. Apr 2012 A1
20120102206 Larson et al. Apr 2012 A1
20120102369 Hiltunen et al. Apr 2012 A1
20120110103 Larson et al. May 2012 A1
20120110185 Ganesan et al. May 2012 A1
20120110186 Kapur et al. May 2012 A1
20120113293 Silverbrook May 2012 A1
20120117237 Larson et al. May 2012 A1
20120117382 Larson et al. May 2012 A1
20120117610 Pandya May 2012 A1
20120124285 Soran et al. May 2012 A1
20120137106 Greiner et al. May 2012 A1
20120137119 Doerr et al. May 2012 A1
20120137286 Schimpf et al. May 2012 A1
20120144005 Quintard Jun 2012 A1
20120144153 Greiner et al. Jun 2012 A1
20120144167 Yates, Jr. et al. Jun 2012 A1
20120144232 Griffith et al. Jun 2012 A1
20120144233 Griffith et al. Jun 2012 A1
20120151225 Huang et al. Jun 2012 A1
20120158610 Botvinick et al. Jun 2012 A1
20120159101 Miyoshi Jun 2012 A1
20120159462 Leibman et al. Jun 2012 A1
20120159478 Spradlin et al. Jun 2012 A1
20120164613 Jung et al. Jun 2012 A1
20120166758 Greiner et al. Jun 2012 A1
20120173732 Sullivan Jul 2012 A1
20120174104 Neogi et al. Jul 2012 A1
20120179446 Tylutki Jul 2012 A1
20120185855 Cervantes et al. Jul 2012 A1
20120191908 North et al. Jul 2012 A1
20120191942 Blandy et al. Jul 2012 A1
20120192142 Schimpf et al. Jul 2012 A1
20120192207 Kashyap Jul 2012 A1
20120204061 Agesen et al. Aug 2012 A1
20120204266 Yoo Aug 2012 A1
20120209822 Prabhakar et al. Aug 2012 A1
20120210042 Lim et al. Aug 2012 A1
20120216045 Seguin et al. Aug 2012 A1
20120216198 Easton et al. Aug 2012 A1
20120218901 Jungck et al. Aug 2012 A1
20120221803 Stabrawa et al. Aug 2012 A1
20120222042 Chess et al. Aug 2012 A1
20120226699 Lillibridge Sep 2012 A1
20120226795 Larson et al. Sep 2012 A1
20120226870 Elnozahy Sep 2012 A1
20120226939 Elnozahy Sep 2012 A1
20120226947 Alberi et al. Sep 2012 A1
20120227041 Lambeth et al. Sep 2012 A1
20120232947 McLachlan et al. Sep 2012 A1
20120233547 McLachlan Sep 2012 A1
20120239624 Barnes et al. Sep 2012 A1
20120239739 Manglik et al. Sep 2012 A1
20120246513 Bum et al. Sep 2012 A9
20120246638 He et al. Sep 2012 A1
20120246727 Elovici et al. Sep 2012 A1
20120254286 Harlow Oct 2012 A1
20120254355 Kihara Oct 2012 A1
20120254862 Dong Oct 2012 A1
20120254888 Kalogeropulos et al. Oct 2012 A1
20120259722 Mikurak Oct 2012 A1
20120260123 Madampath Oct 2012 A1
20120265959 Le et al. Oct 2012 A1
20120266018 Tanaka Oct 2012 A1
20120266132 Coppinger et al. Oct 2012 A1
20120272240 Starks et al. Oct 2012 A1
20120278278 Wester et al. Nov 2012 A1
20120278573 Colbert et al. Nov 2012 A1
20120278793 Jalan et al. Nov 2012 A1
20120284477 Gainey, Jr. et al. Nov 2012 A1
20120284699 Van Der Merwe et al. Nov 2012 A1
20120284714 Venkitachalam et al. Nov 2012 A1
20120284716 Martins et al. Nov 2012 A1
20120290820 Olson et al. Nov 2012 A1
20120290950 Rapaport et al. Nov 2012 A1
20120297246 Liu et al. Nov 2012 A1
20120310888 Kuznetzov et al. Dec 2012 A1
20120311180 Barkey et al. Dec 2012 A1
20120311580 Emelianov et al. Dec 2012 A1
20120324378 Stambaugh Dec 2012 A1
20120324417 Somani et al. Dec 2012 A1
20120324447 Huetter et al. Dec 2012 A1
20120324448 Huetter et al. Dec 2012 A1
20120324449 Huetter et al. Dec 2012 A1
20120324453 Chandramouli et al. Dec 2012 A1
20120331444 Szpak et al. Dec 2012 A1
20130007090 Sankararaman Jan 2013 A1
20130007409 Ganesh et al. Jan 2013 A1
20130007735 Bookman et al. Jan 2013 A1
20130007744 Arasaratnam Jan 2013 A1
20130010125 Silverbrook Jan 2013 A1
20130010128 Silverbrook Jan 2013 A1
20130010129 Silverbrook Jan 2013 A1
20130010135 Silverbrook Jan 2013 A1
20130010136 Silverbrook Jan 2013 A1
20130010150 Silverbrook Jan 2013 A1
20130010151 Silverbrook Jan 2013 A1
20130010159 Silverbrook Jan 2013 A1
20130010167 Silverbrook Jan 2013 A1
20130013795 Larson et al. Jan 2013 A1
20130013839 Silverbrook Jan 2013 A1
20130013893 Silverbrook Jan 2013 A1
20130013953 Eck et al. Jan 2013 A1
20130014226 Larson et al. Jan 2013 A1
20130014227 Larson et al. Jan 2013 A1
20130014228 Munger et al. Jan 2013 A1
20130014259 Gribble et al. Jan 2013 A1
20130015239 Silverbrook Jan 2013 A1
20130016232 Silverbrook Jan 2013 A1
20130016233 Silverbrook Jan 2013 A1
20130016235 Silverbrook Jan 2013 A1
20130016236 Silverbrook Jan 2013 A1
20130016247 Silverbrook Jan 2013 A1
20130016248 Silverbrook Jan 2013 A1
20130016266 Silverbrook Jan 2013 A1
20130019091 Munger et al. Jan 2013 A1
20130019243 Schmidt et al. Jan 2013 A1
20130019280 Larson et al. Jan 2013 A1
20130021443 Silverbrook Jan 2013 A1
20130021444 Silverbrook Jan 2013 A1
20130021482 Silverbrook Jan 2013 A1
20130024645 Cheriton et al. Jan 2013 A1
20130024660 Silverbrook Jan 2013 A1
20130024855 North Jan 2013 A1
20130024937 Glew et al. Jan 2013 A1
20130024939 Glew et al. Jan 2013 A1
20130024940 Hutchins et al. Jan 2013 A1
20130031331 Cheriton et al. Jan 2013 A1
20130036192 Fausak Feb 2013 A1
20130036403 Geist Feb 2013 A1
20130036451 Fausak Feb 2013 A1
20130042150 McNeeney Feb 2013 A1
20130042153 McNeeney Feb 2013 A1
20130046598 Roberts Feb 2013 A1
20130046722 Hanson Feb 2013 A1
20130046948 Vaghani et al. Feb 2013 A1
20130047154 Mehta Feb 2013 A1
20130054807 Sherwood et al. Feb 2013 A1
20130054820 Reisman Feb 2013 A1
20130055009 Patterson et al. Feb 2013 A1
20130055315 Reisman Feb 2013 A1
20130060612 Hurd Mar 2013 A1
20130060947 Nelson Mar 2013 A1
20130060963 Barkey et al. Mar 2013 A1
20130061264 Reisman Mar 2013 A1
20130061273 Reisman Mar 2013 A1
20130061322 Sethumadhavan et al. Mar 2013 A1
20130063568 Silverbrook Mar 2013 A1
20130064241 Larson et al. Mar 2013 A1
20130067103 Larson et al. Mar 2013 A1
20130067224 Larson et al. Mar 2013 A1
20130067277 Mummidi Mar 2013 A1
20130067526 Reisman Mar 2013 A1
20130073072 Popp Mar 2013 A1
20130073738 Reisman Mar 2013 A1
20130073778 Hunter et al. Mar 2013 A1
20130073823 Hunter et al. Mar 2013 A1
20130073905 Van Der Merwe et al. Mar 2013 A1
20130074065 McNeeney et al. Mar 2013 A1
20130074129 Reisman Mar 2013 A1
20130080732 Nellans et al. Mar 2013 A1
20130081134 Glew et al. Mar 2013 A1
20130086147 Kashyap Apr 2013 A1
20130086347 Liu et al. Apr 2013 A1
20130086367 Gschwind et al. Apr 2013 A1
20130091275 Safari et al. Apr 2013 A1
20130091335 Mulcahy et al. Apr 2013 A1
20130097120 Mummidi Apr 2013 A1
20130097369 Talagala et al. Apr 2013 A1
20130097398 Waldspurger et al. Apr 2013 A1
20130097706 Titonis et al. Apr 2013 A1
20130103817 Koponen et al. Apr 2013 A1
20130103818 Koponen et al. Apr 2013 A1
20130104199 Sprunk Apr 2013 A1
20130110490 Letz et al. May 2013 A1
20130111018 Ammons et al. May 2013 A1
20130111473 Ammons et al. May 2013 A1
20130117337 Dunham May 2013 A1
20130117359 Husain et al. May 2013 A1
20130121154 Guay et al. May 2013 A1
20130124479 Namjoshi et al. May 2013 A1
20130137430 Coppinger et al. May 2013 A1
20130138695 Stanev May 2013 A1
20130139262 Glew et al. May 2013 A1
20130145002 Kannan et al. Jun 2013 A1
20130145008 Kannan et al. Jun 2013 A1
20130151494 Dhamankar et al. Jun 2013 A1
20130151846 Baumann et al. Jun 2013 A1
20130151848 Baumann et al. Jun 2013 A1
20130152199 Capalik Jun 2013 A1
20130159649 Sherwood et al. Jun 2013 A1
20130159712 Sigworth et al. Jun 2013 A1
20130166716 Safari et al. Jun 2013 A1
20130166886 Sasanka et al. Jun 2013 A1
20130166951 Burn et al. Jun 2013 A1
20130169830 Silverbrook Jul 2013 A1
20130170334 Koinuma et al. Jul 2013 A1
20130179289 Calder et al. Jul 2013 A1
20130179371 Jain et al. Jul 2013 A1
20130179574 Calder et al. Jul 2013 A1
20130179673 Innes et al. Jul 2013 A1
20130179729 Chiu et al. Jul 2013 A1
20130179881 Calder et al. Jul 2013 A1
20130179894 Calder et al. Jul 2013 A1
20130179895 Calder et al. Jul 2013 A1
20130185480 Newell et al. Jul 2013 A1
20130185530 Puttaswamy Naga et al. Jul 2013 A1
20130185667 Harper et al. Jul 2013 A1
20130185716 Yin et al. Jul 2013 A1
20130186953 Silverbrook et al. Jul 2013 A1
20130198334 Ikenaga et al. Aug 2013 A1
20130198459 Joshi et al. Aug 2013 A1
20130198740 Arroyo et al. Aug 2013 A1
20130198742 Kumar et al. Aug 2013 A1
20130204917 Wang et al. Aug 2013 A1
20130204990 Skjolsvold et al. Aug 2013 A1
20130204991 Skjolsvold et al. Aug 2013 A1
20130208623 Koponen et al. Aug 2013 A1
20130211549 Thakkar et al. Aug 2013 A1
20130212068 Talius et al. Aug 2013 A1
20130212148 Koponen et al. Aug 2013 A1
20130212162 Somadder Aug 2013 A1
20130212205 Flockhart et al. Aug 2013 A1
20130212235 Fulton et al. Aug 2013 A1
20130212243 Thakkar et al. Aug 2013 A1
20130212244 Koponen et al. Aug 2013 A1
20130212245 Koponen et al. Aug 2013 A1
20130212246 Koponen et al. Aug 2013 A1
20130212321 Talagala et al. Aug 2013 A1
20130212592 Strom et al. Aug 2013 A1
20130218915 Billau et al. Aug 2013 A1
20130219037 Thakkar et al. Aug 2013 A1
20130219078 Padmanabhan et al. Aug 2013 A1
20130219183 Billau et al. Aug 2013 A1
20130219280 Weinstein et al. Aug 2013 A1
20130227236 Flynn et al. Aug 2013 A1
20130232343 Horning et al. Sep 2013 A1
20130238559 Bushman Sep 2013 A1
20130238690 Kashyap Sep 2013 A1
20130246355 Nelson et al. Sep 2013 A1
20130246511 Brown et al. Sep 2013 A1
20130246843 Havemose et al. Sep 2013 A1
20130247070 Larimore et al. Sep 2013 A1
20130254369 Rogel et al. Sep 2013 A1
20130254459 Laplace et al. Sep 2013 A1
20130262587 Munger et al. Oct 2013 A1
20130263132 Colbert et al. Oct 2013 A1
20130263220 Larson et al. Oct 2013 A1
20130263247 Jungck et al. Oct 2013 A1
20130268357 Heath Oct 2013 A1
20130268683 Larson et al. Oct 2013 A1
20130268932 Park et al. Oct 2013 A1
20130275391 Batwara et al. Oct 2013 A1
20130275534 Larson et al. Oct 2013 A1
20130275612 Voss et al. Oct 2013 A1
20130275808 McNeeney et al. Oct 2013 A1
20130275973 Greenfield et al. Oct 2013 A1
20130276056 Epstein Oct 2013 A1
20130282994 Wires et al. Oct 2013 A1
20130290506 Astete et al. Oct 2013 A1
20130290671 Greiner et al. Oct 2013 A1
20130290781 Chen et al. Oct 2013 A1
20130290782 Chen et al. Oct 2013 A1
20130290960 Astete et al. Oct 2013 A1
20130297854 Gupta et al. Nov 2013 A1
20130297855 Gupta et al. Nov 2013 A1
20130297894 Cohen et al. Nov 2013 A1
20130298135 Hiltunen et al. Nov 2013 A1
20130298251 Mittal Nov 2013 A1
20130304742 Roman et al. Nov 2013 A1
20130305023 Gainey, Jr. et al. Nov 2013 A1
20130305242 Wang et al. Nov 2013 A1
20130305246 Goggin et al. Nov 2013 A1
20130305247 Easton et al. Nov 2013 A1
20130306276 Duchesneau Nov 2013 A1
20130311607 Larson et al. Nov 2013 A1
20130311767 Larson et al. Nov 2013 A1
20130311774 Larson et al. Nov 2013 A1
20130311910 Stambaugh Nov 2013 A1
20130311992 Fuente et al. Nov 2013 A1
20130318341 Bagepalli et al. Nov 2013 A1
20130318521 Monaghan et al. Nov 2013 A1
20130322335 Smith Dec 2013 A1
20130325450 Levien et al. Dec 2013 A1
20130325451 Levien et al. Dec 2013 A1
20130325452 Levien et al. Dec 2013 A1
20130325453 Levien et al. Dec 2013 A1
20130325704 Gorman et al. Dec 2013 A1
20130325934 Fausak et al. Dec 2013 A1
20130325998 Hormuth et al. Dec 2013 A1
20130332610 Beveridge Dec 2013 A1
20130332660 Talagala et al. Dec 2013 A1
20130332686 Ishizawa et al. Dec 2013 A1
20130332719 Hormuth et al. Dec 2013 A1
20130339479 Hormuth et al. Dec 2013 A1
20130339714 Hormuth et al. Dec 2013 A1
20130345971 Stamm et al. Dec 2013 A1
20130346988 Bruno et al. Dec 2013 A1
20140006482 Raghu et al. Jan 2014 A1
20140006580 Raghu Jan 2014 A1
20140006581 Raghu Jan 2014 A1
20140007089 Bosch et al. Jan 2014 A1
20140007178 Gillum et al. Jan 2014 A1
20140013059 Joshi et al. Jan 2014 A1
20140013311 Garrett et al. Jan 2014 A1
20140032767 Nelson Jan 2014 A1
20140053269 Ghosh et al. Feb 2014 A1
20140056577 Ogawa et al. Feb 2014 A1
20140059333 Dixon et al. Feb 2014 A1
20140059362 Huang et al. Feb 2014 A1
20140082327 Ghose Mar 2014 A1
20140082329 Ghose Mar 2014 A1
20140095821 Yang et al. Apr 2014 A1
20140108726 Laurich et al. Apr 2014 A1
20140108786 Kreft Apr 2014 A1
20140108864 Madampath Apr 2014 A1
20140115596 Khan et al. Apr 2014 A1
20140142904 Drees et al. May 2014 A1
20140142905 Drees et al. May 2014 A1
20140146055 Bala et al. May 2014 A1
20140149492 Ananthanarayanan et al. May 2014 A1
20140149494 Markley et al. May 2014 A1
20140149591 Bhattacharya et al. May 2014 A1
20140149983 Bonilla et al. May 2014 A1
20140172728 Lenkov et al. Jun 2014 A1
20140172944 Newton et al. Jun 2014 A1
20140172951 Varney et al. Jun 2014 A1
20140172952 Varney et al. Jun 2014 A1
20140172956 Varney et al. Jun 2014 A1
20140172970 Newton et al. Jun 2014 A1
20140173023 Varney et al. Jun 2014 A1
20140173029 Varney et al. Jun 2014 A1
20140173030 Varney et al. Jun 2014 A1
20140173038 Newton et al. Jun 2014 A1
20140173039 Newton et al. Jun 2014 A1
20140173040 Newton et al. Jun 2014 A1
20140173041 Newton et al. Jun 2014 A1
20140173042 Newton et al. Jun 2014 A1
20140173043 Varney et al. Jun 2014 A1
20140173044 Varney et al. Jun 2014 A1
20140173045 Crowder et al. Jun 2014 A1
20140173046 Crowder et al. Jun 2014 A1
20140173047 Crowder et al. Jun 2014 A1
20140173048 Crowder et al. Jun 2014 A1
20140173052 Newton et al. Jun 2014 A1
20140173053 Varney et al. Jun 2014 A1
20140173054 Varney et al. Jun 2014 A1
20140173061 Lipstone et al. Jun 2014 A1
20140173062 Lipstone et al. Jun 2014 A1
20140173064 Newton et al. Jun 2014 A1
20140173066 Newton et al. Jun 2014 A1
20140173067 Newton et al. Jun 2014 A1
20140173077 Newton et al. Jun 2014 A1
20140173079 Newton et al. Jun 2014 A1
20140173087 Varney et al. Jun 2014 A1
20140173088 Varney et al. Jun 2014 A1
20140173091 Lipstone et al. Jun 2014 A1
20140173097 Newton et al. Jun 2014 A1
20140173115 Varney et al. Jun 2014 A1
20140173131 Newton et al. Jun 2014 A1
20140173132 Varney et al. Jun 2014 A1
20140173135 Varney et al. Jun 2014 A1
20140181833 Bird et al. Jun 2014 A1
20140195480 Talagala et al. Jul 2014 A1
20140195564 Talagala et al. Jul 2014 A1
20140201503 Tashiro et al. Jul 2014 A1
20140201757 Bird et al. Jul 2014 A1
20140201838 Varsanyi et al. Jul 2014 A1
20140207871 Miloushev et al. Jul 2014 A1
20140208153 Havemose Jul 2014 A1
20140222610 Mikurak Aug 2014 A1
20140222946 Lipstone et al. Aug 2014 A1
20140222977 Varney et al. Aug 2014 A1
20140222984 Varney et al. Aug 2014 A1
20140223002 Varney et al. Aug 2014 A1
20140223003 Varney et al. Aug 2014 A1
20140223015 Varney et al. Aug 2014 A1
20140223016 Varney et al. Aug 2014 A1
20140223017 Lipstone et al. Aug 2014 A1
20140223018 Varney et al. Aug 2014 A1
20140240322 Brumer et al. Aug 2014 A1
20140245318 Adams et al. Aug 2014 A1
20140279941 Atkisson Sep 2014 A1
20140281131 Joshi et al. Sep 2014 A1
20140304698 Chigurapati et al. Oct 2014 A1
20140310473 Bilas et al. Oct 2014 A1
20140310708 Lim et al. Oct 2014 A1
20140310810 Brueckner et al. Oct 2014 A1
20140325238 Ghose Oct 2014 A1
20140325239 Ghose Oct 2014 A1
20140325267 Liu et al. Oct 2014 A1
20140331220 Barrat et al. Nov 2014 A1
20140331228 Barrat et al. Nov 2014 A1
20140337461 Lipstone et al. Nov 2014 A1
20140337472 Newton et al. Nov 2014 A1
20140344315 Larimore et al. Nov 2014 A1
20140344391 Varney et al. Nov 2014 A1
20140344399 Lipstone et al. Nov 2014 A1
20140344400 Varney et al. Nov 2014 A1
20140344401 Varney et al. Nov 2014 A1
20140344413 Lipstone et al. Nov 2014 A1
20140344425 Varney et al. Nov 2014 A1
20140344452 Lipstone et al. Nov 2014 A1
20140344453 Varney et al. Nov 2014 A1
20140351516 Larimore et al. Nov 2014 A1
20140372717 Ciu et al. Dec 2014 A1
20140380039 Larson et al. Dec 2014 A1
20140380405 Forsberg et al. Dec 2014 A1
20140380425 Lockett et al. Dec 2014 A1
20150012570 Le et al. Jan 2015 A1
20150012776 Banikazemi et al. Jan 2015 A1
20150019827 Waldspurger et al. Jan 2015 A1
20150026451 Doerr et al. Jan 2015 A1
20150052517 Raghu et al. Feb 2015 A1
20150052521 Raghu Feb 2015 A1
20150052523 Raghu Feb 2015 A1
20150052524 Raghu Feb 2015 A1
20150052525 Raghu Feb 2015 A1
20150058298 Earl et al. Feb 2015 A1
20150058933 Larson et al. Feb 2015 A1
20150066844 Yin et al. Mar 2015 A1
20150074058 Zhao et al. Mar 2015 A1
20150074670 Gerganov Mar 2015 A1
20150074743 Ilieva et al. Mar 2015 A1
20150095648 Nix Apr 2015 A1
20150113288 Mittal Apr 2015 A1
20150113289 Mittal Apr 2015 A1
20150121087 Mittal Apr 2015 A1
20150121090 Mittal Apr 2015 A1
20150128262 Glew et al. May 2015 A1
20150149999 Ramanathan et al. May 2015 A1
20150154423 Mittal Jun 2015 A1
20150154424 Mittal Jun 2015 A1
20150160964 Nelson Jun 2015 A1
20150163088 Anschutz Jun 2015 A1
20150163097 Lipstone et al. Jun 2015 A1
20150178097 Russinovich Jun 2015 A1
20150178114 Chambers et al. Jun 2015 A1
20150180724 Varney et al. Jun 2015 A1
20150180725 Varney et al. Jun 2015 A1
20150180971 Varney et al. Jun 2015 A1
20150207695 Varney et al. Jul 2015 A1
20150222604 Ylonen Aug 2015 A1
20150222706 Pandya Aug 2015 A1
20150237022 Larson et al. Aug 2015 A1
20150242626 Wang et al. Aug 2015 A1
20150242648 Lemmey et al. Aug 2015 A1
20150242972 Lemmey et al. Aug 2015 A1
20150244680 Larson et al. Aug 2015 A1
20150269617 Mikurak Sep 2015 A1
20150278034 Barnes et al. Oct 2015 A1
20150278126 Maniatis et al. Oct 2015 A1
20150278491 Horning et al. Oct 2015 A1
20150286821 Ghose Oct 2015 A1
20150293791 Adams et al. Oct 2015 A1
20150309883 North Oct 2015 A1
20150310210 Sia et al. Oct 2015 A1
20150317491 Yang et al. Nov 2015 A1
20150331708 Bala et al. Nov 2015 A1
20150331720 Huetter et al. Nov 2015 A1
20150334130 Brueckner et al. Nov 2015 A1
20150341319 Larson et al. Nov 2015 A1
20150356207 Reitman et al. Dec 2015 A1
20150363324 Joshi et al. Dec 2015 A1
20150378766 Beveridge et al. Dec 2015 A1
20150378771 Tarasuk-Levin et al. Dec 2015 A1
20150378785 Tarasuk-Levin et al. Dec 2015 A1
20150378831 Tarasuk-Levin et al. Dec 2015 A1
20150378847 Tarasuk-Levin et al. Dec 2015 A1
20150378940 Bradbury et al. Dec 2015 A1
20150378942 Bradbury et al. Dec 2015 A1
20150381589 Tarasuk-Levin et al. Dec 2015 A1
20160004805 Drees et al. Jan 2016 A1
20160004869 Ismael et al. Jan 2016 A1
20160006756 Ismael et al. Jan 2016 A1
20160012009 Banikazemi et al. Jan 2016 A1
20160019107 North Jan 2016 A1
20160021077 Larson et al. Jan 2016 A1
20160036862 Bagepalli et al. Feb 2016 A1
20160062789 Hiltgen et al. Mar 2016 A1
20160077761 Stabrawa et al. Mar 2016 A1
20160077857 Dong et al. Mar 2016 A1
20160077966 Stabrawa et al. Mar 2016 A1
20160077975 Stabrawa et al. Mar 2016 A1
20160078342 Tang Mar 2016 A1
20160078585 Sheldon et al. Mar 2016 A1
20160092251 Wagner Mar 2016 A1
20160110215 Bonilla et al. Apr 2016 A1
20160110657 Gibiansky et al. Apr 2016 A1
20160117501 Ghose Apr 2016 A1
20160119148 Ghose Apr 2016 A1
20160132333 Dixon et al. May 2016 A1
20160132334 Dixon et al. May 2016 A1
20160132335 Dixon et al. May 2016 A1
20160132336 Dixon et al. May 2016 A1
20160132337 Dixon et al. May 2016 A1
20160134584 Lang et al. May 2016 A1
20160140052 Waldspurger et al. May 2016 A1
20160147631 Magdon-Ismail et al. May 2016 A1
20160147649 Magdon-Ismail et al. May 2016 A1
20160147665 Magdon-Ismail et al. May 2016 A1
20160148403 Brumer et al. May 2016 A1
20160149950 Ashley et al. May 2016 A1
20160150003 Magdon-Ismail et al. May 2016 A1
20160154648 Dixon et al. Jun 2016 A1
20160170849 Cheng et al. Jun 2016 A1
20160179721 Neiger et al. Jun 2016 A1
20160188181 Smith Jun 2016 A1
20160191298 Markley et al. Jun 2016 A1
20160191332 Markley et al. Jun 2016 A1
20160196158 Nipane et al. Jul 2016 A1
20160196426 Hunt et al. Jul 2016 A1
20160210177 Dixon et al. Jul 2016 A1
20160217253 Newman et al. Jul 2016 A1
20160219115 Dong et al. Jul 2016 A1
Foreign Referenced Citations (2)
Number Date Country
2658166 Oct 2013 EP
2010154098 Jul 2010 JP
Non-Patent Literature Citations (76)
Entry
S. Davidoff. Cleartext passwords in linux memory. www.philosecurity.org, 2008.
S. T. King, G. W. Dunlap, and P. M. Chen. Debugging operating systems with time-traveling virtual machines. pp. 1-15, 2005.
S. W. Smith and J. D. Tygar, “Security and Privacy for Partial Order Time”, ISCA Seventh International Conference on Parallel and Distributed Computing Systems, (1994), pp. 70-79.
S. Weingart. Physical security for the μABYSS system. In Proceedings of the IEEE Computer Society Conference on Security and Privacy, pp. 38-51, 1987.
S. White, S. Weingart, W Arnold, and E. Palmer. Introduction to the Citadel architecture: security in physically exposed environments. Technical Report RC16672, IBM Thomas J. Watson Research Center, Mar. 1991.
Sean W. Smith , Elaine R. Palmer , Steve Weingart, “Building a high-performance, programmable secure coprocessor”, Computer Networks (1999).
Sean W. Smith, Vernon Austel, “Trusting Trusted Hardware: Towards a Formal Model for Programmable Secure Coprocessors” USENIX (1998).
Sean W. Smith et al., “Using a High Performance, Programmable Secure Coprocessor,” 2nd International Conference on Financial Cryptography, Feb. 1998.
SETI@home. http://setiathome.ssl.berkeley.edu/, 2014.
slock. tools.suckless.org/slock, 2006-2013.
T. Garfinkel and M. Rosenblum. When virtual is harder than real: security challenges in virtual machine based computing environments. In Proceedings of the 10th conference on Hot Topics in Operating Systems, pp. 20-20, 2005.
T. Garfinkel, B. Pfaff, J. Chow, and M. Rosenblum. Data lifetime is a systems problem. In Proc. of ACM SIGOPS European workshop. ACM, 2004.
Tal Garfinkel , Mendel Rosenblum, “A Virtual Machine Introspection Based Architecture for Intrusion Detection” (2003), Proc. Network and Distributed Systems Security Symposium.
Tal Garfinkel and Ben Pfaff and Jim Chow and Mendel Rosenblum and Dan Boneh, “Terra: a virtual machine-based platform for trusted computing”, ACM Press 2003, pp. 193-206.
TCPA. http://www.trustedcomputing.org/, 2014.
TPM Part 1 Design Principles Version 1.2 Revision 103, published Jul. 9, 2007.
TPM part 2 specification 1.2 Revision 103, published on Jul. 9, 2007.
TPM Part 3 Commands Version 1.2 Revision 116, published Feb. 2011.
U. Maheshwari, R. Vingralek, and W. Shapiro. How to build a trusted database system on untrusted storage. In Proceedings of the 4th USENIX Symposium on Operating Systems Design and Implementation, pp. 135-150, Oct. 2000.
Vivek Haldar, Deepak Chandra and Michael Franz, “Semantic Remote Attestation—A Virtual Machine directed approach to Trusted Computing”, USENIX Virtual Machine Research and Technology Symposium, May 2004.
Vmware ace virtualization suite. www.vmware.com/products/ace, 2013.
VMware Inc. Vmware infrastructure. www.vmware.com/landing.sub.-pages/ discover.html, 2013.
VMware Inc. www.vmware.com, 2013.
VMware.Cloud computing.www.vmware.com/solutions/cloud-computing, Sep. 27, 2013.
William A. Arbaugh , David J. Farbert , Jonathan M. Smith, “A Secure and Reliable Bootstrap Architecture” (1997). Proceedings of the 1997 IEEE Symposium on Security and Privacy.
Xen. Xen cloud platform—advanced virtualization infrastructure for the clouds. www.xen.org/products/cloudxen.html, 2013.
Xfree86. www.xfree86.org/4.2.0/xwininfo.1.html, Aug. 12, 2016.
Xfree86. www.xfree86.org/current/xprop.1.html, Apr. 24, 2011.
A. Dinaburg, P. Royal, M. Sharif, and W. Lee. Ether: malware analysis via hardware virtualization extensions. In 15th ACM conference on Computer and communications security, pp. 51-62, 2008.
A. Joshi, S. T. King, G. W. Dunlap, and P. M. Chen. Detecting past and present intrusions through vulnerability-specific predicates. In Proceedings of the twentieth ACM symposium on Operating systems principles, pp. 91-104, 2005.
A. Kivity, Y. Kamay, D. Laor, U. Lublin, and A. Liguori. kvm: the linux virtual machine monitor. In Proc. of the Linux Symposium, pp. 225-230, Jun. 2007.
A. M. Nguyen, N. Schear, H. Jung, A. Godiyal, S. T. King, and H. D. Nguyen. Mavmm: Lightweight and purpose built vmm for malware analysis. In Annual Computer Security Applications Conference, pp. 441-450, 2009.
A. Seshadri, M. Luk, N. Qu, and A. Perrig. Secvisor: a tiny hypervisor to provide lifetime kernel code integrity for commodity oses. In Proceedings of Twenty-First ACM SIGOPS symposium on Operating Systems Principles, pp. 335-350, 2007.
Arora et al., Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors, IEEE, 2006.
B. D. Payne, M. Carbone, M. Sharif, and W. Lee. Lares: An architecture for secure active monitoring using virtualization. In IEEE Symposium on Security and Privacy, pp. 233-247, 2008.
B. Gassend, D. Clarke, M. Van Dijk, and S. Devadas. Controlled physical random functions. In Proceedings of the 18th Annual Computer Security Applications Conference, Dec. 2002.
B. Yee. Using secure coprocessors. PhD thesis, Carnegie Mellon University, May 1994.
Bryan Parno Jonathan M. McCune Adrian Perrig, “Bootstrapping Trust in Commodity Computers”, IEEE Symposium on Security and Privacy, May 2010.
Chen and Morris, “Certifying Program Execution with Secure Processors”, Proceedings of the 9th conference on Hot Topics in Operating Systems, USENIX, vol. 9, pp. 133-138, 2003.
D.A. S. d. Oliveira and S. F. Wu. Protecting kernel code and data with a virtualization-aware collaborative operating system. In Annual Computer Security Applications Conference, pp. 451-460, 2009.
D. Lezcano. Linux containers. lxc.sourceforge.net/lxc.html, Feb. 27, 2010.
D. Lie, C. A. Thekkath, M. Mitchell, P. Lincoln, D. Boneh, J. C. Mitchell, and M. Horowitz. Architectural support for copy and tamper resistant software. In Proceedings of Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 168-177, 2000.
D. Lie, “Architectural Support For Copy and Tamper Resistant Software,” Dissertation, Department of Electrical Engineering and the Committee for Graduate Studies of Stanford University, Oct. 2003.
D. Nurmi, R. Wolski, C. Grzegorczyk, G. Obertelli, S. Soman, L. Youseff, and D. Zagorodnov. The eucalyptus open-source cloud-computing system. In Proceedings of the 9th IEEE/ACM International Symposium on Cluster Computing and the Grid, pp. 124-131, 2009.
D. P. Bovet and M. C. Ph. Understanding the Linux Kernel, Third Edition. O'Reilly Media, 3 edition, Nov. 2005.
Dan Williams and Emin Gun Sirer, “Optimal Parameter Selection for Efficient Memory Integrity Verification Using Merkle Hash trees”, Proceedings. Third IEEE International Symposium on Network Computing and Applications, 2004. (NCA 2004).
Edward Suh, Dwaine Clarke, Blaise Gassend, Marten van Dijk, Srini Devadas, “AEGIS: Architecture for Tamper-Evident and Tamper-Resistant Processing”, Submission to the Proceedings of the 17th International Conference on Supercomputing, Computation Structures Group Memo 461 2003).
Edward Suh, Dwaine Clarke, Blaise Gassend, Marten van Dijk, Srini Devadas, “AEGIS: Architecture for Tamper-Evident and Tamper-Resistant Processing”, Submission to the Proceedings of the 17th International Conference on Supercomputing, Computation Structures Group Memo 474 2004).
Elaine Shi, Adrian Perrig , Leendert Van Doom, “BIND: A Fine-grained Attestation Service for Secure Distributed Systems” (2005), IEEE Symposium on Security and Privacy.
G. Edward Suh and Dwaine Clarke and Blaise Gassend and Marten Van Dijk and Srinivas Devadas, “Efficient Memory Integrity Verification and Encryption for Secure Processors”, Proceedings of the 36th Annual International Symposium on Microarchitecture (2003), pp. 339-350.
G. Edward Suh and Dwaine Clarke and Blaise Gassend and Marten van Dijk and Srinivas Devadas, “Hardware Mechanisms for Memory Integrity Checking” (2002).
G. W. Dunlap, S. T. King, S. Cinar, M. A. Basrai, and P. M. Chen. Revirt: Enabling intrusion analysis through virtual-machine logging and replay. In in Proceedings of the 2002 Symposium on Operating Systems Design and Implementation (OSDI), pp. 211-224, 2002.
Gang Xu and Cristian Borcea and Liviu Iftode, “Satem: Trusted service code execution across transactions”, Proc. IEEE Int. Symp. Reliable Distributed Systems (2006).
Google Corp. Inter-process communication. dev.chromium.org/developers/ design-documents/inter-process-communication, Sep. 27, 2013.
Healey et al., Dynamic Tracking of Information Flow Signatures for Security Checking, University of Illinois—Center for Reliable and High-Performance Computing, 2007.
J. Chow, B. Pfaff, T. Garfinkel, and M. Rosenblum. Shredding your garbage: reducing data lifetime through secure deallocation. In Proceedings of the USENIX Security Symposium, pp. 22-22, 2005.
J. Chow, B. Pfaff, T. Garfinkel, K. Christopher, and M. Rosenblum. Understanding data lifetime via whole system simulation. In Proceedings of USENIX Security Symposium, pp. 22-22, 2004.
J. Corbet, A. Rubini, and G. Kroah-Hartman. Linux Device Drivers, 3rd Edition. O'Reilly Media, Inc., 2005.
Jonathan M. McCune and Bryan Pamo and Adrian Perrig and Michael K. Reiter and Hiroshi Isozaki, “Flicker: An Execution Infrastructure for TCB Minimization”, (2008).
Joseph Zambreno and Alok Choudhary, “SAFE-OPS: An approach to embedded software security”, ACM Transactions on Embedded Computing Systems (TECS), vol. 4, Issue 1 (2005).
Joshua N. Edmison, “Hardware Architectures for Software Security”, Ph.D Thesis, Virginia Polytechnic Institute and State University (2006).
K. Kourai and S. Chiba. Hyperspector: Virtual distributed monitoring environments for secure intrusion detection. In ACM/USENIX International Conference on Virtual Execution Environments, pp. 197-207, 2005.
M. Balduzzi, J. Zaddach, D. Balzarotti, E. Kirda, and S. Loureiro. A security analysis of amazon's elastic compute cloud service. In ACM Symposium on Applied Computing, pp. 1427-1434, 2012.
M. I. Gofman, R. Luo, P. Yang, and K. Gopalan. SPARC: A security and privacy aware virtual machine checkpointing mechanism. In Proceedings of the 10th annual ACM Workshop on Privacy in the Electronic Society (WPES), in conjunction with the ACM Conference on Computer and Communications Security (CCS), pp. 115-124, 2011.
Marten Van Dijk and Luis F. G. Sarmenta and Charles W. O'donnell and Srinivas Devadas, “Proof of Freshness: Flow to efficiently use on online single secure clock to secure shared untrusted memory”, (2006).
Marten Van Dijk and Luis F. G. Sarmenta and Jonathan Rhodes and Srinivas Devadas, “Securing Shared Untrusted Storage by using TPM 1.2 Without Requiring a Trusted OS”, (2007).
Michael E. Locasto and Stelios Sidiroglou and Angelos D. Keromytis, “Speculative Virtual Verification: PolicyConstrained Speculative Execution”, Proceedings of the 14th New Security Paradigms Workshop (NSPW 2005), pp. 1-19.
Michael E. Locasto, “Micro-speculation, Micro-sandboxing, and Self-Correcting Assertions: Support for Self-Healing Software and Application Communities”, PhD Thesis Proposal, Department of Computer Science, Columbia University, Dec. 5, 2005.
Microsoft Corp. Hyper-v server 2012 r2.www.microsoft.com/hyper-v-server/ en/us/overview.aspx, 2013.
N. Santos, K. P. Gummadi, and R. Rodrigues. Towards trusted cloud computing. In HOTCLOUD, 2009.
Nick L. Petroni and Jr. Timothy and Fraser Aaron and Walters William and A. Arbaugh, “An architecture for specification-based detection of semantic integrity violations in kernel dynamic data”, Proceedings of the USENIX Security Symposium (2006), pp. 289-304.
Nick L. Petroni and Jr. Timothy and Fraser Jesus and Molina William and A. Arbaugh, “Copilot—a coprocessor-based kernel runtime integrity monitor”, Proceedings of the 13th USENIX Security Symposium, 2004, pp. 179-194.
Oh et al., Control-Flow Checking by Software Signatures, IEEE, 2002.
OpenVZ. Container-based Virtualization for Linux, www.openvz.com, 2013.
Oracle Corp. Virtualbox. www.VirtualBox.org, Sep. 27, 2013.
R. Riley, X. Jiang, and D. Xu. Guest-transparent prevention of kernel rootkits with vmm-based memory shadowing. In the 11th international symposium on Recent Advances in Intrusion Detection, pp. 1-20, 2008.
Related Publications (1)
Number Date Country
20160117501 A1 Apr 2016 US
Provisional Applications (1)
Number Date Country
61364795 Jul 2010 US
Continuations (2)
Number Date Country
Parent 14330441 Jul 2014 US
Child 14981011 US
Parent 13183857 Jul 2011 US
Child 14330441 US