Patent Application
20250119098
The present invention relates in general to crystal oscillators, and more particularly to system and method of compensating for leakage current of a pad used for coupling an external crystal resonator of a crystal oscillator.
A crystal oscillator circuit includes a crystal resonator having terminals connected between the input and output of a transconductance (GM) amplifier. The GM amplifier includes a relatively large feedback resistor, such as several Mega-Ohms (MΩ), depending on the parameters of the crystal resonator. In many configurations the GM amplifier is implemented on an integrated circuit (IC) in which the crystal resonator is connected via a pair of pads of the IC. Leakage current in one of the pads flows through the feedback resistor causing a voltage drop across the feedback resistor. The leakage current manifests as a direct-current (DC) voltage offset between the crystal resonator terminals. The leakage current is often greater in lower semiconductor manufacturing technology processes, such as, for example the 5 nanometer (nm) process. For lower cost ICs and system configurations, pin-count becomes an issue such that the pads coupling the crystal resonator may be shared with other functional circuitry resulting in additional leakage current.
As the leakage current through the feedback resistor becomes more significant, the resulting offset voltage may shift the DC operating point of the GM amplifier, which in turn may prevent the GM amplifier from being able to provide the required gain. As a result, the crystal oscillator may produce no oscillations, or may produce oscillations that are distorted by the common mode DC voltage difference between the crystal terminals. The distorted oscillations cause a degraded duty cycle of an output clock generated by the crystal oscillator.
Embodiments of the present invention are illustrated by way of example and are not limited by the accompanying figures. Similar references in the figures may indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
A compensation system for a crystal oscillator circuit is shown and described. The crystal oscillator circuit includes an amplifier with a feedback resistance coupled between first and second pads which are coupled to first and second terminals, respectively, of a crystal resonator. The compensation system may include a DC level comparator, current compensation circuitry, and a compensation controller. The DC level comparator is configured to compare a DC level of the first pad with a DC level of the second pad and to provide a compensation signal indicative thereof. The current compensation circuitry is configured to apply a compensation current to the first pad. The compensation controller that is configured to control a magnitude and direction of the compensation current based on the compensation signal.
A method of compensating for leakage current of a crystal oscillator circuit is shown and described. The method may include comparing a DC level of an input terminal with a DC level of an output terminal and providing a compensation signal indicative thereof, selecting a direction of compensation based on a state of the compensation signal, when the compensation signal is in a first state, providing a source compensation current to the input terminal and adjusting a level of the source compensation current until the compensation signal transitions to a second state, and when the compensation signal is in the second state, drawing a sink compensation current from the input terminal and adjusting a level of the sink compensation current until the compensation signal transitions to the first state.
The GM amplifier 106 is coupled between a positive analog supply voltage AVDD provided on an internal supply node 116 and a negative analog supply voltage AVSS provided on another internal supply node 118, in which AVSS is otherwise referred to herein as analog ground. In one embodiment, the GM amplifier 106 includes a current source 120 providing a source current I_GM, a feedback resistor 122 with a resistance RF, and an N-type or N-channel MOS (NMOS) transistor N1. The current source 120 has an input coupled to AVDD and an output that provides the source current I_GM to XTAL (node 114). The feedback resistor 122 is coupled between XTAL (node 114) and EXTAL (node 112). N1 has a drain terminal coupled to XTAL, a gate terminal coupled to EXTAL, and a source terminal coupled to AVSS. N1 may have an internal bulk connection coupled to its source terminal.
The PAD_E 102 includes additional circuitry that may provide at least one path for leakage current, among other possible current paths. As shown, the PAD_E 102 includes electrostatic discharge (ESD) circuitry including diodes A1, A2, and B1, and a resistor RB. A1 has an anode coupled to node 112 (EXTAL) and a cathode coupled to AVDD. A2 has an anode coupled to node 112 and a cathode coupled to one end of resistor RB, having its other end coupled to AVDD. B1 has an anode coupled to AVSS and a cathode coupled to node 112. A first leakage current LI1 is shown flowing through A2 (and/or A1) and through feedback resistor 122, and a second leakage current LI2 is shown flowing through feedback resistor 122 and through diode B1. The resistance RF of the feedback resistor 122 may be relatively large, such as several Mega-Ohms (MΩ) (e.g., 5-10 MΩ), so that even a relatively small amount of leakage current in either direction causes a significant voltage drop across resistance RF causing a relatively large direct-current (DC) voltage offset between EXTAL and XTAL. The DC voltage offset between EXTAL and XTAL may shift the DC operating point of the GM amplifier 106, which in turn may prevent the GM amplifier 106 from being able to provide the required gain to establish or sustain successful oscillation. As a result, the crystal oscillator may produce no oscillations, or may produce oscillations that are distorted by the common mode DC voltage offset resulting in degraded duty cycle of an output clock generated by the crystal oscillator.
Upon power on or restart/reset (POR) of the crystal oscillator clock circuit 200, the GM amplifier 106 begins driving the crystal resonator XTL 101 in an attempt to generate oscillation on the EXTAL and XTAL signals. The CLKSEL signal initially selects ECLK to provide ECLK as CLK to the compensation controller 212. The CCLK generator 202 receives and senses oscillation via one or both the EXTAL and XTAL signals for generating CCLK, but monitors the characteristics of oscillation including stability and duty cycle. The CCLK generator 202 asserts CLKSEL to select ECLK until balanced oscillation on both EXTAL and XTAL is achieved such that CCLK achieves successful oscillation meaning stable oscillation with a duty cycle within a predetermined acceptable margin of error.
The leakage compensation circuit 110 includes a DC level comparator 210 that generates a comparator output signal COMP_OUT based on the voltage offset between EXTAL and XTAL. The leakage compensation circuit 110 includes the compensation controller 212 that generates a compensation current control (CCCTL) signal based on the COMP_OUT signal, in which the CCCTL signal is provided to an input of the current compensation circuit 216. The CCCTL signal may have any suitable format but generally indicates the direction and magnitude of compensation current to be applied to the node 112 to compensate for leakage current. The current compensation circuit 216 uses the CCCTL signal to apply the indicated amount of compensation current in the indicated direction as further described herein. When the leakage current is sufficiently compensated, the DC voltage offset between EXTAL and XTAL is sufficiently reduced so that CCLK achieves successful oscillation (meaning that CCLK achieves stable oscillation with a duty cycle within a predetermined acceptable margin of error), so that the CCLK generator 202 switches CLKSEL to select CCLK. In one embodiment, the leakage compensation circuit 110 operates continuously or periodically over time to automatically compensate for leakage current over time and during changes in operation or operating conditions such as, for example, changes in temperature.
Each of the current sinks 506 has an output coupled to AVSS and an input coupled to a corresponding one of the sink switches 508. Each of the sink switches 508 is configured as a SPST switch controlled by a corresponding one of a set of digital control signals NC<N:0>, which is NC<2:0> for N=2. Each of the sink switches 508 has a first switched terminal coupled to an input of a corresponding one of the current sinks 506 and a second switched terminal coupled to node 112 (EXTAL). For N=2, the sink switches 508 include a first switch SN0 controlled by NC<0>, a second switch SN1 controlled by NC<1>, and a third switch SN2 controlled by NC<2>.
It is noted that controlling the source switches 504 using the digital control signals PC<N:0> effectively activates selected ones of the current sources 502 for controlling a level or magnitude of the corresponding compensation source current. In an alternative embodiment, each of the current sources 502 may be configured to be directly activated or deactivated by a corresponding one of the PC<N:0> signals. In a similar manner, controlling the sink switches 508 using the digital control signals NC<N:0> effectively activates selected ones of the current sinks 506 for controlling a level or magnitude of the corresponding compensation sink current. In an alternative embodiment, each of the current sinks 506 may be configured to be directly activated or deactivated by a corresponding one of the NC<N:0> signals.
The series of current sources 502 are binarily weighted and based on a unit current level Io. In the illustrated configuration for N=2, a first current source provides a unit current Io to the first switch SP0, a second current source provides a current 2×Io to the second switch SP1, and a third current source provides a current 4×Io to the third switch SP2, in which “x” denotes multiplication. When any one of the PC<N:0> control signals is at a first logic state, such as logic 0, then the corresponding one of the source switches 504 is opened, and when at a second logic state, such as logic 1, then the corresponding one of the source switches 504 is closed. When closed, then the current from the corresponding current source is provided to node 112 (EXTAL), and when opened, the current is not provided. In this manner, PC<2:0> control signals (for N=2) can be controlled to deliver a selected source current of 0, Io, 2×Io, . . . , 7×Io in increments of Io to EXTAL.
The series of current sinks 506 are binarily weighted in a similar manner also based on the unit current level Io, in which a first current sink sinks a unit current Io through the first switch SN0, a second current sink sinks a current 2×Io through the second switch SN1, and a third current sink sinks a current 4×Io through the third switch SN2. The lower switches SN0, SN1, and SN2 are controlled by the NC<0>, NC<1>, and NC<2> control signals, respectively, in a similar manner. When closed, then the current drawn from the corresponding current sink is pulled from node 112 (EXTAL), and when opened, the current is not pulled. In this manner, NC<2:0> control signals (for N=2) can be controlled to sink a selected current of 0, Io, 2×Io, . . . , 7×Io in increments of Io from EXTAL.
It is noted that the current compensation circuit 216 illustrated in
When the current compensation circuit 216 is configured as shown in
With reference to
The value of Io should be selected for a given configuration as the maximum amount of current that may flow through the feedback resistor 122 in either direction that can be tolerated while such that oscillation of XTAL/EXTAL is sustained and CCLK achieves successful oscillation. The value of N, which defines the number of current sources 502 and current sinks 506 and corresponding source and sink switches 504 and 508, is defined such that the maximum source/sink current (2N+1−1)×Io is sufficiently greater than an expected (or theoretical) maximum amount of leakage current in either direction for a given implementation. In this manner, the unit current level Io and the value of N are selected to provide a sufficient level of compensation current in either direction to offset leakage current to enable successful oscillation of XTAL/EXTAL and so that CCLK achieves successful oscillation (i.e., achieves stable oscillation with a duty cycle within a predetermined acceptable margin of error).
The counter 602 is a 4-bit bidirectional counter controlled by COMP_OUT and ICLK producing 3 preliminary count bits S′0, S′1, S′2, and DIR, in which S′0 is the least significant bit (LSB) and DIR is the most significant bit (MSB). DIR is used as a compensation current direction bit for selecting between source current or sink current as further described herein. The count bits S′0, S′1, and S′2 (S′<2:0>) are used to develop magnitude bits S<2:0> for controlling either the source switches 504 when DIR=0 or the sink switches 506 when DIR=1 for determining the magnitude of the compensation current. When COMP_OUT is 0 and while ICKL is active (CEN=1), the counter 602 increments S′<2:0> with each cycle of ICLK and when COMP_OUT is 1, the counter 602 decrements S′<2:0> with each cycle of ICLK. In addition, a set of D type flip-flops (DFFs) 614 generate next state count bits S″<2:0>. A set of MUXes 616 select between the count bits S′<2:0> and the next state count bits S″<2:0> based on the state of CEN to provide the magnitude bits S<2:0>, in which S<2:0>=S″<2:0> while CEN=1 (while ICLK is active) and S<2:0>=S′<2:0> when CEN=0 (when ICLK becomes inactive).
The output select circuit 604 includes a first set of MUXes 618 that selects the magnitude bits S<2:0> as the the digital control signals PC<2:0> when DIR=0 or that sets each of the digital control signals PC<2:0> to zero when DIR=1. Similarly, the output select circuit 604 includes a second set of MUXes 620 that selects the magnitude bits S<2:0> as the digital control signals NC<2:0> when DIR=1 or that sets each of the digital control signals NC<2:0> to zero when DIR=0.
The transition detector 606 detects a transition of COMP_OUT from 0 to 1 or from 1 to 0 while ICLK is active. The transition detector 606 includes a 3-input NOR gate 622 having respective inputs receiving signals 10, 01, and OVF, and has an output providing the CEN clock enable signal. A reset signal RST clears both 10 and 01 to 0 and OVF remains at 0 unless an overflow condition is detected by the overflow circuit 612 as further described herein. When 10, 01 and OVF are each logic 0, CEN=1 so that ICLK is active (as a copy of CLK). When COMP_OUT transitions from 0 to 1 while ICLK is active, then signal 01 goes high to logic 1 so that the NOR gate 622 pulls CEN low to logic 0 to deactivate ICLK. Similarly, when COMP_OUT transitions from 1 to 0 while ICLK is active, then 10 goes high to logic 1 so that the NOR gate 622 pulls CEN low to logic 0 to deactivate ICLK. ICLK remains inactive until RST is next pulsed high to clear 10 and 01.
The delay circuit 610 divides CLK by an integer value M to provide a divided clock signal CLK/M, in which M is a programmable value. The delay circuit 610 normally asserts the reset signal RST low. Each time CLK/M transitions from 1 to 0 after one full cycle of CLK/M, the delay circuit 610 pulses RST high for one CLK cycle to reset the transition detector 606 which then re-activates ICLK for the next iteration for sampling COMP_OUT.
In operation of the compensation controller 212, after the CLK/M delay from the previous cycle, the delay circuit 610 pulses RST high to reset the transition detector 606 so that CEN is asserted to logic 1. When CEN=1, ICLK is activated and the counter 602 increments or decrements S′<2:0> based on the level of COMP_OUT, and the magnitude bits S<2:0> are updated one ICLK later by the MUXes 616 using the next state count bits S″<2:0>. The digital control signals PC<2:0> are updated accordingly to adjust the magnitude of the compensation source current while DIR=0 or to adjust the magnitude of the compensation sink current while DIR=1. When COMP_OUT transitions, CEN is pulled low to 0 to deactivate ICLK to lock the compensation current until the next reset determined by CLK/M. When CEN transitions from 1 to 0, the magnitude bits S<2:0> are locked back to the previous step (or count) of S′<2:0> by the MUXes 616.
The overflow circuit 612 monitors the count bits S′0, S′1, and S′2, the DIR bit, and the COMP_OUT signal for determining an overflow condition. OVF is held low at logic 0 when any one of these 5 signals are logically different, which is the normally expected condition. However, when all 5 of these signals are at the same logic value (e.g., all 0's or all 1's), then the overflow condition is detected (or about to occur) and OVF is asserted high to pull CEN low to deactivate ICLK. An overflow condition is an unexpected error condition that may be handled by software or additional circuitry that is not shown or described.
When COMP_OUT=1 as determined at block 710, then the DC level comparator 210 has toggled from 0 to 1 from block 706 to block 710 and operation instead advances to block 712 in which the compensation current is locked. When the current compensation circuit 216 is configured as shown in
Referring back to block 706, if COMP_OUT=1 as determined at block 706, then operation advances instead to block 716 in which the compensation controller 212 decreases the magnitude of the compensation current. When the current compensation circuit 216 is configured as shown in
When COMP_OUT=0 as determined at block 718, then the DC level comparator 210 has toggled from 1 to 0 from block 706 to block 718 and operation instead advances to block 712 in which the compensation current is locked as previously described. Operation then advances to block 714 in which the compensation controller 210 waits the programmable time period, and then back to block 704 to repeat the process for the next iteration. Operation continues to loop until the next POR or when power is turned off.
After POR, in parallel with current compensation performed by blocks 702 to 718, operation also advances to block 720 in which the CCLK generator 202 initially asserts CLKSEL to select the external clock signal ECLK. Operation advances to next block 722 in which the CCLK generator 202 determines whether CCLK is successful, meaning CCLK has achieved stable oscillation with a duty cycle within a predetermined acceptable margin of error as previously described. If CCLK has not yet achieved successful oscillation, operation loops back to block 720, and operation loops between blocks 720 and 722 until CCLK is determined to be successful. When CCLK is successful as determined at block 722, operation loops instead to block 724 in which the CCLK generator 202 asserts CLKSEL to select the internal crystal clock signal CCLK. While CCLK maintains successful oscillation, operation continuously loops between blocks 722 and 724. If CCLK fails for any reason during operation or upon subsequent POR, then operation loops back to block 720 to again select ECLK until CCLK is successful.
Although the present invention has been described in connection with several embodiments, the invention is not intended to be limited to the specific forms set forth herein. On the contrary, it is intended to cover such alternatives, modifications, and equivalents as can be reasonably included within the scope of the invention as defined by the appended claims. For example, variations of positive circuitry or negative circuitry may be used in various embodiments in which the present invention is not limited to specific circuitry polarities, device types or voltage or error levels or the like. For example, circuitry states, such as circuitry low and circuitry high may be reversed depending upon whether the pin or signal is implemented in positive or negative circuitry or the like. In some cases, the circuitry state may be programmable in which the circuitry state may be reversed for a given circuitry function.
The terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202341066496 | Oct 2023 | IN | national |
