Patent Application
20140091860
The present disclosure relates generally to integrated circuits, and more specifically, to a system and method of implementing input/output (I/O) drivers using relatively low voltage devices.
Integrated circuits of today typically include numerous devices (e.g., millions or even billions of devices) in order to perform their intended operations. One of the most common devices used in integrated circuits is the complementary metal oxide semiconductor field effect transistor (CMOSFET or CMOS, for short). Some CMOS devices are employed to process signals residing internally within integrated circuits. Other CMOS devices are implemented at the periphery of integrated circuits, such as in input/output (I/O) circuits, to receive input data or signaling for the integrated circuits or produce output data or signaling for devices external to the integrated circuits.
Often, I/O drivers are configured to receive or output data or signaling with defined voltage levels. For example, some I/O drivers are required to generate digital data or signaling with defined voltage levels of zero (0) and +3.6V. However, the non-I/O driver devices internal to integrated circuits may not have such voltage level requirements. In many cases, it is desirable to operate the non-I/O driver devices at much lower voltages in order to process the data or signaling at a much faster rate. For example, it may be desirable to operate CMOS devices at defined voltage levels of zero (0) and +1.8V.
However, employing two or more different types of CMOS, such as lower voltage CMOS devices for non-I/O applications and higher voltage CMOS devices for I/O applications, is not generally desirable since it requires more masks and more processing steps to manufacture the integrated circuits. Generally, the higher number of masks and processing steps required to manufacture integrated circuits, the higher the associated costs to manufacture the integrated circuits. Further, simply employing the lower voltage devices for higher voltage I/O applications is also not desirable since such lower voltage devices may be overstressed and their reliability would be decreased, or altogether damaged and performance and functionality would be compromised.
An aspect of the disclosure relates to an apparatus comprising a pull-up circuit including first and second switching devices coupled in series between a first voltage rail and an output, wherein the first and second switching devices are configured to turn on to cause a voltage at the output to be substantially at a steady-state first rail voltage, and wherein the first and second switching devices are configured to turn off to isolate the output from the first voltage rail when the output voltage is substantially at a steady-state second rail voltage.
The apparatus further comprises a pull-down circuit comprising third and fourth switching devices coupled in series between the output and a second voltage rail, wherein the third and fourth switching devices are configured to turn on to cause the output voltage to be substantially at the steady-state second rail voltage, and wherein the third and fourth switching devices are configured to turn off to isolate the output from the second voltage rail when the output voltage is substantially at the steady-state first rail voltage.
Additionally, the apparatus comprises a compensation circuit configured to: apply a first compensation voltage to a first node between the first and second switching devices to maintain a first voltage across the second switching device at or below a first defined threshold; apply a second compensation voltage to a second node between the third and fourth switching devices to maintain a second voltage across the third switching device at or below a second defined threshold; or apply the first compensation voltage to the first node between the first and second switching devices to maintain the first voltage across the second switching device at or below the first defined threshold, and apply the second compensation voltage to the second node between the third and fourth switching devices to maintain the second voltage across the third switching device at or below the second defined threshold.
In another aspect of the disclosure, the compensation circuit is configured to apply the first compensation voltage to the first node between the first and second switching devices to maintain the first voltage across the second switching device at or below the first defined threshold when the output voltage is substantially at the steady-state second rail voltage. In still another aspect, the compensation circuit is configured to apply the second compensation voltage to the second node between the third and fourth switching devices to maintain the second voltage across the third switching device at or below the second defined threshold when the output voltage is substantially at the steady-state first rail voltage.
In another aspect of the disclosure, the compensation circuit is further configured to apply the first compensation voltage to the first node between the first and second switching devices during at least a portion of a transition of the output voltage from the second rail voltage to the first rail voltage to maintain the first voltage across the second switching device at or below the first defined threshold during the transition of the output voltage from the second rail voltage to the first rail voltage.
In another aspect of the disclosure, the compensation circuit is further configured to apply the second compensation voltage to the second node between the third and fourth switching devices during at least a portion of a transition of the output voltage from the first rail voltage to the second rail voltage to maintain the second voltage across the third switching device at or below the second defined threshold during the transition of the output voltage from the first rail voltage to the second rail voltage.
In another aspect of the disclosure, the compensation circuit is further configured to apply the first compensation voltage to the first node between the first and second switching devices during a first portion of a transition of the output voltage from the second rail voltage to the first rail voltage to maintain the first voltage across the second switching device at or below the first defined threshold during the first portion of the transition of the output voltage from the second rail voltage to the first rail voltage; and discontinue the application of the first compensation voltage to the first node between the first and second switching devices during a second portion of the transition of the output voltage from the second rail voltage to the first rail voltage.
In another aspect of the disclosure, the apparatus comprises a controller configured to control the compensation circuit in applying the first compensation voltage to the first node between the first and second switching devices. In still another aspect, the controller is configured to turn on the second switching device during the first portion of the transition of the output voltage from the second rail voltage to the first rail voltage to form a first charging path from a source of the first compensation voltage to the output. In yet another aspect, the controller is configured to turn on both the first and second switching devices during the second portion of the transition of the output voltage from the second rail voltage to the first rail voltage to form a second charging path from the first voltage rail to the output.
In another aspect of the disclosure, the controller is configured to turn off both the third and fourth switching devices during the transition of the output voltage from the second rail voltage to the first rail voltage. And, in yet another aspect, the controller is configured to control the compensation circuit to apply the second compensation voltage to the second node between the third and fourth switching devices during the transition of the output voltage from the second rail voltage to the first rail voltage.
In another aspect of the disclosure, the compensation circuit is further configured to apply the second compensation voltage to the second node between the third and fourth switching devices during a first portion of a transition of the output voltage from the first rail voltage to the second rail voltage to maintain the second voltage across the third switching device at or below the second defined threshold during the first portion of the transition of the output voltage from the first rail voltage to the second rail voltage, and discontinue the application of the second compensation voltage to the second node between the third and fourth switching devices during a second portion of the transition of the output voltage from the first rail voltage to the second rail voltage.
In another aspect of the disclosure, the apparatus comprises a controller configured to control the compensation circuit in applying the second compensation voltage to the second node between the third and fourth switching devices. In yet another aspect, the controller is configured to turn on the third switching device during the first portion of the transition of the output voltage from the first rail voltage to the second rail voltage to form a first discharging path from the output to a source of the second compensation voltage. In still another aspect, the controller is configured to turn on both the third and fourth switching devices during the second portion of the transition of the output voltage from the first rail voltage to the second rail voltage to form a second discharging path from the output to the second voltage rail.
In another aspect of the disclosure, the controller is configured to turn off both the first and second switching devices during the transition of the output voltage from the first rail voltage to the second rail voltage. In still another aspect, the controller is configured to control the compensation circuit to apply the first compensation voltage to the first node between the first and second switching devices during the transition of the output voltage from the first rail voltage to the second rail voltage.
Other aspect of the disclosure relates to apparatus, components, modules, devices, encoded computer-readable storage mediums, and other elements configured to achieve the operations in accordance with the aforementioned method. In general, other aspects, advantages and novel features of the present disclosure will become apparent from the following detailed description of the disclosure when considered in conjunction with the accompanying drawings.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.”
Various aspects of the disclosure are described below. It should be apparent that the teachings herein may be embodied in a wide variety of forms and that any specific structure, function, or both being disclosed herein are merely representative. Based on the teachings herein one skilled in the art should appreciate that an aspect disclosed herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, such an apparatus may be implemented or such a method may be practiced using other structure, functionality, or structure and functionality in addition to or other than one or more of the aspects set forth herein.
The PFET MP2 of the pull-up circuit may be biased with a substantially constant gate voltage VPBIAS, which may be set to VDD/2 (e.g., +1.8V). Configured as such, the PFET MP2 turns on and off in response to the turning on and off of PFET MP1/respectively. For instance, when control voltage VPCTL is substantially at VDD/2 (e.g., +1.8V), the PFET MP1 is turned on because VGS (e.g., 3.6V−1.8V=1.8V) is greater than the threshold voltage (e.g., 0.4V) of the device. The turning on of device PFET MP1 causes VDD to be substantially applied to the source of PFET MP2. Accordingly, PFET MP2 turns on because VGS (e.g., 3.6V−1.8V=1.8V) is greater than the threshold voltage (e.g., 0.4V) of the device. Both PFETs MP1 and MP2 being turned on causes VDD to be applied substantially to the output of the I/O driver 100 by way of resistor RP, which results in the output voltage VOUT to be at substantially VDD (e.g., ˜3.6V). The resistor RP limits the current flow through the devices MP1 and MP2 to prevent overstressing or damaging of the devices.
Similarly, when control voltage VPCTL is substantially at VDD (e.g., +3.6V), the PFET MP1 is turned off because VGS (e.g., 3.6V−3.6V=0V) is less than the threshold voltage (e.g., 0.4V) of the device. The device PFET MP1 being turned off isolates VDD from the source of PFET MP2, which causes the source of PFET MP2 to settle to a voltage VPI no greater than a threshold voltage above VPBIAS. Thus, PFET MP2 is turned off because VGS does not exceed the threshold voltage of the device. With both PFETs MP1 and MP2 turned off, the output of the I/O driver 100 is substantially isolated from VDD, allowing a pull-down circuit of the I/O driver 100 to control the state of the output, e.g., to place the output voltage VOUT at substantially the steady-state second rail voltage VSS (e.g., 0V). When the output voltage VOUT is at VSS, the PFET MP2 prevents the entire voltage difference between VDD and VSS to be applied across PFET MP1, thereby preventing overstressing or damage to device MP1.
The I/O driver 100 further comprises a pull-down circuit situated between the output of the I/O driver 100 and the second voltage rail. The pull-down circuit is configured to couple the output to the second voltage rail to cause the output voltage VOUT to be substantially at the steady-state second rail voltage VSS. The pull-down circuit is also configured to isolate the output of the I/O device 100 from the second voltage rail when the output voltage VOUT is substantially at the first rail voltage VDD. In this example, the pull-down circuit includes a pair of n-channel CMOS devices (NFETs) MN1 and MN2, and resistor RN. The NFET MN1 is responsive to a control signal VNCTL for turning on and off the NFET MN1 in order to pull-down and isolate the output voltage VOUT to and from the second rail voltage VSS, respectively.
The NFET MN2 of the pull-down circuit may be biased with a substantially constant gate voltage VNBIAS, which may be set to VDD/2 (e.g., +1.8V). Configured as such, the NFET MN2 turns on and off in response to the turning on and off of NFET MN1, respectively. For instance, when control voltage VNCTL is at VDD/2 (e.g., +1.8V), the NFET MN1 is turned on because VGS (e.g., 1.8V−0V=1.8V) is greater than the threshold voltage (e.g., 0.4V) of the device. The turning on of device NFET MP1 causes VSS to be substantially applied to the source of NFET MN2. In response, NFET MN2 turns on because VGS (e.g., 1.8V−0V=1.8V) is greater than the threshold voltage (e.g., 0.4V) of the device. Both NFETs MN1 and MN2 being turned on causes VSS to be applied substantially to the output of the I/O driver 100 by way of resistor RN, which results in the output voltage VOUT to be substantially at the second rail voltage VSS (e.g., 0V). The resistor RN limits the current flow through the devices MN1 and MN2 to prevent overstressing or damaging of the devices.
Similarly, when control voltage VNCTL is at VSS (e.g., 0V), the NFET MN1 is turned off because VGS (e.g., 0V−0V=0V) is less than the threshold voltage (e.g., 0.4V) of the device. The device NFET MN1 being turned off isolates VSS from the source of NFET MN2, which causes the source of NFET MN2 to be no more than a threshold voltage below VNBIAS. Accordingly, NFET MN2 is turned off because VGS does not exceed the threshold voltage of the device. Both NFETs MN1 and MN2 being turned off results in the output being substantially isolated from the second voltage rail, allowing the pull-up circuit of the I/O driver 100 to control the state of the output, e.g., to place the output voltage VOUT substantially at the first rail voltage VDD (e.g., +3.6V). When the output voltage VOUT is at VDD, the NFET MN2 prevents the entire voltage difference between VDD and VSS to be applied across NFET MN1, thereby preventing overstressing or damage to device MN1.
The y- or vertical axis of the timing diagram represents the various voltages of the I/O driver 100. For instance, from top to bottom, the voltages are: (1) the control voltage VPCTL for PFET MP1; (2) the gate bias voltage VPBIAS for PFET MP2; (3) the voltage VPI at the source of PFET MP2; (4) the output voltage VOUT of the I/O driver 100; (5) the gate bias voltage VNBIAS for NFET MN2; (6) the voltage VNI at the source of NFET MN2; and (7) the control voltage VNCTL for NFET MN1.
In operation, during the state or time interval where the output voltage VOUT of the I/O driver 100 is substantially at VDD as indicated in the first column of the timing diagram, the control voltage VPCTL and the gate bias voltage VPBIAS are both at substantially VDD/2 (e.g., +1.8V) in order to turn on both PFETs MP1 and MP2. The turning on of both PFETs MP1 and MP2 results in substantially coupling VDD to the output of the I/O driver 100, thereby causing the output voltage VOUT to be substantially at VDD (e.g., +3.6V). Also, the voltage VPI at the source of PFET MP1 is also substantially at VDD (e.g., +3.6V). Further, during this state or time interval, the control voltage VNCTL is substantially at VSS (e.g., 0V) to turn off NFET MN1. The gate bias voltage VNBIAS of NFET MN2 is substantially at VDD/2 (e.g., +1.8V). With NFET MN1 being turned off, the voltage VNI at the source of NFET MN2 will settle to no more than a threshold voltage below VNBIAS, for example, to +1.4V. Thus, both NFET MN1 and MN2 are turned off to isolate the output of the I/O driver 100 from VSS.
During the state or time interval where the output voltage VOUT of the I/O driver 100 is transitioning from VDD to VSS as indicated in the second column of the timing diagram, the control voltage VPCTL for PFET MP1 is raised to substantially VDD (e.g., +3.6V) to turn off PFET MP1. The gate bias voltage VPBIAS of PFET MP2 remains substantially at VDD/2 (e.g., +1.8V). Thus, the voltage VPI at the source of PFET MP2 will settle no more than a threshold voltage above VPBIAS, for example, to +2.2V. Thus, both PFET MP1 and MP2 are turned off to isolate the output of the I/O driver 100 from VDD. Also, during this state or time interval, the control voltage VNCTL is raised to VDD/2 (e.g., +1.8V) to turn on NFET MN1. The turning on of NFET MN1 causes the voltage VNI at the source of NFET MN2 to decrease to VSS (e.g., 0V). The gate bias voltage of NFET MN2 remains at VDD/2 (e.g., +1.8V). Thus, the gate-to-source voltage VGS of NFET MN2 is greater than the threshold voltage of the device MN2, thereby causing NFET MN2 to turn on. Both NFETs MN1 and MN2 being turned on causes the output voltage VOUT to decrease substantially to VSS (e.g., 0V).
Once the voltages have transitioned, they will remain substantially constant during the state or time interval where the output voltage VOUT is at substantially VSS, as indicated in the third column. That is, the voltages VPCTL and VPBIAS are substantially constant at respectively VDD and VDD/2 to keep devices MP1 and MP2 turned off to isolate the output from the first voltage rail. The source of PFET MP2 remains substantially constant at no more than a threshold voltage above VPBIAS (e.g., +2.2V). The voltages VNCTL and VNBIAS are substantially constant at VDD/2 to keep both devices MN1 and MN2 turned on to cause the output voltage VOUT to be substantially at the steady-state second rail voltage VSS. Both devices MN1 and MN2 being turned on, the source VNI of NFET MN2 settles to substantially VSS (e.g., 0V).
During the state or time interval where the output voltage VOUT of the I/O driver 100 is transitioning from VSS to VDD as indicated in the fourth column of the timing diagram, the control voltage VPCTL for PFET MP1 is lowered to VDD/2 (e.g., +1.8V) to turn on PFET MP1. The gate bias voltage VPBIAS for PFET MP2 remains at VDD/2 (e.g., +1.8V). Thus, both PFETs MP1 and MP2 turn on. Accordingly, the voltage VPI at the source of PFET MP2 as well as the output voltage VOUT will increase to substantially VDD (e.g., +3.6 V). Also, during this state or time interval, the control voltage VNCTL is lowered to VSS (e.g., 0V) to turn off NFET MN1. The gate bias voltage VNBIAS of NFET MN2 remains at VDD/2 (e.g., +1.8V). Accordingly, the voltage VNI at the source of NFET MN2 increases to at least a threshold voltage below VNBIAS, to, for example, +1.4V. Thus, the gate-to-source voltage VGS of NFET MN2 does not exceed the threshold voltage of NFET MN2, thereby causing NFET MN2 to turn off. Both NFET MN1 and MN2 being turned off isolates the output voltage VOUT from VSS (e.g., 0V). Once the voltages have transitioned, they will remain substantially constant during the state or time interval where the output voltage VOUT is at substantially VDD, as indicated in the last column.
There are a couple of issues with the I/O driver 100. For instance, if the devices MP1, MP2, MN1, and MN2 used in I/O driver 100 are manufactured in accordance with 45 nm, 40 nm or 28 nm technology (e.g., to use the same technology for all other non-I/O devices in an integrated circuit), the maximum voltage across any terminals (VGS, VGA, and VDS) of these devices is about +2.0V. If the devices are exposed to voltages above the reliable limit of +2.0V and for an extended period of time (e.g., a few picoseconds), recoverable or unrecoverable damage to these devices may result. Such damage may be due to negative bias temperature instability (NBTI) or hot carrier injection (HCl). As a consequence, the performance and functionality of the devices may degrade or completely fail.
With reference again to
Further, during the state or time interval where the output voltage VOUT is transitioning from VDD to VSS as indicated in the second column of the timing diagram, the voltage VNI at the source of NFET MN2 decreases from +1.4V to 0V at a rate much faster than the output voltage VOUT decreases from +3.6V to 0V, due to generally a larger load present at the output of the I/O driver 100. As a result, the voltage across the drain and source of NFET MN2 increases up to about +2.8V during the transition of the output voltage VOUT from VDD to VSS, again exceeding the reliability limit of 2.0V if the device is manufactured in accordance with 45 nm, 40 nm or 28 nm technology.
Similarly, when the output voltage VOUT is at steady-state VSS as indicated in the third column of the timing diagram, the voltage at the drain of the PFET MP2 is substantially at VSS (e.g., 0V) and the voltage at the source of the PFET MP2 is at +2.2V. Thus, the voltage difference (e.g., VDS) across the drain and source of PFET MP2 is 2.2V. As previously discussed, this voltage differential of 2.2V across PFET MP2 would exceed the reliability limit of 2.0V if this device was manufactured in accordance with 45 nm, 40 nm or 28 nm technology.
Also, similarly, during the state or time interval where the output voltage VOUT is transitioning from VSS to VDD as indicated in the fourth column of the timing diagram, the voltage VPI at the source of PFET MP2 increases from +2.2V to +3.6V at a rate much faster than the output voltage VOUT increases from 0V to +3.6V due to generally a larger load present at the output of the I/O driver 100. As a result, the voltage across the drain and source of PFET MP2 increases up to about +2.8V during the transition of the output voltage VOUT from VSS to VDD, again exceeding the reliability limit of 2.0V if the device is manufactured in accordance with 45 nm, 40 nm or 28 nm technology.
Similarly, when the output voltage VOUT is substantially at steady-state VSS (e.g., 0V), which occurs in this graph between 11 ns and 15 ns, the voltage difference (VDS) across the drain and source of PFET MP2 is approximately at 2.2V, which exceeds the reliability limit of 2.0V for a 45 nm, 40 nm or 28 nm technology device. Also, during the transition of the output voltage VOUT from VSS to VDD, which occurs in this graph between 15 ns and 16 ns, the voltage difference (VDS) across the drain and source of PFET MP2 spikes up to approximately 2.8V, which substantially exceeds the reliability limit of 2.0V for a 45 nm, 40 nm or 28 nm technology device.
Thus, there is a need to implement lower voltage devices, such as those manufactured in accordance with 45 nm, 40 nm or 28 nm technology, for I/O driver operations, while controlling the voltages across the devices so as to not exceed the reliability limits. A discussion of exemplary I/O drivers that achieve at least this end is provided below.
In particular, the I/O driver 200 comprises a pull-up circuit including PFETs MP1 and MP2 and resistor R. The sources and drains of PFETs MP1 and MP2 are coupled in series with the resistor RP between a first voltage rail and an output of the I/O driver 200. A control voltage VPCTL for the pull-up circuit is applied to the gate of PFET MP1. A gate bias voltage VPBIAS is applied to the gate of PFET MP2 The operation of the pull-up circuit is similar to that of pull-up circuit of the I/O driver 100 previously discussed, with the exception that the gate bias voltage VPBIAS is varied in order to maintain the voltage difference across the gate and source of PFET MP2 at or below the reliability limit or a defined threshold.
The I/O driver 200 further comprises a pull-up compensation circuit for applying a compensation voltage VC to the source of PFET MP2 at a defined time and for a defined duration in order to maintain the voltage across the drain and source of PFET MP2 at or below the reliability limit or a defined threshold. The pull-up compensation circuit comprises an NFET MNC having a source and drain coupled between a source of the compensation voltage VC and the source of PFET MP2. A control voltage VPCCTL is applied to the gate of the NFET MNC. The compensation voltage VC may be set to VDD/2 (e.g., +1.8V).
The I/O driver 200 further comprises a pull-down circuit including NFETs MN1 and MN2 and resistor RN. The resistor RN and the drains and sources of NFETs MN1 and MN2 are coupled in series between the output of the I/O driver 200 and a second voltage rail. A control voltage VPCTL for the pull-down circuit is applied to the gate of NFET MN1. A gate bias voltage VNBIAS is applied to the gate of NFET MN2 The operation of the pull-down circuit is similar to that of the pull-down circuit of the I/O driver 100 previously discussed, with the exception that the gate bias voltage VNBIAS is varied in order to maintain the voltage difference across the drain and source of NFET MN2 at or below the reliability limit or a defined threshold.
The I/O driver 200 further comprises a pull-down compensation circuit for applying the compensation voltage VC to the source of NFET MN2 at a defined time and for a defined duration in order to maintain the voltage difference across the drain and source of NFET MN2 at or below the reliability limit or a defined threshold. The pull-down compensation circuit comprises a PFET MPC having a source and drain coupled between a source of the compensation voltage VC and the source of NFET MN2. A control voltage VNCCTL is applied to the gate of the PFET MPC. As previously discussed, the compensation voltage VC may be set to VDD/2 (e.g., +1.8V). A discussion of the operation of the I/O driver 200 is provided below with reference to
The y- or vertical axis of the timing diagram represents the various voltages of the I/O driver 200. For instance, from top to bottom, the voltages are: (1) the control voltage VPCTL for PFET MP1; (2) the control voltage VPCCTL for NFET MNC; (3) the voltage VPI at the source of PFET MP2; (4) the gate bias voltage VPBIAS for PFET MP2; (5) the output voltage VOUT of the I/O driver 200; (6) the gate bias voltage VNBIAS for NFET MN2; (7) the voltage VNI at the source of NFETs MN2; (8) the control voltage VNCCTL for the PFET MPC; and (9) the control voltage VNCTL for NFET MN1.
In operation, during the state or time interval where the output voltage VOUT of the I/O driver 200 is substantially at steady-state VDD as indicated in the first column of the timing diagram, the control voltage VPCTL and the gate bias voltage VPBIAS are both substantially at VDD/2 (e.g., +1.8V) so that both PFETs MP1 and MP2 are turned on. Both PFETs MP1 and MP2 being turned on results in substantially coupling VDD to the output of the I/O driver 200, thereby causing the output voltage VOUT to be at substantially VDD (e.g., +3.6V). Also, at this state or time interval, the control voltage VPCCTL for the NFET MNC is set to VDD/2 (e.g., +1.8V) to turn off NFET MNC to prevent the coupling of the compensation voltage VC to the source of PFET MP2. Accordingly, the voltage VPI at the source of PFET MP1 is also substantially at VDD (e.g., +3.6V).
Also, during this state or time interval, the control voltage VNCTL is set to VSS (e.g., 0V) to turn off NFET MN1. The gate bias voltage VNBIAS of NFET MN2 is set to VDD/2 (e.g., +1.8V). The control voltage VNCCTL is set to VSS (e.g., 0V) to turn on PFET MPC. The turning on of PFET MPC causes the compensation voltage VC to be applied to the source of NFET MN2. Thus, the voltage across the drain and source of NFET MN2 is substantially VDD/2 (e.g., 1.8V), which is less than the reliability limit or defined threshold of 2.0V. Thus, when the output voltage VOUT is substantially at steady-state VDD, the compensation voltage VC is applied to the source of NFET MN2 in order to maintain the voltage across the drain and source of NFET MN2 at or below the reliability limit of the device MN2. This ensures that the device MN2 is not overstressed or damaged due to voltages across its terminals that exceed its reliability limits. Since, during this state or time interval, the gate bias voltage VNBIAS of NFET MN2 is substantially the same as the compensation voltage VC (i.e., VDD/2), which is applied to the source of NFET MN2, the device MN2 is turned off. Thus, both NFET MN1 and MN2 are turned off to isolate the output of the I/O driver 200 from VSS.
During the state or time interval where the output voltage VOUT of the I/O driver 200 is transitioning from VDD to VSS as indicated in the second column of the timing diagram, the control voltage VPCTL for PFET MP1 is raised to VDD (e.g., +3.6V) to turn off PFET MP1. The gate bias voltage VPBIAS of PFET MP2 remains at VDD/2 (e.g., +1.8V). The control voltage VPCCTL is raised to VDD (e.g., 3.6V) to turn on NFET MNC in order for the compensation voltage VC to be applied to the source of PFET MP2. Since, the gate bias voltage VPBIAS of PFET MP2 is substantially the same as the compensation voltage VC (e.g., VDD/2), which is applied to the source of PFET MP2, the device MP2 is turned off. Thus, both PFETs MP1 and MP2 are turned off to isolate the output of the I/O driver 200 from VDD. The compensation voltage VC being applied to the source of PFET MP2 ensures that the voltage across the drain and source of PFET MP2 is maintained at or below a reliability limit or defined threshold (e.g., 2.0V) when the output voltage VOUT reaches VSS (e.g., 0V).
Also, at substantially the beginning of the time interval where the output voltage VOUT is transitioning from VDD to VSS, the gate control voltage VNBIAS for NFET MN2 is raised to VDD (e.g., +3.6V) for a defined interval Δt1 to turn on NFET MN2. Also, during the defined time interval Δt1, the control voltage VNCTL for NFET MN1 is maintained at VSS (e.g., 0V) to maintain NFET MN1 turned off, and the control voltage VNCCTL for PFET MPC is also maintained at VSS (e.g., 0V) to maintain PFET MPC turned on. Thus, during the first portion Δt1 of the transition of the output voltage VOUT from VDD to VSS, a first discharge path is formed from the output of the I/O driver 200 to the source of the compensation voltage VC by way of NFET MN2 and PFET MPC. This prevents the voltage across the drain and source of NFET MN2 from exceeding the reliability limit or defined threshold during the initial phase of the transition of the output voltage from VDD to VSS.
When the output voltage VOUT has decreased to a level where the difference between VOUT and VSS is at or below the defined threshold or the reliability limit of PFET MP2 (e.g., ≦+2.0V), marking the end of the defined time interval Δt1, the control voltage VNCTL for NFET MN1 is raised to VDD/2 (e.g., +1.8V) to turn on NFET MN1, the control voltage VNCCTL for PFET MPC is also raised to VDD/2 (e.g., +1.8V) to turn off PFET MPC, and the gate bias voltage VNBIAS is lowered to VDD/2 (e.g., +1.8V) to maintain NFET MN2 turned on with a lower gate-to-source voltage (e.g., lower than the defined threshold or reliability limit of 2.0V). Thus, during the second portion Δt2 of the transition of the output voltage VOUT from VDD to VSS, a second discharge path is formed from the output of the I/O driver 200 to the second voltage rail by way of NFETs MN2 and MN1. Since, as discussed above, the output voltage VOUT has decreased to at or below the defined threshold or reliability limit of NFET MN2 (e.g., (e.g., ≦+2.0V) at the beginning of the second time interval Δt2, the turning on of NFET MN1 and consequently applying VSS to the source of NFET MN2 at the beginning of the second time interval Δt2 does not cause any reliability problems for NFET MN2 since the voltage across NFET MN2 continues to stay at or below the reliability limit or defined threshold. Thus, during both portions Δt1 and Δt2, the voltage across the drain and source of NFET MN2 remains at or below the defined threshold or reliability limit of the device MN2.
Once the voltages have transitioned, they will remain substantially constant during the state or time interval where the output voltage VOUT is substantially at steady-state VSS, as indicated in the third column of the timing diagram. That is, during this state or time interval, the control voltage VPCTL is at VDD (e.g., +3.6V) to keep PFET MP1 turned off; the control voltage VPCCTL is at VDD to keep NFET MNC turned on so that the compensation voltage VC (e.g., +1.8V) is applied to the source of PFET MP2 to maintain the voltage across the drain and source of PFET MP2 at or below the reliability limit or defined threshold while the output voltage VOUT is at VSS; the gate bias voltage VPBIAS for PFET MP2 is at VDD/2 (e.g., +1.8V) to keep PFET MP2 turned off. Due to both PFETs MP1 and MP2 being turned off during this state or time interval, the pull-up circuit isolates the output from the first voltage rail, and the application of the compensation voltage VC to the source of PFET MP2 ensures that the voltage across the device MP2 is at or below the reliability limit or defined threshold.
Also, during the state or time interval where the output voltage VOUT is at substantially VSS as indicated in the third column of the timing diagram, the control voltage VNCTL for NFET MN1 is at VDD/2 (e.g., +1.8V) to maintain NFET MN1 turned on; the control voltage VNCCTL for PFET MPC is at VDD/2 (e.g., +1.8V) to maintain PFET MPC turned off to prevent the compensation voltage VC to be applied to the source of NFET MN2; and the gate bias voltage VNBIAS for NFET MN2 is at VDD/2 (e.g., +1.8V) so that NFET MN2 is turned on. Both NFETs MN1 and MN2 being turned on causes the second voltage rail to be coupled to the output of the I/O driver 200 to maintain the output voltage VOUT at substantially VSS (e.g., 0V). Consequently, the voltage VNI at the source of NFET MN2 is also substantially at VSS (e.g., 0V).
During the state or time interval where the output voltage VOUT of the I/O driver 200 is transitioning from VSS to VDD as indicated in the fourth column of the timing diagram, the control voltage VNCTL for NFET MN1 is lowered to VSS (e.g., 0V) to turn off NFET MN1. The gate bias voltage VNBIAS of NFET MN2 remains at VDD/2 (e.g., +1.8V). The control voltage VNCCTL is lowered to VSS (e.g., 0V) to turn on PFET MPC in order for the compensation voltage VC (e.g., VDD/2=+1.8V) to be applied to the source of NFET MN2. Since, the gate bias voltage VNBIAS of NFET MN2 is substantially the same as the compensation voltage VC (both being VDD/2 or +1.8V), which is applied to the source of NFET MP2, the device MN2 is turned off. Thus, both NFETS MN1 and MN2 are turned off to isolate the output of the I/O driver 200 from the second voltage rail. The compensation voltage VC being applied to the source of NFET MN2 ensures that the voltage across the drain and source of NFET MN2 is maintained at or below a reliability limit or defined threshold (e.g., ≦+2.0V) when the output voltage VOUT reaches VDD (e.g., +3.6V).
Also, at substantially the beginning of the time interval where the output voltage VOUT is transitioning from VSS to VDD, the gate control voltage VPBIAS for PFET MP2 is lowered to VSS (e.g., 0V) for a defined interval Δt3 to turn on PFET MP2. Also, during the defined time interval Δt3, the control voltage VPCTL for PFET MP1 is maintained at VDD (e.g., +3.6V) to maintain PFET MP1 turned off, and the control voltage VPCCTL for NFET MNC is also maintained at VDD (e.g., +3.6V) to maintain NFET MNC turned on. Thus, during a first portion Δt3 of the transition of the output voltage VOUT from VSS to VDD, a first charge path is formed from the source of the compensation voltage VC to the output of the I/O driver 200 by way of NFET MNC and PFET MP2. This prevents the voltage across the drain and source of PFET MN2 from exceeding the reliability limit or defined threshold during the initial phase of the transition of the output voltage VOUT from VSS to VDD.
When the output voltage VOUT has increased to a level where the difference between VDD and VOUT is at or below the defined threshold or the reliability limit of PFET MP2 (e.g., ≦+2.0V), marking the end of the defined time interval Δt3, the control voltage VPCTL for PFET MP1 is lowered to VDD/2 (e.g., +1.8V) to turn on PFET MP1, the control voltage VPCCTL for NFET MNC is also lowered to VDD/2 (e.g., +1.8V) to turn off NFET MNC, and the gate bias voltage VPBIAS is raised to VDD/2 (e.g., +1.8V) to maintain PFET MP2 turned on with a lower gate-to-source voltage (e.g., lower than the defined threshold or reliability limit of 2.0V). Thus, during the second portion Δt4 of the transition of the output voltage VOUT from VSS to VDD, a second charge path is formed from the first voltage rail to the output of the I/O driver 200 by way of PFETs MP1 and MP2. Since, as discussed above, the output voltage VOUT has increased to a level where the difference between VDD and VOUT is at or below the defined threshold or reliability limit of PFET MP2 (e.g., (e.g., ≦+2.0V) at the beginning of the second time interval Δt3, the turning on of PFET MP1 and consequently, the coupling of VDD to the source of PFET MP2 at the beginning of the second time interval Δt4 does not cause any reliability problems for PFET MP2 since the voltage across PFET MP2 continues to stay at or below the reliability limit or defined threshold. Thus, during both portions Δta and Δt4, the voltage across the drain and source of PFET MP2 remains at or below the defined threshold or reliability limit of the device MP2. Once the voltages have transitioned, they will remain substantially constant during the state or time interval where the output voltage VOUT is at substantially VDD, as indicated in the last (or first) column of the timing diagram.
Similarly, when the output voltage VOUT is substantially at steady-state VSS (e.g., 0V), which occurs in this graph between 10 ns to 14 ns, the voltage (VDS) across the drain and source of PFET MP2 is approximately at 1.8V, which does not exceed the reliability limit of 2.0V for a 45 nm, 40 nm or 28 nm technology device. Also, during the transition of the output voltage VOUT from VSS to VDD, which occurs in this graph between 14 ns and 15 ns, the voltage (VDS) across the drain and source of PFET MP2 does not exceed the reliability limit of 2.0V for a 45 nm, 40 nm or 28 nm technology device. Thus, the I/O driver 200 allows for lower voltage devices (e.g., 45 nm, 40 nm or 28 nm technology device) for applications that require higher output voltages (e.g., +3.6V).
The pull-up circuit 310, in turn, comprises switching devices MP1 and MP2 and RP, all coupled in series between a first voltage rail and an output of the I/O driver 300. Although, in this example, the switching devices MP1 and MP2 are illustrated as p-channel CMOS, it shall be understood that the devices may comprise any type of switching device, including other types of field effect transistors as well as other types of bipolar transistors. The switching devices MP1 and MP2 perform at least two functions: (1) to couple the first voltage rail to the output so that the output voltage VOUT may be maintained substantially at a steady-state first rail voltage VDD; and (2) to isolate the output from the first voltage rail when the output voltage VOUT is at a steady-state second rail voltage VSS.
The pull-down circuit 350, in turn, comprises switching devices MN1 and MN2 and resistor RN, all coupled in series between the output of the I/O driver 300 and a second voltage rail. Although, in this example, the switching devices MN1 and MN2 are illustrated as n-channel CMOS, it shall be understood that the devices may comprise any type of switching device, including other types of field effect transistors as well as other types of bipolar transistors. The switching devices MN1 and MN2 perform at least two functions: (1) to couple the output to the second voltage rail so that the output voltage VOUT may be maintained substantially at the steady-state second rail voltage (VSS); and (2) to isolate the output from the second voltage rail when the output voltage VOUT is at the steady-state first rail voltage (VDD).
The pull-up control circuit 320 is configured to generate control voltages VPCTL and VPBIAS for the pull-up circuit 310 under the control of the controller 390. The pull-up control circuit 320 comprises a pre-driver 325, a two-pole-one-throw switching device 330, and a voltage source 335. The pre-driver 325 generates control voltage VPCTL based on a command to drive the output voltage VOUT to either the first rail voltage VDD or the second rail voltage VSS. For instance, if the command dictates that the output voltage VOUT is to be driven to the first rail voltage VDD, then the pre-driver 325 generates the control voltage VPCTL at substantially VDD/2 in order to cause switching device MP1 to turn on. Conversely, if the command dictates that the output voltage VOUT is to be driven to the second rail voltage VSS, then the pre-driver 325 generates the VPCTL at substantially VDD in order to cause switching device MP1 to turn off.
The voltage source 335 generates a bias voltage VPBIAS for switching device MP2. With an exception as discussed further herein, the bias voltage VPBIAS is substantially constant and set to VDD/2. Thus, with bias voltage VPBIAS set accordingly, the switching device MP2 turns on in response to switching device MP1 turning on, and turns off in response to switching device MP1 turning off. Hence, in response to the control voltage VPCTL set to VDD/2, both switching devices MP1 and MP2 are turned on to couple the first voltage rail to the output, so that the output voltage VOUT may be maintained substantially at the steady-state first rail voltage VDD. And, in response to the control voltage VPCTL set to VDD, both switching devices MP1 and MP2 are turned off to isolate the output from the first voltage rail when the output voltage VOUT is substantially at the steady-state second rail voltage VSS. As discussed in more detail herein, the two-pole-one-throw switching device 330 and the voltage source 335 being controllable by the controller 390 are for the purpose of maintaining the voltage across the switching device MP2 at or below a defined threshold during operation of the I/O driver 300.
The pull-down control circuit 360 is configured to generate control voltages VNCTL and VNBIAS for the pull-down circuit 360 under the control of the controller 390. The pull-down control circuit 360 comprises a pre-driver 365, a two-pole-one-throw switching device 370, and a voltage source 375. The pre-driver 365 generates control voltage VNCTL based on a command to drive the output voltage VOUT to either the first rail voltage VDD or the second rail voltage VSS. For instance, if the command dictates that the output voltage VOUT is to be driven to the second rail voltage VSS, the pre-driver 365 generates the control voltage VNCTL at substantially VDD/2 in order to cause switching device MN1 to turn on. Conversely, if the command dictates that the output voltage VOUT is to be driven to the first rail voltage VDD, the pre-driver 365 generates the VNCTL at substantially VSS in order to cause switching device MN1 to turn off.
The voltage source 375 generates a bias voltage VNBIAS for switching device MN2. With an exception as discussed further herein, the bias voltage VNBIAS is substantially constant and set to VDD/2. Thus, with bias voltage VNBIAS set accordingly, the switching device MN2 turns on in response to switching device MN1 turning on, and turns off in response to switching device MN1 turning off. Hence, in response to the control voltage VNCTL set to VDD/2, both switching devices MN1 and MN2 are turned on to couple the second voltage rail to the output so that the output voltage VOUT may be maintained substantially at the steady-state second rail voltage VSS. And, in response to the control voltage VNCTL set to VSS, both switching devices MN1 and MN2 are turned off to isolate the output from the second voltage rail when the output voltage VOUT is substantially at the steady-state first rail voltage VDD. As discussed in more detail herein, the two-pole-one-throw switching device 370 and the voltage source 375 being controllable by the controller 390 are for the purpose of maintaining the voltage across the switching device MN2 at or below a defined threshold during operation of the I/O driver 300.
The pull-up compensation circuit 340 is configured to apply a compensation voltage VC to the node between the switching devices MP1 and MP2 at the appropriate time and duration for the purpose of maintaining the voltage across the switching device MP2 at or below the defined threshold during operation of the I/O driver 300. The pull-up compensation circuit 340 comprises a voltage source 342 for generating the compensation voltage VC (which may be set to substantially VDD/2), a switching device MNC coupled between the voltage source 342 and the node between the switching devices MP1 and MP2, and a voltage source 344 for generating a control voltage VPCCTL for the switching device MNC under the control of the controller 390. Although, in this example, the switching device MNC is illustrated as an n-channel CMOS, it shall be understood that the device may be configured as any type of switching device, including other types of field effect transistors as well as other types of bipolar transistors.
The maintaining of the voltage across the switching device MP2 at or below the defined threshold operates as follows. When the output voltage VOUT is at the steady-state second voltage rail VSS, the controller 390 issues a command to the voltage source 344 to generate the control voltage VPCCTL at substantially VDD to turn on switching device MNC. The turning on of switching device MNC causes the compensation voltage VC to be applied to the node between switching devices MP1 and MP2. Thus, the voltage across switching device MP2 is substantially VDD/2, which is the difference between the compensation voltage VC at VDD/2 and the output voltage VOUT at VSS. This voltage difference VDD/2 may be at or below a reliability limit or threshold for the switching device MP2.
When the output voltage VOUT begins transitioning from the second rail voltage VSS to the first rail voltage VDD due to control voltages VPCTL and VNCTL being driven to VDD/2 and VSS, respectively, the controller 390 operates the switching device 330 to couple VDD (instead of VPCTL) to the switching device MP1 to maintain the switching device MP1 off during a first portion of the transition of the output voltage VOUT from the second rail voltage VSS to the first rail voltage VDD. Additionally, during the first portion, the controller 390 operates the voltage source 335 to produce VPBIAS at substantially VSS to maintain switching device MP2 turned on. This forms a first charge path from the compensation voltage source 342 to the output by way of switching devices MNC and MP2 to charge the output voltage VOUT from VSS to VDD/2. Thus, the maximum voltage across the switching device MP2 during the first portion is VDD/2, the difference between the compensation voltage VC and the second rail voltage VSS, which again may be at or below the reliability limit or threshold for the switching device MP2.
At the start of a second portion of the output voltage VOUT transitioning from the second rail voltage VSS to the first rail voltage VDD, which could be marked when the output voltage VOUT reaches VDD/2, the controller 390 controls the voltage source 344 to change the control voltage VPCCTL to VDD/2 in order to turn off switching device MNC. This decouples the compensation voltage VC from the node between the first and second switching devices MP1 and MP2. Also, the controller 390 operates the switching device 330 to couple the control voltage VPCTL (instead of VDD) to the switching device MP1 to turn on device MP1. Additionally, the controller 390 controls the voltage source 335 to produce VPBIAS at substantially VDD/2 to maintain switching device MP2 turned on. This forms a second charge path from the first voltage rail to the output by way of switching devices MP1 and MP2 to complete the charging of the output voltage VOUT to VDD. Again, the maximum voltage across the switching device MP2 during the second portion is VDD/2, the difference between the first rail voltage VDD and the output voltage VOUT at the start of the second portion of the transition of the output voltage from VSS to VDD.
The pull-down compensation circuit 380 is configured to apply a compensation voltage VC to the node between switching devices MN1 and MN2 at the appropriate time and duration for the purpose of maintaining the voltage across the switching device MN2 at or below the defined threshold during operation of the I/O driver 300. The pull-down compensation circuit 380 comprises a voltage source 382 for generating the compensation voltage VC (which may be set to substantially VDD/2), a switching device MPC coupled between the voltage source 382 and the node between switching devices MN1 and MN2, and a voltage source 384 for generating a control voltage VNCCTL for the switching device MPC under the control of the controller 390. Although, in this example, the switching device MPC is illustrated as a p-channel CMOS, it shall be understood that the device may be configured as any type of switching device, including other types of field effect transistors as well as other types of bipolar transistors. Additionally, although two different voltage sources 342 and 382 for the compensation voltage VC are illustrated to facilitate explanation, it shall be understood that there may be a single voltage source for the compensation voltage VC.
The maintaining of the voltage across the switching device MN2 at or below the defined threshold operates as follows. When the output voltage VOUT is substantially at the steady-state first rail voltage VDD, the controller 390 issues a command to the voltage source 384 to produce the control voltage VNCCTL at substantially VSS to turn on switching device MPC. The turning on of switching device MPC causes the compensation voltage VC to be applied to the node between switching devices MN1 and MN2. Thus, the voltage across switching device MN2 is substantially VDD/2, which is the difference between the output voltage VOUT at VSS and the compensation voltage VC at VDD/2. This voltage difference VDD/2 may be at or below a reliability limit or threshold for the switching device MN2.
When the output voltage VOUT begins transitioning from the first rail voltage VDD to the second rail voltage VSS due to control voltages VPCTL and VNCTL being driven to VDD and VDD/2, respectively, the controller 390 operates the switching device 370 to couple VSS (instead of VNCTL) to the switching device MN1 to maintain the switching device MN1 off during a first portion of the transition of the output voltage VOUT from the first rail voltage VDD to the second rail voltage VSS. Additionally, during the first portion, the controller 390 operates the voltage source 375 to produce VNBIAS at substantially VDD to maintain switching device MN2 turned on. This forms a first discharge path from the output to the voltage source 382 by way of switching devices MN2 and MPC to discharge the output voltage VOUT from VDD to VDD/2. Thus, the maximum voltage across the switching device MN2 during the first portion is VDD/2, the difference between the first rail voltage VDD and the compensation voltage VC, which again may be at or below the reliability limit or threshold for the switching device MN2.
At the start of a second portion of the output voltage VOUT transitioning from the first rail voltage VDD to the second rail voltage VSS, which could be marked when the output voltage VOUT has decayed to approximately VDD/2, the controller 390 controls the voltage source 384 to change the control voltage VNCCTL to VDD/2 in order to turn off switching device MPC. This decouples the compensation voltage VC from the node between the switching devices MN1 and MN2. Also, the controller 390 operates the switching device 370 to couple the control voltage VNCTL to the switching device MN1 to turn on device MN1. Additionally, the controller 390 controls the voltage source 375 to produce the bias voltage VNBIAS to VDD/2 to maintain switching device MN2 turned on. This forms a second discharge path from the output to the second voltage rail by way of switching devices MN1 and MN2 to complete the discharging of the output voltage VOUT to VSS. Again, the maximum voltage across the switching device MN2 during the second portion is VDD/2, the difference between the output voltage VOUT at the start of the second portion and the second rail voltage VSS.
According to the method 400, the controller 390 detects a command to transition the output voltage VOUT from the first rail voltage VDD to the second rail voltage VSS (block 402). The controller 390 may detect this command by monitoring the state of control voltages VPCTL and VNCTL. For instance, when control voltages VPCTL and VNCTL transition to respectively VDD and VDD/2, this indicates a command to transition the output voltage VOUT from VDD to VSS. In response to detecting the command pursuant to block 402, the controller 390 maintains the switching device 330 at a state where the control voltage VPCTL is applied to switching device MP1 to turn off device MP1, and the controller 390 maintains the voltage source 335 producing a bias voltage VPBIAS at VDD/2 so that switching device MP2 turns off in response to switching device MP1 turning off (block 404). Thus, the operation in block 404 is performed to isolate the output from the first voltage rail.
Also, in response to detecting the command to transition the output voltage VOUT from VDD to VSS pursuant to block 402, the controller 390 configures the voltage source 344 to produce the control voltage VPCCTL at VDD in order to turn on switching device MNC (block 406). This causes the compensation voltage VC to be applied to the node between switching devices MP1 and MP2 in order to maintain the voltage across switching device MP2 at or below a defined threshold when the output voltage VOUT is substantially at the steady-state second rail voltage VSS.
Also, in response to detecting the command to transition the output voltage VOUT from VDD to VSS pursuant to block 402, the controller 390 maintains the voltage source 384 producing VNCCTL at VSS in order to maintain switching device MPC turned on to maintain the voltage across switching device MN2 at or below the defined threshold for a first portion of the transition of the output voltage VOUT from VDD to VSS (block 408). Additionally, during the first portion, the controller 390 operates the voltage source 375 to produce the bias voltage VNBIAS at substantially VDD to turn on switching device MN2, and operates the switching device 370 to couple VSS to the switching device MN1 (instead of VNCTL) in order to maintain switching device MN1 off, during the first portion of the transition of the output voltage from VDD to VSS (block 410). The operations of blocks 408 and 410 result in a first discharging path being formed between the output and the compensation voltage source 382 by way of switching device MN2 and MPC in order to discharge the output voltage VOUT from substantially VDD to VDD/2 during the first portion of the transition.
When the output voltage VOUT has reached approximately VDD/2, the controller 390 configures the voltage source 384 to produce the control voltage VNCCTL at VDD/2 in order to turn off switching device MPC, operates the switching device 370 to couple VNCTL to switching device MN1 (instead of VSS) to turn on device MN1, and operates the voltage source 375 to produce the VNBIAS at VDD/2 to maintain switching device MP2 turned on while keeping the voltage across the terminals of the device MP2 below the defined threshold (block 412). The operations of block 412 result in a second discharging path formed between the output and the second voltage rail by way of switching device MN2 and MN1 in order to complete the discharging of the output voltage VOUT from substantially VDD/2 to VSS during the second or remaining portion of the transition of VOUT from VDD to VSS.
As specified in block 414, while the output voltage VOUT is substantially at the steady-state second rail voltage VSS, the controller 390: (1) maintains switching devices MP1 and MP2 turned off to isolate the output from the first voltage rail; (2) maintains switching device MNC turned on to couple the compensation voltage VC to the node between devices MP1 and MP2 to maintain the voltage across device MP2 at or below a defined threshold; (3) maintains switching devices MN1 and MN2 turned on to couple the output to the second voltage rail to maintain the output voltage VOUT at substantially the steady-state second rail voltage VSS; and (4) maintains the switching device MPC off to decouple the compensation voltage VC from the node between switching devices MN1 and MN2.
At a later time, the controller 390 detects a command to transition the output voltage VOUT from the second rail voltage VSS to the first rail voltage VDD (block 416). The controller 390 may detect this command by monitoring the state of control voltages VPCTL and VNCTL. For instance, when control voltages VPCTL and VNCTL transition to VDD/2 and VSS, respectively, this indicates a command to transition the output voltage VOUT from VSS to VDD. In response to detecting the command pursuant to block 416, the controller 390 maintains the switching device 370 at a state where the control voltage VNCTL is applied to switching device MN1 to turn off device MN1, and maintains the voltage source 375 producing a bias voltage VNBIAS at VDD/2 so that switching device MN2 turns off in response to switching device MN1 turning off (block 418). Thus, the operations in block 418 are performed to isolate the output from the second voltage rail.
Also, in response to detecting the command to transition the output voltage VOUT from VSS to VDD pursuant to block 416, the controller 390 configures the voltage source 384 to produce the control voltage VNCCTL at VSS in order to turn on switching device MPC (block 420). This causes the compensation voltage VC to be applied to the node between switching devices MN1 and MN2 in order to maintain the voltage across switching device MN2 at or below a defined threshold when the output voltage VOUT is substantially at the steady-state first rail voltage VDD.
Also, in response to detecting the command to transition the output voltage VOUT from VSS to VDD pursuant to block 416, the controller 390 maintains the voltage source 344 producing VPCCTL at VDD in order to maintain switching device MNC turned on to maintain the voltage across switching device MP2 at or below the defined threshold for a first portion of the transition of the output voltage VOUT from VSS to VDD (block 422). Additionally, during the first portion, the controller 390 operates the voltage source 335 to produce the bias voltage VPBIAS at substantially VSS to turn on switching device MP1, and operates the switching device 330 to couple VDD to the switching device MP1 (instead of VPCTL) in order to maintain switching device MP1 turned off, during the first portion of the transition of the output voltage from VSS to VDD (block 424). The operations of blocks 420 and 422 result in a first charging path formed between the compensation voltage source 342 and the output by way of switching device MNC and MP2 in order to charge the output voltage VOUT from substantially VSS to VDD/2 during the first portion of the transition.
When the output voltage VOUT has reached approximately VDD/2, the controller 390 configures the voltage source 344 to produce the control voltage VPCCTL at VDD/2 in order to turn off switching device MNC, operates the switching device 330 to couple VPCTL to switching device MP1 (instead of VDD) to turn on device MP1, and operates the voltage source 335 to produce VPBIAS at substantially VDD/2 to maintain switching device MP1 turned on which maintaining the voltage across the terminals at or below the defined threshold (block 426). The operations of block 422 result in a second charging path being formed from the first voltage rail to the output rail by way of switching device MP2 and MP1 in order to complete the charging of the output voltage VOUT from substantially VDD/2 to VDD during the second or remaining portion of the transition of VOUT from VSS to VDD.
As specified in block 428, while the output voltage VOUT is at substantially the steady-state first rail voltage VDD, the controller 390: (1) maintains switching devices MN1 and MN2 turned off to isolate the output from the second voltage rail; (2) maintains switching device MPC turned on to couple the compensation voltage VC to the node between devices MN1 and MN2 to maintain the voltage across device MN2 at or below a defined threshold; (3) maintains switching devices MP1 and MP2 turned on to couple the first voltage rail to the output to maintain the output voltage VOUT at substantially the steady-state first rail voltage VDD; and (4) maintains the switching device MNC off to decouple the compensation voltage VC from the node between switching devices MP1 and MP2.
Various aspects of the disclosure have been described above. It should be apparent that the teachings herein may be embodied in a wide variety of forms and that any specific structure, function, or both being disclosed herein is merely representative. Based on the teachings herein one skilled in the art should appreciate that an aspect disclosed herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, such an apparatus may be implemented or such a method may be practiced using another structure, functionality, or structure and functionality in addition to or other than one or more of the aspects set forth herein. As an example of some of the above concepts, in some aspects concurrent channels may be established based on pulse repetition frequencies. In some aspects concurrent channels may be established based on pulse position or offsets. In some aspects concurrent channels may be established based on time hopping sequences. In some aspects concurrent channels may be established based on pulse repetition frequencies, pulse positions or offsets, and time hopping sequences.
Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Also, it should be understood that any reference to an element herein using a designation such as “first,” “second,” and so forth does not generally limit the quantity or order of those elements. Rather, these designations are generally used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements may be employed there or that the first element must precede the second element in some manner. Also, unless stated otherwise a set of elements comprises one or more elements. In addition, terminology of the form “at least one of A, B, or C” or “one or more of A, B, or C” or “at least one of the group consisting of A, B, and C” used in the description or the claims means “A or B or C or any combination of these elements.”
As used herein, the term “determining” encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining, and the like. Also, “determining” may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Also, “determining” may include resolving, selecting, choosing, establishing, and the like.
Those of skill in the art understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, any data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Those of skill would further appreciate that the various illustrative logical blocks, modules, processors, means, circuits, and algorithm steps described in connection with the aspects disclosed herein may be implemented as electronic hardware (e.g., a digital implementation, an analog implementation, or a combination of the two, which may be designed using source coding or some other technique), various forms of program or design code incorporating instructions (which may be referred to herein, for convenience, as “software” or a “software module”), or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented within or performed by an integrated circuit (“IC”), an access terminal, or an access point. The IC may comprise a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, electrical components, optical components, mechanical components, or any combination thereof designed to perform the functions described herein, and may execute codes or instructions that reside within the IC, outside of the IC, or both. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
It is understood that any specific order or hierarchy of steps in any disclosed process is an example of a sample approach. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged while remaining within the scope of the present disclosure. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
The functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may comprise a processing system in a wireless node. The processing system may be implemented with a bus architecture. The bus may include any number of interconnecting buses and bridges depending on the specific application of the processing system and the overall design constraints. The bus may link together various circuits including a processor, machine-readable media, and a bus interface. The bus interface may be used to connect a network adapter, among other things, to the processing system via the bus. The network adapter may be used to implement the signal processing functions of the PHY layer. In the case of a user terminal 120 (see
The processor may be responsible for managing the bus and general processing, including the execution of software stored on the machine-readable media. The processor may be implemented with one or more general-purpose and/or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuitry that can execute software. Software shall be construed broadly to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Machine-readable media may include, by way of example, RAM (Random Access Memory), flash memory, ROM (Read Only Memory), PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), registers, magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof. The machine-readable media may be embodied in a computer-program product. The computer-program product may comprise packaging materials.
In a hardware implementation, the machine-readable media may be part of the processing system separate from the processor. However, as those skilled in the art will readily appreciate, the machine-readable media, or any portion thereof, may be external to the processing system. By way of example, the machine-readable media may include a transmission line, a carrier wave modulated by data, and/or a computer product separate from the wireless node, all which may be accessed by the processor through the bus interface. Alternatively, or in addition, the machine-readable media, or any portion thereof, may be integrated into the processor, such as the case may be with cache and/or general register files.
A processing system may include hardware, software, firmware or any combination thereof. The processing system may be configured as a general-purpose processing system with one or more microprocessors providing the processor functionality and external memory providing at least a portion of the machine-readable media, all linked together with other supporting circuitry through an external bus architecture. Alternatively, the processing system may be implemented with an ASIC (Application Specific Integrated Circuit) with the processor, the bus interface, the user interface in the case of an access terminal), supporting circuitry, and at least a portion of the machine-readable media integrated into a single chip, or with one or more FPGAs (Field Programmable Gate Arrays), PLDs (Programmable Logic Devices), controllers, state machines, gated logic, discrete hardware components, or any other suitable circuitry, or any combination of circuits that can perform the various functionality described throughout this disclosure. Those skilled in the art will recognize how best to implement the described functionality for the processing system depending on the particular application and the overall design constraints imposed on the overall system.
The machine-readable media may comprise a number of software modules. The software modules include instructions that, when executed by the processor, cause the processing system to perform various functions. The software modules may include a transmission module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. By way of example, a software module may be loaded into RAM from a hard drive when a triggering event occurs. During execution of the software module, the processor may load some of the instructions into cache to increase access speed. One or more cache lines may then be loaded into a general register file for execution by the processor. When referring to the functionality of a software module below, it will be understood that such functionality is implemented by the processor when executing instructions from that software module.
If implemented in software, the functions may be stored or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage medium may be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared (IR), radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Thus, in some aspects computer-readable media may comprise non-transitory computer-readable media (e.g., tangible media). In addition, for other aspects computer-readable media may comprise transitory computer-readable media (e.g., a signal). Combinations of the above should also be included within the scope of computer-readable media.
Thus, certain aspects may comprise a computer program product for performing the operations presented herein. For example, such a computer program product may comprise a computer-readable medium having instructions stored (and/or encoded) thereon, the instructions being executable by one or more processors to perform the operations described herein. In some aspects, a computer-readable medium comprises codes executable to perform one or more operations as taught herein. For certain aspects, the computer program product may include packaging material.
Further, it should be appreciated that modules and/or other appropriate means for performing the methods and techniques described herein can be downloaded and/or otherwise obtained by a user terminal and/or base station as applicable. For example, such a device can be coupled to a server to facilitate the transfer of means for performing the methods described herein. Alternatively, various methods described herein can be provided via storage means (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or floppy disk, etc.), such that a user terminal and/or base station can obtain the various methods upon coupling or providing the storage means to the device. Moreover, any other suitable technique for providing the methods and techniques described herein to a device can be utilized.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
This application claims the benefit of the filing date of Provisional Application Ser. No. 61/708,563, filed on Oct. 1, 2012, and entitled “System and Method of Implementing Input/Output Drivers with Low Voltage Devices,” which is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 61708563 | Oct 2012 | US |
