This disclosure relates generally to loading programmable counters and in particular but not exclusively, relates to loading a programmable counter of a Phase-Locked Loop (PLL).
Frequency-hopping spread spectrum (“FHSS”) is widely used in communication systems, in which PLLs may provide frequency stability and accuracy. However, PLLs may require a significant amount of settling/locking time to tune to a desired frequency channel.
Furthermore, when designing a communication application, the battery life is a key design parameter. One solution to extend the battery life of the communication application may be by periodically entering a “sleep” mode, in which many system components power down. However, the responsiveness of the communication application may be significantly compromised, because upon “awakening” from the sleep mode, the communication application may perform a complete resynchronization procedure to resume communication with the rest communication system. This resynchronization procedure may increase the frequency settling and locking time of the PLLs. Other solutions may include continuously maintaining synchronization, at the expense of decreased battery life.
Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.
Embodiments of a system and method of loading a programmable counter are described herein. In the following description numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
The illustrated embodiment of transmitter 105 includes a transmit digital signal processor (DSP) block 120, digital-to-analog converters (DAC) 122 and 124, low-pass filters 126 and 128, mixers 130 and 132, a phase shifter 134, a summing block 136, and an amplifier/buffer 138. Receiver 110 is illustrated as including an amplifier/buffer 140, mixers 142 and 144, a phase shifter 146, a complex band pass filter (BPF) 148, analog-to-digital converters (ADC) 150 and 152, and a demodulator and data out block 154.
Divider 220 divides down the higher speed frequency fout from VCO 215 for a comparison to the PFD reference signal by the PFD 205. Divider 225 divides an input frequency (e.g., from a crystal oscillator) before being presented to the PFD 205. In addition, a VCO calibration value may be loaded into the VCO 215 to calibrate the VCO frequency.
At 525, a new VCO CAL value may be loaded into the VCO. Although
The above-described PLL re-lock technique 500 may be referred as a clean “on-the-fly” PLL. “Clean” means gentle edge displacement of the feedback waveform, while “on-the-fly” refers to the condition in which the PLL can be reprogrammed during running without significantly disturbing the functionality of the PLL. The clean “on-the-fly” PLL allows for quick locking/settling into a new channel as compared to PLL re-lock technique 300 of
Referring to
At 825, a new VCO calibration value may be loaded into the VCO. Although
Divider 920 divides down the higher speed frequency fout from the VCO 915 for a comparison to the reference signal by the PFD 905. Divider 925 divides an input frequency (e.g., a reference frequency signal from a crystal oscillator) before being presented to the PFD 905. Divider 920 may be implemented using a programmable counter, such as the N divide loading example shown in
As PLL 900 operates, VCO 915 provides frequency output signal FOUT back to divider 920. Divider 920 divides the frequency of output signal FOUT by a number N (e.g., the currently loaded digital divide value). The output of the programmable counter (e.g., PFD feedback signal) is then fed back to PFD 905 for comparison with the PFD reference signal.
In one embodiment, any digital divide value that is currently stored in divide register 930 is loaded into the programmable counter upon completion of each counting cycle. Thus, processing device 935 may write a digital divide value to divide register 930 to change the count of the next counting cycle. However, processing device 935 and programmable counter 920 may operate asynchronously. That is, processing device 935 may operate at a clock speed that is independent and different that that of divider 920. Thus, the operation of PLL 900 may be drastically effected by the timing of when a divide value is written to divide register 930. For example, if processing device 935 were to be in the middle of writing a digital divide value to divide register 930 at the same time that the digital divide value were being loaded into divider 930, then the resultant value loaded into divider 920 may be unpredictable. This “glitch” in loading a digital divide value to divider 920 may result in longer or shorter counting cycles than desired. More importantly, the resultant edge displacement between the reference signal (e.g., PFD REF signal) and the feedback signal (e.g., PFD FB signal) may be large resulting in longer settling times and thus, greater current consumption by PLL circuit 900.
Accordingly, embodiments of the present invention provide a system and method of loading a programmable counter by writing a digital divide value to divide register 930 at a time that is responsive to a time remaining in the counting cycle of the programmable counter. It is in this manner that the writing of the digital divide value to divide register 930 can be completed before it is loaded into divider 920.
Still referring to
If decision block 1030 determines that there is sufficient time remaining in the current counting cycle for processing device 935 to compete a write to divide register 930, then process 1000 proceeds to block 1035 where processing device 935 completes such a write operation. However, if there is insufficient time in decision block 1030 to complete a write to divide register 930 then process 1000 waits until there is sufficient time. That is, in one embodiment, processing device 935 may be forced to wait until a next counting cycle until the new digital divide value N2 is written to divide register 930.
As further shown in
Static Random Access Memory (“SRAM”) 1210 and processing device 1211 are also coupled to system bus 1212. Processing device 1211 is coupled to non-volatile storage (“NVS”) 1216 which may be used to store firmware (e.g., control algorithms executable by processing device 1211 to implement process 500).
An analog block array 1218 is coupled to system bus 1212. Analog block array 1218 also may be configured to implement a variety of analog circuits (e.g., ADCs, analog filters, comparators, buffers, current sources, etc.) using configurable UMs. Analog block array 1218 is also coupled to an analog I/O unit 1224 which is coupled to I/O ports 1202.
As illustrated, radio transceiver 1230 is coupled to system bus 1212. IC 1200 may further include an IRQ, RFIN, RFOUT, and XTAL terminals. In one embodiment, the IRQ terminal may be coupled to I/O port 1202 to receive an interrupt request indicating that a channel change is requested. Furthermore, the illustrated embodiment of
In one embodiment, radio transceiver 1230 is implemented as a Frequency-hopping spread spectrum (“FHSS”) radio. In this embodiment, an interrupt request to change communications channel (e.g., block 1025 of process 100 in
The order in which some or all of the process blocks appear in each process should not be deemed limiting. Rather, one of ordinary skill in the art having the benefit of the present disclosure will understand that some of the process blocks may be executed in a variety of orders not illustrated.
The processes explained above are described in terms of computer software and hardware. The techniques described may constitute processing device-executable instructions embodied within a processing device-readable medium, that when executed by a processing device will cause the processing device to perform the operations described. Additionally, the processes may be embodied within hardware, such as an application specific integrated circuit (“ASIC”) or the like.
A medium readable by a processing device includes any mechanism that provides (e.g., stores) information in a form readable by a processing device (e.g., a computer, network device, personal digital assistant, manufacturing tool, any device with a set of one or more processors, etc.). For example, a processing device-readable medium includes recordable/non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, network attached storage (NAS), etc.). In one embodiment, a medium readable by a processing device is a computer readable storage medium.
As described above, radio transceiver 100 or PLL 900 may be incorporated into IC 1200, as well as, various other integrated circuits. Descriptions of radio transceiver 100 or PLL 900 may be generated and compiled for incorporation into other integrated circuits. For example, behavioral level code describing PLL 900, or portions thereof, may be generated using a hardware descriptive language, such as VHDL or Verilog, and stored to a processing-readable medium. Furthermore, the behavioral level code can be compiled into register transfer level (“RTL”) code, a netlist, or even a circuit layout and stored to a processing-readable medium. The behavioral level code, the RTL code, the netlist, and the circuit layout all represent various levels of abstraction to describe PLL 900.
The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
This application claims the benefit of U.S. Provisional Application No. 60/992,011, filed Dec. 3, 2007.
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