System and method of performing digital multi-channel audio signal decoding

Abstract

A system and method are disclosed for performing digital multi-channel decoding of a BTSC composite audio signal. Each subsequent stage of the digital multi-channel decoding process is performed at the lowest sampling rate that yields acceptable performance for that stage. Analog-to-digital conversion of the composite audio signal is performed first to generate a composite digital audio signal. After analog-to-digital conversion, all signal processing may be performed in the digital domain. The composite digital audio signal is digitally filtered to frequency compensate for variations caused by previous stages of processing, including IF demodulation. Digital channel demodulation and filtering are performed to isolate single channels of the composite digital audio signal such as SAP, L−R, and L+R channels. SAP and L−R channels are DBX decoded resulting in corresponding decoded signals using a unique combination of digital filters that are an efficient translation of a corresponding combination of analog filters. The decoded L−R channel and the L+R channel are re-matrixed to form left and right stereo signals. Any of the SAP signal, left and right stereo signals, and L+R channel signal may be sample rate converted and output at a standard audio output rate.

Description

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] [Not Applicable]

MICROFICHE/COPYRIGHT REFERENCE

[0003] [Not Applicable]

BACKGROUND OF THE INVENTION

[0004] Certain embodiments of the present invention relate to the processing of multi-channel television signals. More specifically, certain embodiments relate to a system and method for digitally decoding BTCS (Broadcast Television System Committee) audio signals.

[0005] During the 1980's, the FCC adopted the BTSC format as a standard for multi-channel television sound (MTS). Typically, the BTSC format is used with a composite TV signal that includes a video signal as well as the BTSC format for the sound reproduction.

[0006] The BTSC format is similar to FM stereo but has the ability to carry two additional audio channels. Left plus right (L+R) channel mono information is transmitted in a way similar to stereo FM in order to ensure compatibility with monaural television receivers. A 15.734 KHz pilot signal is used, instead of the FM stereo 19 KHz pilot signal, which allows the pilot signal to be phase-locked to the horizontal line frequency. A double sideband-suppressed carrier at twice the frequency of the pilot transmits the left minus right (L−R) stereo information. The stereo information is DBX encoded to aid in noise reduction. An SAP channel is located at 5 times the pilot frequency. The SAP channel may be used for second language or independent source program material. A professional audio channel may be added at 6.5 times the pilot frequency in order to accommodate additional voice or data.

[0007] Stereo tuners and demodulator units capable of decoding the BTSC format have been on the market for some time. The front end of the units typically includes analog components or integrated circuit chips. Traditionally, BTSC decoding has been done in the analog domain requiring larger, more expensive implementations that consume a significant amount of power. Previous digital implementations may not be optimized, requiring many clock cycles to perform various processing functions.

[0008] It is desirable to perform BTSC decoding in the digital domain on a block of an ASIC chip such that the implementation is optimized for reduced complexity and cost. By reducing the complexity, fewer clock cycles are required for processing, and power consumption is also reduced.

[0009] Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with embodiments of the present invention as set forth in the remainder of the present application with reference to the drawings.

[0010] A need exists for an approach to perform efficient multi-channel audio signal decoding in the digital domain by reducing the complexity of the hardware required, therefore reducing cost and power consumption.

BRIEF SUMMARY OF THE INVENTION

[0011] An embodiment of the present invention provides efficient, low cost digital multi-channel audio signal decoding of BTSC audio signals in the digital domain. In such an environment, several stages of digital signal processing are used where each subsequent stage of the digital multi-channel decoding process is performed at the lowest sampling rate that yields acceptable performance for that stage. Efficient pipelined processing is used to execute the various processing functions in order to reduce clock cycles and addressing to memory.

[0012] A method is provided for performing digital multi-channel decoding of a DBX-encoded composite audio signal. Each subsequent stage of the digital multi-channel decoding process is performed at the lowest sampling rate that yields acceptable performance for that stage. Analog-to-digital conversion of the composite audio signal is performed first to generate a composite digital audio signal. After analog-to-digital conversion, all signal processing may be performed in the digital domain. The composite digital audio signal is digitally filtered to compensate for uneven frequency response caused by previous stages of processing, including IF demodulation. Digital channel demodulation and filtering are performed to isolate single channels of the composite digital audio signal such as SAP, L−R, and L+R channels. SAP and L−R channels are DBX decoded resulting in corresponding decoded signals using a unique combination of digital filters that are an efficient translation of a corresponding combination of analog filters. The decoded L−R channel and the L+R channel are re-matrixed to form left and right stereo signals. Any of the SAP signal, left and right stereo signals, and L+R channel signal may be sample rate converted and output at a standard audio output rate.

[0013] A system is provided on an ASIC chip for performing digital multi-channel audio signal decoding. The system comprises a sigma-delta analog-to-digital (A/D) conversion block operating on a composite analog audio signal to generate a composite digital audio signal, a clock generation block generating a master clock signal and other clock signals used in the multi-channel audio signal decoding process, and a DSP processing block including a five-stage pipelined data path performing certain digital multi-channel audio signal processing functions in response to a set of instructions. The system further includes an input buffer block connected between the sigma-delta A/D conversion block and the DSP processing block to transfer the composite digital audio signal to the DSP processing block, a configuration register block interfacing to the DSP processing block, the input buffer block, and the sigma-delta A/D conversion block, and an output buffer block interfacing to the DSP processing block and the clock generation block to output standard audio output signals at standard audio output rates. The five-stage pipelined data path comprises a memory address calculation stage, a memory data fetch stage, a multiplication stage, an accumulation/mantissa-generation/signal-shifter stage, and a registers/memory-write stage.

[0014] Certain embodiments of the present invention afford an approach to achieve efficient, low cost digital multi-channel audio signal decoding of BTSC audio signals in the digital domain. Certain embodiments of the present invention use several stages of digital signal processing where each subsequent stage of the digital multi-channel decoding process is performed at the lowest sampling rate that yields acceptable performance for that stage.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG. 1 is an illustration of the various components of a composite audio signal to be decoded in accordance with an embodiment of the present invention.

[0016] FIG. 2 is a schematic functional block diagram of the decoding method used to decode the composite audio signal of FIG. 1 in accordance with an embodiment of the present invention.

[0017] FIG. 2B is a schematic functional block diagram of pilot signal detection and DSB demodulation performed in the method of FIG. 2 in accordance with an embodiment of the present invention.

[0018] FIG. 3 is a schematic functional block diagram of a combination of digital filter transfer functions used to perform DBX decoding in accordance with an embodiment of the present invention.

[0019] FIG. 3B is a schematic functional block diagram of a transfer function of FIG. 3 in accordance with an embodiment of the present invention.

[0020] FIG. 4 illustrates the translated analog and digital transfer function equations corresponding to the DBX decoding performed in FIG. 3 in accordance with an embodiment of the present invention.

[0021] FIG. 5 is a schematic block diagram of a decoding system implemented on an ASIC chip and used to implement the decoding method of FIG. 2 in accordance with an embodiment of the present invention.

[0022] FIG. 6 is a flowchart illustration of the data path processing performed by the pipelined decoding system of FIG. 5 in accordance with an embodiment of the present invention.

[0023] FIG. 7 is a table of instructions that may be implemented by the data path processing of FIG. 6 in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0024] FIG. 1 is an illustration of the various components of a BTSC composite audio signal 10 to be decoded in accordance with an embodiment of the present invention. During the 1980's, the FCC adopted the BTSC format as a standard for multi-channel television sound (MTS). Typically, the BTSC format is used with a composite TV signal that includes a video signal as well as the BTSC format for the sound reproduction.

[0025] The BTSC format is similar to FM stereo but has the ability to carry two additional audio channels. Left plus right (L+R) channel mono information 20 is transmitted in a way similar to stereo FM in order to ensure compatibility with monaural television receivers. A 15.734 KHz pilot signal 25 is used, instead of the FM stereo 19 KHz pilot signal, which allows the pilot signal 25 to be phase-locked to the horizontal line frequency. A double sideband-suppressed carrier, at twice the frequency of the pilot, transmits the left minus right (L−R) stereo information 30. The stereo information is DBX encoded to aid in noise reduction. An SAP channel 40 is located at 5 times the pilot frequency. The SAP channel 40 may be used for second language or independent source program material. A professional audio channel (not shown) may be added at 6.5 times the pilot frequency 25 in order to accommodate additional voice or data.

[0026] FIG. 2 is a schematic functional block diagram of the decoding method 100 used to decode the BTSC composite audio signal 10 of FIG. 1 in accordance with an embodiment of the present invention. The method 100 comprises analog-to-digital conversion 110, digital amplitude compensation 115, digital channel demodulation and filtering 120, DBX decoding 130, stereo re-matrixing 140, and sample rate conversion 150.

[0027] The composite audio signal 10 is an analog base-band signal and is converted to a composite digital audio signal 11 in the analog-to-digital conversion step 110. As a result, subsequent processing may be performed in the digital domain. The analog-to-digital conversion step 110 operates at a clock rate of 20.25 MHz which is created by dividing down a master clock signal of 162 MHz by a factor of eight as shown in FIG. 2. The composite digital audio signal 11 is output from the analog-to-digital conversion step 110 at a sample rate of 316.4 KHz and is presented to the digital amplitude compensation step 115. The sample rate of 316.4 KHz is derived from the master clock signal by dividing down by a factor of 512.

[0028] Step 115, the compensation of uneven frequency response, applies a second-order IIR filter to digitally compensate for amplitude unevenness in the composite digital audio signal due to an uneven frequency response of a previous IF demodulation stage that is not part of the decoding process described herein. The output of the digital amplitude compensation step 115 is a compensated composite audio signal 12 at a sample rate of 316.4 KHz.

[0029] The compensated composite audio signal 12 is sent to the digital channel demodulation and filtering step 120. Step 120 also operates at the sample rate of 316.4 KHz and effectively breaks up the compensated composite audio signal into the individual signal components including the left plus right (L+R) channel mono signal 20, the 15.734 KHz pilot signal 25, the left minus right (L−R) stereo signal 30, and the SAP signal 40.

[0030] The SAP signal 40 is centered at five times the pilot signal 25 at a frequency of 78.67 KHz. In order to demodulate this part of the composite audio signal, step 120 first applies a band-pass FIR filter 121 to remove the L+R 20 and L−R 30 stereo channels and the professional channel if it is present in the composite signal. Step 20 then performs FM demodulation 122 by applying a Hilbert filter, a demodulation equation, and a low-pass filter to generate the FM demodulated SAP audio signal 123. The resultant demodulated SAP audio signal 123 is at a sample rate of 158.2 KHz which is the master clock signal divided by 1024. Further details about demodulating the SAP component 40 of the composite audio signal 10 may be found in the application entitled “System and Method for SAP FM Demodulation” filed under docket number 13586US01 on the same day as the application herein (docket number 13578US01) was filed.

[0031] The left minus right (L−R) stereo signal 30 is centered at twice the pilot signal frequency at 31.468 KHz and is a double sideband (DSB) suppressed carrier signal. According to FCC OET 6, the phase of the pilot signal 25 should be synchronized with the phase of the L−R DSB signal 30 to within three degrees in order to properly demodulate the signal. The phase of the L−R DSB signal 30 may be recovered by employing a digital phase-locked loop (DPLL) that is locked to the phase of the pilot signal 25. Referring to FIG. 2B, to perform the DPLL function, an eigth-order IIR band-pass filter 124 is applied to the digitized BTSC composite signal. The output of the band-pass filter 124 is then applied to a configuration 125 comprising a phase detector, a cosine look-up-table (LUT), and a loop filter as shown in FIG. 2B which also performs detection of the pilot signal 25 as part of the DPLL process. Finally DSB demodulation is performed using the same cosine look-up-table (LUT) and a tenth-order elliptical IIR low-pass filter 126 also shown in FIG. 2B. The low-pass filter 126 has a pass-band ripple of −0.1 dB at 13 KHz, 50 dB of attenuation at 15.734 KHz (the pilot signal frequency), and over 80 dB of attenuation above 19 KHz. The output is a demodulated version 127 of the left minus right (L−R) stereo signal 30 at a sample rate of 158.2 KHz as shown in FIG. 2 and FIG. 2B. Further details about demodulating the L−R DSB component 30 of the composite audio signal 10 may be found in the application entitled “System and Method of Performing Analog Multi-Channel Audio Signal Amplitude Correction” filed under docket number 13588US01 on the same day as the application herein (docket number 13578US01) was filed, and in the application “Pilot Tone Based Automatic Gain Control System and Method” filed under docket number 13589US01 on the same day as the application herein (docket number 13578US01) was filed.

[0032] Step 120 is also used to demodulate the left plus right (L+R) channel mono signal 20. The L+R signal 20 is first applied to the same tenth-order elliptical low-pass filter 126 having a pass-band ripple of −0.1 dB at 13 KHz, 50 dB of attenuation at 15.734 KHz (the pilot signal frequency), and over 80 dB of attenuation above 19 KHz.

[0033] In FM systems, the noise accompanying a received audio signal increases rapidly in the higher audio frequency range. To offset the effect, at the transmitter the audio signal is pre-emphasized to raise the level of the higher audio frequencies relative to the lower audio frequencies. As a result, the received audio signal needs to be de-emphasized, yielding an overall flat audio frequency response while greatly reducing the effects of noise introduced by the transmission process.

[0034] To accomplish the de-emphasis of the L+R signal 20, the output of the low-pass filter 126 in fed to a 75 micro-second de-emphasis digital filter 128. In an embodiment of the present invention, the transfer function of the de-emphasis digital filter 128 is 1$\begin{array}{cc}{H}_{75\mathrm{us}}\left(z\right)=\frac{0.04126}{1-0.47937z^{-1}}& \left[1\right]\end{array}$

[0035] The resultant L+R demodulated audio signal 129 is at a sample rate of 31.64 KHz which is the master clock frequency of 162 MHz divided down by a factor of 5120. As shown in FIG. 2, the demodulated L+R audio signal 129 may be fed to re-matrixing step 140 or to sample rate conversion step 150.

[0036] Both the left minus right (L−R) stereo channel 30 and the SAP channel 40 are originally DBX encoded on transmit to aid in noise reduction. DBX encoding is also known as signal companding. Signal companding is a technique used to reduce the effects of noise introduced by signal losses, circuit limitations, and interference during transmission of an audio signal. The audio signal to be transmitted is first dynamically compressed by a certain factor to reduce the overall dynamic range of the audio signal. Upon reception, the audio signal is expanded by a corresponding factor, thereby restoring the original dynamic range of the audio signal and reducing transmission noise.

[0037] Therefore, the left minus right (L−R) stereo channel 30 and the SAP channel 40 must be DBX decoded after demodulation and filtering step 120. DBX decoding is accomplished in step 130 as shown in FIG. 2. FIG. 3 is a schematic functional block diagram of a combination of digital filters 131 used to perform DBX decoding 130 in accordance with an embodiment of the present invention. A total of seven digital filters with transfer functions H1-H7 (132, 133, 134, 136, 137, 139, and 141) are used as shown in FIG. 3. The equations of the transfer functions H1-H7 are shown in FIG. 4 in both analog form 160 and digital form 165. In an embodiment of the present invention, the analog form 160 of the transfer functions H1-H7 have been translated to the digital form 165. The digital form 165 is implemented as shown in FIG. 3. The unique combination of digital filters performs adaptive audio signal companding based on the frequency and magnitude of the incoming demodulated audio signal (e.g. SAP or L−R). DBX decoding 130 is done at a sample rate of 158.2 KHz, which is the master clock frequency of 162 MHz divided down by a factor of 1024. The output of the DBX decoding step 130 is a decoded audio signal 142 (e.g. SAP or L−R) at a sample rate of 31.64 KHz.

[0038] A feature of the DBX decoding step 130 is the efficient implementation of the transfer function H2 139 shown in FIG. 3. Transfer function H2 performs variable de-emphasis as a function of frequency and magnitude of the demodulated audio signal. A root mean square detector 135 is implemented as part of the DBX decoding step using transfer functions H5 136 and H7 137 and square root operation 138 (FIG. 4 illustrates how the square root operation is performed). An output of the root mean square detector 135 is a coefficient “b” 144 which is input to transfer function H2 and is a function of audio signal frequency and magnitude.

[0039] For implementation and computation efficiency, the coefficient 147A of transfer function H2 is implemented as a look-up-table (LUT) 145 and a linear interpolator 146 as shown in FIG. 3B. The coefficient “b” 144 addresses the LUT 145 which then outputs the two nearest LUT data values corresponding to input “b”. The resolution of the LUT data values is designed to be coarse, thus minimizing the number of values that need to be stored in the LUT. The interpolator 146 then interpolates between the two output data values from the LUT 145 to generate an intermediate coefficient value 147A having a finer resolution and more accurately representing the output of the LUT for the input “b”. In an embodiment of the present invention, the intermediate coefficient value 147A is

1/(3b/103+1)   [2]

[0040] The intermediate coefficient value 147A is sent to IIR coefficients generator 146A. In one embodiment of the present invention, three IIR coefficients are generated based on the intermediate coefficient value 147A and are sent to IIR filter 146B. The three IIR coefficients are

a (1)=(b/103+101/103)/(3b/103+1)   [3]

b (0)=(b+3/103)/(3b/103+1)   [4]

b (1)=(101b/103+1/103)/(3b/103+1)   [5]

[0041] IIR filter 146B then generates output value 147 that is sent to transfer function H3 141. The configuration of FIG. 3B effectively implements the transfer function equation 165A for H2 shown in FIG. 4. As a result, the desired fine resolution of the output 147 of transfer function H2 139 may be achieved without implementing a more complicated design requiring more memory and/or more computation.

[0042] In step 140 of the decoding method 100, the DBX decoded L−R audio signal 142 and the demodulated L+R audio signal 129 may be re-matrixed to form a left audio signal 148 and a right audio signal 149 at a sample rate of 31.64 KHz. Re-matrixing 140 is accomplished as

left=(S+D)/2   [6]

[0043] and

right=(S−D)/2   [7]

[0044] where S=L+R and D=L−R. Therefore, re-matrixing 140 recovers the original stereo left 148 and right 149 audio signals.

[0045] In step 150, sampling rate conversion (SRC) is performed on the decoded SAP audio signal 142, the demodulated mono audio signal (L+R) 129, or the stereo left 148 and right 149 audio signals. Sampling rate conversion 150 is a process of translating the audio signal sampling rate of 31.64 KHz to a sampling rate including one of the standard audio output sampling rates of 32 KHz, 44.1 KHz, or 48 KHz in accordance with an embodiment of the present invention. An embodiment of the present invention accomplishes sampling rate conversion 150 by performing a combination of signal up-sampling, interpolation, and signal down-sampling.

[0046] A feature of one embodiment of the present invention with respect to sampling rate conversion 150 is that any of the resultant audio output signals (SAP out 151, mono out 152, left out 153, right out 154) may be output at any one of the three standard audio output sampling rates listed above by using the same set of low-pass filter coefficients in the SRC conversion process 150. Further details of an embodiment of sampling rate conversion may be found in the application entitled “System and Method of Performing Sample Rate Conversion” filed under docket number 13587US01 on the same day as the application herein (docket number 13578US01) was filed.

[0047] FIG. 5 is a schematic block diagram of a decoding system 200 implemented on an ASIC chip and used to implement the decoding method 100 of FIG. 2 in accordance with an embodiment of the present invention.

[0048] System 200 comprises various blocks implemented on an ASIC chip in accordance with an embodiment of the present invention. Block 210 is a sigma-delta analog-to-digital (A/D) conversion block operating on composite analog audio signal 10 and performing the function of step 110 in FIG. 2 to generate a low noise, high resolution composite digital audio signal 11. Block 230 is a clock generation block generating clock signals of 20.25 MHz, 316.4 KHz, and buffer clock signals related to the standard output sampling rates from a master clock signal of 162 MHz. The clock signals are used in the multi-channel audio signal decoding process of FIG. 2. Block 250 is a DSP processing block that performs many of the functions of the decoding process of FIG. 2. Block 220 is an input buffer block connected between the AID conversion block 210 and the DSP processing block 250 and is used to transfer composite digital audio signal data 11 into the DSP processing block 250. A configuration register block 240 interfaces to DSP processing block 250, input buffer block 220, and A/D conversion block 210 to provide configuration data to the system 200. Output buffer block 260 interfaces to DSP processing block 250 and clock generation block 230 to output standard audio output signals at standard audio output rates such as 32 KHz, 44.1 KHz, and 48 KHz in accordance with an embodiment of the present invention.

[0049] In accordance with an embodiment of the present invention, DSP processing block 250 includes two port data RAM memory 251 for temporary storage of data. DSP processing block 250 also includes coefficient ROM/RAM memory 252 for storing sets of coefficients used in the digital multi-channel audio signal decoding process of FIG. 2. Also included in DSP processing block 250 are instruction RAM memory 253 and instruction decoder 254. Instruction RAM memory 253 stores a set of instructions 300 to be executed by the DSP processing block 250 (see FIG. 7). Instruction decoder 254 interprets the set of instructions 300 in instruction RAM memory 253. In accordance with an embodiment of the present invention, the set of instructions 300 include those defined in FIG. 7 and are used to perform the functions of FIG. 2. Finally, DSP processing block 250 includes a five-stage pipelined data path 255 to execute the set of instructions 300 of FIG. 7.

[0050] FIG. 6 shows the five-stage pipelined data path 255 in accordance with an embodiment of the present invention. The 5-stages include memory address calculation stage 256, memory data fetch stage 257, multiplication stage 258, accumulation/mantissa-generation/signal-shifter stage 259, and registers/memory-write stage 261.

[0051] The five-stage pipelined data path 255 along with the set of instructions 300 are used to execute the decoding functions of FIG. 2 including digital amplitude compensation 115, digital channel demodulation and filtering 120, DBX decoding 130, re-matrixing 140, and sampling rate conversion 150.

[0052] A feature of a preferred embodiment of the present invention is that instruction 5 (301), 20-bit first-order IIR filtering, may be performed by the five-stage pipelined data path 255 in no more than three clock cycles. Another feature of a preferred embodiment of the present invention is that instruction 6 (302), 20-bit second-order IIR filtering, may be performed in no more than five clock cycles.

[0053] The various blocks illustrated in FIG. 5 may be combined or separated according to various embodiments of the present invention within the ASIC chip or may be separated and implemented over more than one chip.

[0054] In summary, certain embodiments of the present invention use several stages of digital signal processing where each subsequent stage of the digital multi-channel decoding process is performed at the lowest sampling rate that yields acceptable performance for that stage. As a result, certain embodiments of the present invention afford an approach to achieve efficient, low cost, low power, digital multi-channel audio signal decoding of BTSC audio signals in the digital domain.

[0055] While the invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims

1. A method of performing digital multi-channel audio signal decoding, said method comprising: performing analog-to-digital conversion of a composite analog audio signal at a fast clock rate to generate a composite digital audio signal at a first sample rate; performing digital frequency compensation of said composite digital audio signal at said first sample rate to generate a compensated composite audio signal; and performing digital channel demodulation and filtering of said compensated composite audio signal at said first sample rate to generate a first single channel audio signal at a second sample rate.

2. The method of claim 1 further comprising performing DBX decoding of said first single channel audio signal at said second sample rate to generate a decoded audio signal at a third sample rate.

3. The method of claim 2 wherein said fast clock rate is greater than said first sample rate, said second sample rate is less than said first sample rate, and said third sample rate is less than or equal to said second sample rate.

4. The method of claim 2 wherein said fast clock rate is an integer multiple of said first sample rate, said second sample rate, and said third sample rate.

5. The method of claim 2 further comprising performing digital channel demodulation and filtering of said compensated composite audio signal at said first sample rate to generate a second single channel audio signal at said third sample rate.

6. The method of claim 5 further comprising generating a left audio signal and a right audio signal based on said decoded audio signal and said second single channel audio signal at said third sample rate.

7. The method of claim 2 further comprising performing sampling rate conversion of said decoded audio signal to generate a second audio program (SAP) output signal at a standard audio output rate.

8. The method of claim 6 further comprising performing sampling rate conversion of said left audio signal and said right audio signal to generate a left stereo output signal and a right stereo output signal at a standard audio output rate.

9. The method of claim 5 further comprising performing sampling rate conversion of said second single channel audio signal to generate a mono audio output signal at a standard audio output rate.

10. The method of claim 1 wherein said first single channel audio signal at said second sampling rate comprises one of: a second audio program (SAP) signal; and a left minus right (L−R) stereo difference signal.

11. The method of claim 5 wherein said second single channel audio signal at said third sample rate comprises a left plus right (L+R) stereo sum signal.

12. The method of claim 1 wherein said performing digital frequency compensation comprises implementing a digital filter compensating for uneven frequency response in said composite digital audio signal due to an uneven frequency response of a previous IF demodulation function.

13. The method of claim 2 wherein said performing DBX decoding comprises implementing a combination of digital filters that are a translation of a set of analog filters.

14. The method of claim 2 wherein said performing DBX decoding includes performing variable de-emphasis of said first single channel audio signal by, in part, indexing into a look-up-table (LUT) and performing linear interpolation on data samples extracted from said LUT to generate an intermediate coefficient value.

15. A system for performing digital multi-channel audio signal decoding, said system comprising: a sigma-delta analog-to-digital (A/D) conversion block operating on a composite analog audio signal to generate a composite digital audio signal; a clock generation block generating clock signals used in said multi-channel audio signal decoding; and a DSP processing block including a multi-stage pipelined data path performing certain digital multi-channel audio signal processing functions in response to a set of instructions.

16. The system of claim 15 further comprising: an input buffer block connected between said sigma-delta A/D conversion block and said DSP processing block to transfer said composite digital audio signal to said DSP processing block; a configuration register block interfacing to at least said DSP processing block, said input buffer block, and said sigma-delta A/D conversion block; and an output buffer block interfacing to at least said DSP processing block and said clock generation block to output standard audio output signals at standard audio output rates.

17. The system of claim 15 wherein said DSP processing block further includes: data memory for temporary storage of data; coefficient memory for storing sets of coefficients used in said digital multi-channel audio signal decoding; instruction memory for storing said set of instructions; and an instruction decoder for interpreting said set of instructions.

18. The system of claim 15 wherein said multi-stage pipelined data path comprises: a memory address calculation stage; a memory data fetch stage; a multiplication stage; an accumulation/mantissa-generation/signal-shifter stage; and a registers/memory-write stage.

19. The system of claim 15 wherein said set of instructions, operating on said multi-stage pipelined data path, is capable of performing at least: digital frequency compensation of said composite digital audio signal to generate a compensated composite audio signal at a first sample rate; digital channel demodulation and filtering of said compensated composite audio signal to generate a first single channel audio signal at a second sample rate; digital channel demodulation and filtering of said compensated composite audio signal to generate a second single channel audio signal at a third sample rate; DBX decoding of said first single channel audio signal to generate a decoded audio signal at said third sample rate; re-matrixing of said decoded audio signal and said second single channel audio signal to generate left and right audio signals at said third sample rate; and sampling rate conversion of at least one of said decoded audio signal, said left and right audio signals, and said second single channel audio signal to generate at least one standard audio output signal at a standard audio output rate.

20. The system of claim 15 wherein said set of instructions includes: an instruction for performing first-order IIR filtering in no more than three clock cycles; and an instruction for performing second-order IIR filtering in no more than five clock cycles.

21. The system of claim 15 wherein said system is implemented as part of an ASIC chip.