Patent Application
20140082307
1. Technical Field The present invention relates to computer architecture and specifically to prioritizing access to memory.
2. Brief Summary
Various systems are provided which include a central processing unit (CPU), a peripheral device connected to a memory controller configured to control a main memory. Access to and from the main memory by the CPU and access to and from the main memory by the peripheral device is prioritized respectively according to a CPU priority level and a peripheral device priority level. An arbitration module is operatively attached to: the CPU, the peripheral device and to the memory controller. The arbitration module is configured to receive the peripheral device priority level. When the CPU priority level and the peripheral device priority level are both set at the highest available priority level, the arbitration module is configured to output to the memory controller a new CPU priority level less than the highest available priority level.
The arbitration module may be configured to receive the CPU priority level. When the CPU priority level and the peripheral device priority level are set at different priority levels, the arbitration module is configured to output to the memory controller the new CPU priority level equal to the CPU priority level as received.
The CPU priority level may be a predetermined constant value equal to the highest available priority level. The CPU priority level may be set by the CPU or a device external to the CPU. The peripheral device priority level may be set by the peripheral device or may be set by a device external to the peripheral device.
The peripheral device may be a video controller adapted to write streaming image data into the main memory. The video controller may include a write buffer for temporary storage of the image data prior to writing the image data into the main memory. The video controller sets and outputs to the arbitration module the highest available priority level when the write buffer is substantially full. The video controller sets and outputs to the arbitration module a priority level less than the highest available priority level when the write buffer is less than substantially full. Accordingly, the priority level for the peripheral device may be set at a value proportional to the fullness of the write buffer
The peripheral device may a video controller adapted to read streaming image data from the main memory. The video controller may include a read buffer for temporary storage of the image data prior to outputting the image data read from the main memory. The video controller sets and outputs to the arbitration module the highest available priority level when the write buffer is substantially empty. The video controller sets and outputs to the arbitration module a priority level less than the highest available priority level when the write buffer is not substantially empty. Accordingly, the priority level for the peripheral device may be set at a value proportional to the emptiness of the read buffer
Various methods are provided for arbitrating memory access between a central processing unit CPU and a peripheral device to main memory.
The memory access to and from the main memory by the CPU and memory access to and from the main memory by the peripheral device is prioritized respectively according to a CPU priority level and a peripheral device priority level . An arbitration module is provided externally to the CPU, to the peripheral device and to the memory controller. The arbitration module receives the peripheral device priority level from the peripheral device. When the CPU priority level and the peripheral device priority level are both set at the highest available priority level, the arbitration module outputs to the memory controller a new CPU priority level less than the highest available priority level. The CPU priority level may be set by either said CPU or a device external to said CPU. The peripheral device priority level may be set by the peripheral device.
The foregoing and/or other aspects will become apparent from the following detailed description when considered in conjunction with the accompanying drawing figures.
The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:
Reference will now be made in detail to features of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The features are described below to explain the present invention by referring to the figures.
Before explaining features of the invention in detail, it is to be understood that the invention is not limited in its application to the details of design and the arrangement of the components set forth in the following description or illustrated in the drawings. The invention is capable of other features or of being practiced or carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein is for the purpose of description and should not be regarded as limiting.
By way of introduction, aspects of the present invention are directed to arbitrating memory access between a central processing unit CPU and a peripheral device to and from a main memory. According to aspects of the present invention, an arbitration module may be configured to output to the main memory controller a new and/or modified CPU priority level which is less than the highest available priority level so that data from the peripheral device is not lost.
Reference is now made to
Writing to memory 102 by video controller 104 or CPU 106 is prioritized by DRAM controller 100 based on priority levels supplied respectively to DRAM controller 100.
Some examples of peripheral devices 104 and/or CPU 106 may set their own priority level. Otherwise, the priority levels may be set externally to peripheral device 104, CPU 106 and DRAM controller 100. Priority levels for a DRAM controller 100 may be 2 bits, giving four possible priority levels (0-3) from either video controller 104 or CPU 106. Normally, CPU 106 is given the highest priority for memory access because while waiting for data, CPU 106 completely stops. Normally, video controller 104 does not require the highest priority because image frames 15 are temporarily stored in data buffer FIFO. However, when video controller 104 and CPU 106 have the same level of highest priority (3), a loss of an image frame 15 may occur if CPU 106 is still accessing memory 102 when write buffer FIFO overflows. Loss of an image frame 15 may be unacceptable for instance in camera based driver assistance systems and other real time, e.g. video, digital processing systems.
CPU 106, peripheral device 104 and DRAM controller 100 may be “off-the-shelf” components. Under normal circumstances it may be that neither CPU 106 nor peripheral device 104 are available with priority level generation logic, because arbitration with priority may not be included in standard bus protocols. CPU 106 is not configured to receive a signal from peripheral device 104 and or otherwise change CPU priority status for memory access based on immediate requirement of peripheral device 104.
Thus, there is a need for and it would be advantageous to have a system and method for preventing data loss in the event that peripheral device, e.g. video controller 104 does not receive timely access to memory 102.
Reference is now made to
Arbitration module 200 is operatively attached to CPU 106 to receive priority control line 22 which is K bits wide. Priority control line 22 may alternatively receive a CPU priority level from another component (not shown) in system 20 other than CPU 106 or the CPU priority level on priority control line 22 may be set at a predetermined constant value without priority control line 22 as shown. Video controller 104 provides a priority control line 26 which is supplied to both DRAM controller 100 and arbitration module 200.
Video control unit 104 priority level may be set as a discrete variable priority level according to the remaining capacity of peripheral 104 FIFO buffer to store additional data. For video control unit 104 FIFO buffer being empty a priority level of 0 may be set. For video control unit 104 FIFO buffer somewhat full a priority level of 1 may be set, which may be equal to that of other co-processors or accelerators not shown in system 20. For a video control unit 104 FIFO buffer still fuller a priority level of 2 may be set which may be greater than that of the other co-processors but still below that of the priority level of CPU 106. When control unit 104 FIFO buffer is nearly full, a priority level may be set of 3 (for K=2 bits) equal to the CPU priority level. Accordingly, arbitration unit 200 may provide a modified or new priority level on priority control line 24 for CPU 106 which is based on the priority level of peripheral 104.
Reference is now also made to
Arbitration unit 200 provides a modified priority output for CPU 106 on priority control line 24 which is based on the received priorities for reading data provided on priority control lines 22 and 26.
Reference is now made to
Reference is now also made to
In step 505, arbitration module 200 receives priority levels from CPU 106 and peripheral device 104, 304 for instance on priority control lines 22 and 26 respectively.
In decision block 507, if the priority levels of both CPU 106 and peripheral device 104, 304 are both at a maximum (priority level 3 for K=2 bits), i.e. both have priority levels of 3, then the modified output on priority control line 24 is reduced to 2 in step 509, so that CPU 106 priority level is less than the priority level (3) of video control 104. If in decision 507, the priority levels of both CPU 106 and peripheral device 104, 304 are not at a maximum (priority level 3 for K=2 bits) then the modified output on priority control line 24 is the same value as the priority value on priority control line 22 in step 511. After either step 509 or step 511, step 505 continues, with arbitration module 200 receiving priority levels from CPU 106 and video control 104 on priority control lines 22 and 26 respectively.
Video control 104 may set its priority for memory access dependent on how full is FIFO data buffer. The more full the ‘write’ FIFO data register in video control 104, the higher is the priority set by video control 104 on priority control line 26. In the case of reading from main memory 102 (as shown in system 30), display controller 304 priority level may be set depending on how empty a ‘read’ FIFO data register is in display controller 304. The more empty the ‘read’ FIFO data register is in display controller 304, the higher is the priority set by display controller 304 on priority control line 26.
The indefinite articles “a”, “an” is used herein, such as “a processor”, has the meaning of “one or more” that is “one or more processors”.
Although selected features of the present invention have been shown and described, it is to be understood the present invention is not limited to the described features. Instead, it is to be appreciated that changes may be made to these features without departing from the principles and spirit of the invention, the scope of which is defined by the claims and the equivalents thereof.
