The present invention relates to class D devices, and more specifically, to class D modulators.
Devices, such as class AB drivers, modulators, converters, and amplifiers, can be used in audio devices such as speakers and headphone drivers. Most of these applications are battery driven, and thus power consumption is an important parameter. These devices also need to meet high performance in terms of signal-to-noise ratio (SNR) and total harmonic distortion (THD). Typically, these applications have different modes of operation, such that one mode can be performance optimized and another can be power consumption optimized.
Class D devices, such as drivers, modulators, converters, and amplifiers, can be used in audio devices such as speakers. In a conventional transistor amplifier, the output stage includes transistors that supply continuous output current. However, in conventional amplifiers, the output stage power dissipation is large. Class D amplifiers, dissipate much less power. Class D amplifiers use switches as amplifying devices. In particular, a class D amplifier output stage switches between the positive and negative power supplies so as to produce a train of voltage pulses. This reduces power dissipation because the output transistors have zero current when not switching, and have a low voltage when they are conducting current. Thus, class D devices have lower power dissipation, produce less heat, save circuit board space and cost, and (in portable systems) extend battery life.
Systems and method are provided for improving stability and performance in class-D modulators. In particular, a multi-cycle feedback network is positioned around a quantizer of a digital class-D amplifier. The multi-cycle feedback network allows the main class-D feedback loop to have multiple clock cycles of delay.
According to one aspect, an architecture for a class D modulator comprises an input line for receiving an input signal, a summer configured to subtract a feedback signal from the input signal and generate a summer output, a loop filter configured to receive the summer output and produce a filtered output, a quantizer configured to quantize the filtered output and output a quantized signal, a main feedback loop from the quantizer to the summer configured to filter the quantized signal to generate the feedback signal, and a quantizer feedback loop around the quantizer configured to add a delay to the quantized signal and feed a weighted delayed quantized signal back into the quantizer.
According to various implementations, the quantizer feedback loop includes an amplifier configured to apply a weight to the delayed quantized signal to generate the weighted delayed quantized signal. In some implementations, the quantizer feedback loop is a first quantizer feedback loop and further comprising a second quantizer feedback loop in parallel with the first quantizer feedback loop, wherein the second quantizer feedback loop is configured to add a second delay to the quantized signal. In some implementations, the weight is a first weight and wherein the second quantizer feedback loop includes a second amplifier configured to apply a second weight to the quantized signal. In some examples, the first weight is less than the second weight. In some examples, the weight has a value that is less than one, and wherein the weighted delayed quantized signal is smaller than the quantized signal
According to various implementations, the architecture includes a plurality of quantizer feedback loops around the quantizer. For examples, the architecture can include two, three, four, five, or more than five parallel quantizer feedback loops. In some implementations, the summer is a first summer and further comprising a second summer configured to add the filtered output and the weighted delayed quantized signal to generate a summed signal for input to the quantizer. In some implementations, the loop filter includes a plurality of integrators, wherein the filtered output includes a plurality of integrator outputs, and wherein each of the plurality of integrator outputs is summed at the second summer to generate the filtered output. In some implementations, the quantizer is one of a single-bit quantizer and a multi-bit quantizer. In various examples, the quantizer feedback loop includes one of a finite impulse response filter and an infinite impulse response filter.
The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not necessarily drawn to scale, and are used for illustration purposes only. Where a scale is shown, explicitly or implicitly, it provides only one illustrative example. In other embodiments, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
For a fuller understanding of the nature and advantages of the present invention, reference is made to the following detailed description of preferred embodiments and in connection with the accompanying drawings, in which:
In digital class D devices, the feedback analog-to-digital converter (ADC) is in a feedback loop for the modulator. The ADC is a low latency and complex ADC. A low latency ADC results in higher power consumption since the modulator runs at high speeds to achieve low latency. Systems and methods are provided for a modulator architecture in which the ADC runs at slower speeds, such that the modulator can be stabilized for more than 1 clock cycle delay. The power efficiency of the modulator is enhanced by running the ADC at a slower speed.
Systems and methods are provided for improving stability and performance in class-D modulators. In particular, a multi-cycle feedback network is positioned around a quantizer of a digital class-D amplifier. The multi-cycle feedback network allows the main class-D feedback loop to have multiple clock cycles of delay.
Generally, in a class-D amplifier with a digitally implemented loop filter, an ADC is used in the feedback path to convert the analog output back to digital for summation with the input. In some examples, the ADC has multiple clock cycles of latency in order to provide the noise performance dictated by the amplifier's specifications. However, the delays in the ADC add additional poles to the root locus, affecting closed-loop pole placement. This can negatively affect stability and result in large peaks in the noise transfer function (NTF). Systems and methods are provided to correct for the additional poles. In particular, for N cycles of delay in the ADC an Nth order filter can be placed in an additional digital feedback loop around the quantizer specifically. The additional digital feedback loop affects the additional poles such that the additional poles have a lesser impact on the placement of the other closed-loop poles. This results in an NTF that much more closely resembles that of the system without any delays in the feedback path. In some examples, for instance for larger N, the additional feedback loop causes an otherwise unstable loop to become stable.
Additionally, the loop filter includes two feedback loops. The first feedback loop feeds the output from the second part of the second integrator 210b back to the second summer 206. The first feedback loop includes a fifth amplifier 216a, which amplifies the signal, and the fifth amplifier 216a output is input to the second summer 206. At the second summer 206, the amplified feedback signal is added to the output from the first summer 204 and input to the first part of the first integrator 208a. The second feedback loop similarly feeds the output from the second part of the fourth integrator 210d back to the third summer 212. The second feedback loop includes a sixth amplifier 216b, which amplifies the signal, and the sixth amplifier 216b output is input to the third summer 212. At the third summer 212, the amplified feedback signal is added to the output from the second part of the second integrator 210b and input to the first part of the third integrator 208c.
The quantizer feedback loop 202 provides feedback around the quantizer 226. The feedback loop 202 around the quantizer 226 includes a filter. The quantizer feedback loop 202 takes the quantizer 226 output, filters it, at feeds it back to the quantizer 226 input. In some examples, the filter is a finite impulse response filter and, in some examples, the filter is an infinite impulse response filter. The feedforward paths 222a-222d can be either gain blocks or filters, which become IIR filters. In some examples, the input to the filter 230a is the quantizer 226 output. In some examples, the input to the filter 230a is the quantizer 226 input. In some examples, the input to the filter 230a is the summer 224 output.
The quantizer feedback loop 202 takes the quantizer 226 output and multiplies it by the gain factor k1 at a first feedback amplifier 232a and feeds it back to the fourth summer 224, where it is fed directly back to the quantizer 226. The quantizer feedback 202 loop has a gain of ‘k1’, and is faster than the outer main feedback loop that includes the delay block 240. In one example, the quantizer feedback loop 202 has a one clock cycle delay at the first feedback delay block 230a; z−1 can have up to a one clock cycle delay. Adding the delay at the first feedback delay block 230a in the quantizer feedback loop 202 corrects for the ADC delay. In particular, z−1 allows for a delay of one sample in the ADC. In some examples, the gain factor k1 at the first feedback amplifier 232a is less than one. In various examples, the gain factor 1k is 0.5, 0.4, 0.03, 0.25, 0.2, 0.15, 0.125, 0.1, 0.075, 0.0625, or 0.05. The feedback loop 202 allows for error correction in the quantizer 226.
In some implementations, the digital-only/quantizer output is used directly for the quantizer feedback loop 202, and the quantizer feedback loop 202 does not use the power stage output. In contrast, the main outer feedback loop with the outer delay block 240 uses the power stage output. Thus, the two feedback loops are different. In some examples, the feedback delay itself causes extra pulses, thereby minimizing increased pulse density.
The feedback loop 252 around the quantizer 226 includes a second feedback delay block 230b and a second feedback amplifier 232b, and the quantizer feedback loop 252 takes the quantizer 226 output, filters it, at feeds it back to the quantizer 226 input. In particular, the second quantizer feedback loop 252 takes the quantizer 226 output and multiplies it by the gain factor k2 and feeds it back to the fourth summer 224, where it is fed directly back to the quantizer 226. The second feedback amplifier has a gain of ‘k2’. In one example, there is a two clock cycle delay; that is, the second feedback delay block 230b has a z−2 delay, which can be a two clock cycle delay. Adding the second delay in the second quantizer feedback loop 252 allows for additional ADC latency. In particular, z−2 allows for a delay of two samples in the ADC. In some examples, the gain factor k2 is less than one. In various examples, the gain factor k2 is 0.5, 0.4, 0.03, 0.25, 0.2, 0.15, 0.125, 0.1, 0.075, 0.0625, or 0.05. In some examples, k1 and k2 have different values. In one example, k1 is 0.125 and k2 is 0.25. The second quantizer feedback loop 252 allows for additional error correction in the quantizer 226.
In another example, more filtering can be added at k and the outer feedback loop can have be z−3, z−4, . . . z−n. In various examples, this slows the feedback loop down more than one clock cycle. In some examples, the quantizer feedback loop filter is one of a finite impulse response (FIR) filter and an infinite impulse response (IIR) filter.
The third quantizer feedback loop 262 around the quantizer 226 includes a third feedback delay block 230c and a third feedback amplifier 232c, and the third quantizer feedback loop 262 takes the quantizer 226 output, filters it, at feeds it back to the quantizer 226 input. As illustrated in
Sigma delta modulator performance is represented by the signal transfer function (STF) and the noise transfer function (NTF). The STF is a measure of the output signal relative to the input signal. The NTF is a function of the output error relative to the input error and indicates the error introduced by the quantizer. From a frequency domain perspective, the root locus can be analyzed to graphically examine how the modulator input and output change with variations in quantizer feedback.
As shown in
In various implementations, more than one clock cycle delay is added to the feedback path ADC. In particular, as discussed above with respect to
where H(z) is the loop filter transfer function, and K(z) is the feedback to the quantizer directly. The loop filter transfer function H(z) is the transfer function for the integrators, the summer, and the resonators.
In various examples, the delays are managed between the two branches. The block diagram in
In some implementations, three delays can be added to the feedback path. However, without K(z) correction, three delays in the feedback path produces an unstable loop without K(z) correction. Adding K(z) correction as described herein makes the loop stable. In one example, shown in
In some implementations, the stability and/or headroom of the circuit can lose a few dB at very high output levels. According to various examples, integrators reach wraparound much faster when there is feedback delay. Thus, calculating integrator saturation while including the delay limits the output level. However, integrator saturation points based on the loop without feedback delay show that the integrators are saturated at lower values for the same input level. The integrators can be re-optimized after adding the feedback loop with the filter around the quantizer. According to various examples, the circuit can have better in-band performance even when the delay is added back in.
Additionally, in various embodiments, the electrical device 900 may not include one or more of the components illustrated in
The electrical device 900 may include a processing device 902 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 902 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 900 may include a memory 904, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 904 may include memory that shares a die with the processing device 902. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some embodiments, the electrical device 900 may include a communication chip 912 (e.g., one or more communication chips). For example, the communication chip 912 may be configured for managing wireless communications for the transfer of data to and from the electrical device 900. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 912 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 912 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 912 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 912 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 912 may operate in accordance with other wireless protocols in other embodiments. The electrical device 900 may include an antenna 922 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 912 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 912 may include multiple communication chips. For instance, a first communication chip 912 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 912 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 912 may be dedicated to wireless communications, and a second communication chip 912 may be dedicated to wired communications.
The electrical device 900 may include battery/power circuitry 914. The battery/power circuitry 914 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 900 to an energy source separate from the electrical device 900 (e.g., AC line power).
The electrical device 900 may include a display device 906 (or corresponding interface circuitry, as discussed above). The display device 906 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 900 may include an audio output device 908 (or corresponding interface circuitry, as discussed above). The audio output device 908 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The electrical device 900 may include an audio input device 924 (or corresponding interface circuitry, as discussed above). The audio input device 924 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The electrical device 900 may include a GPS device 910 (or corresponding interface circuitry, as discussed above). The GPS device 910 may be in communication with a satellite-based system and may receive a location of the electrical device 900, as known in the art.
The electrical device 900 may include another output device 910 (or corresponding interface circuitry, as discussed above). Examples of the other output device 910 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 900 may include another input device 920 (or corresponding interface circuitry, as discussed above). Examples of the other input device 920 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The electrical device 900 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server device or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, the electrical device 900 may be any other electronic device that processes data.
Example 1 provides an architecture for a class D modulator, comprising: an input line for receiving an input signal; a summer configured to subtract a feedback signal from the input signal and generate a summer output; a loop filter configured to receive the summer output and produce a filtered output; a quantizer configured to quantize the filtered output and output a quantized signal; a main feedback loop from the quantizer to the summer configured to filter the quantized signal to generate the feedback signal; and a quantizer feedback loop around the quantizer including a first filter, configured to generate a filtered quantized signal, wherein the filtered quantized signal is added back into the quantizer.
Example 2 provides an architecture according to one or more of the preceding and/or following examples, wherein the quantizer feedback loop includes an amplifier configured to apply a weight to the quantized signal to generate the filtered quantized signal.
Example 3 provides an architecture according to one or more of the preceding and/or following examples, wherein the quantizer feedback loop is a first quantizer feedback loop and the filtered quantized signal is a first filtered quantized signal, and further comprising a second quantizer feedback loop in parallel with the first quantizer feedback loop, wherein the second quantizer feedback loop is configured to generate a second filtered quantized signal, and wherein the second filtered quantized signal is added back to the quantizer.
Example 4 provides an architecture according to one or more of the preceding and/or following examples, wherein the weight is a first weight and wherein the second quantizer feedback loop includes a second amplifier configured to apply a second weight to the quantized signal to generate the second filtered quantized signal.
Example 5 provides an architecture according to one or more of the preceding and/or following examples, wherein the first weight is less than the second weight.
Example 6 provides an architecture according to one or more of the preceding and/or following examples, wherein the weight has a value that is less than one, and wherein the filtered quantized signal is smaller than the quantized signal.
Example 7 provides an architecture according to one or more of the preceding and/or following examples, further comprising a plurality of quantizer feedback loops around the quantizer.
Example 8 provides an architecture according to one or more of the preceding and/or following examples, wherein the summer is a first summer and further comprising a second summer configured to add the filtered output and the filtered quantized signal to generate a summed signal for input to the quantizer.
Example 9 provides an architecture according to one or more of the preceding and/or following examples, wherein the loop filter includes a plurality of integrators, wherein the filtered output includes a plurality of integrator outputs, and wherein each of the plurality of integrator outputs is summed at the second summer to generate the filtered output.
Example 10 provides an architecture according to one or more of the preceding and/or following examples, further comprising a plurality of feedforward paths, each feedforward path from a respective integrator output of the plurality of integrator outputs to the second summer, wherein each of the plurality of feedforward paths includes at least one of a filter and a gain.
Example 11 provides an architecture according to one or more of the preceding and/or following examples, wherein the summed signal is input to the first filter.
Example 12 provides an architecture according to one or more of the preceding and/or following examples, wherein the quantizer is one of a single-bit quantizer and a multi-bit quantizer.
Example 13 provides an architecture according to one or more of the preceding and/or following examples, wherein the quantizer feedback loop includes one of a finite impulse response filter and an infinite impulse response filter.
Example 14 provides an architecture according to one or more of the preceding and/or following examples, wherein the loop filter if further configured to receive the filtered quantized signal generated by the first filter.
Example 15 provides an architecture according to one or more of the preceding and/or following examples, wherein the main feedback loop has an N clock cycle delay, wherein N is an integer.
Example 16 provides a method for a class D modulator, comprising: receiving an input signal; subtracting a feedback signal from the input signal at a summer to generate a summer output; filtering the summer output at a loop filter to generate a filtered output; quantizing the filtered output at a quantizer and outputting a quantized signal; in a main feedback loop: filtering the quantized signal to generate the feedback signal; and feeding back the feedback signal to the summer; wherein filtering the quantized signal and feeding back the feedback signal includes adding a main feedback loop delay, and wherein the main feedback loop delay is one or more clock cycles; and in a quantizer feedback loop: filtering the quantized signal to generate a filtered quantized signal; and feeding back the filtered quantized signal to the quantizer.
Example 17 provides a method according to one or more of the preceding and/or following examples, wherein, in the quantizer feedback loop, filtering the quantized signal includes applying a weight to the quantized signal to generate the filtered quantized signal.
Example 18 provides a method according to one or more of the preceding and/or following examples, wherein, in a second quantizer feedback loop, filtering the quantized signal to generate a second filtered quantized signal, and feeding back the second filtered quantized signal to the quantizer.
Example 19 provides an architecture for a class D modulator, comprising: an input line for receiving an input signal; a summer configured to subtract a feedback signal from the input signal and generate a summer output; a loop filter configured to receive the summer output and produce a filtered output; a quantizer configured to quantize the filtered output and output a quantized signal; and a main feedback loop from the quantizer to the summer configured to filter the quantized signal to generate the feedback signal, wherein the main feedback loop has a delay of one or more clock cycles.
Example 20 provides an architecture according to one or more of the preceding and/or following examples, further comprising a quantizer feedback loop around the quantizer including a first filter, configured to generate a filtered quantized signal, wherein the filtered quantized signal is added back to an input to the quantizer.
Example 21 provides a system including a digital class D modulator including a feedback loop having at least one clock cycle delay.
Example 22 provides a system including a digital class D modulator including a feedback loop around a quantizer.
Example 23 is a system according to one or more of the preceding examples wherein the feedback loop includes a filter.
Example 24 is a system according to one or more of the preceding examples wherein the feedback loop includes a second order filter.
Example 25 is a system according to one or more of the preceding examples wherein the feedback loop includes a third order filter.
Example 26 is a system according to one or more of the preceding examples wherein the feedback loop includes at least two clock cycles delay.
Example 27 is a system according to one or more of the preceding examples, wherein the modulator is one of a 2 level modulator, a 3 level modulator, a 4 level modulator, a 5 level modulator, a 6 level modulator, a 7 level modulator, and an 8 level modulator.
Example 28 is a system according to one or more of the preceding examples, wherein the filter is one of an FIR filter and an IIR filter.
Example 29 provides a system according to one or more of the preceding examples wherein the quantizer is a multibit quantizer.
Example 30 provides a system according to one or more of the preceding examples wherein the quantizer is a single bit quantizer.
Example 31 includes an apparatus that includes a converter as discussed or depicted in any of examples 1-10, some other example, or as otherwise discussed or depicted herein.
Example 32 includes an apparatus comprising means to implement a converter as discussed or depicted in any of examples 1-10, some other example, or as otherwise discussed or depicted herein.
Example 33 includes a method for implementing or manufacturing a converter as discussed or depicted in any of examples 1-10, some other example, or as otherwise discussed or depicted herein.
Example 34 includes one or more non-transitory computer-readable media comprising instructions that, upon execution of the instructions by an electronic device, are to cause the electronic device to implement or manufacture a converter as discussed or depicted in any of examples 1-10, some other example, or as otherwise discussed or depicted herein.
In the preceding discussion, reference may be made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the preceding detailed description is not to be taken in a limiting sense.
For the purposes of the present disclosure, the phrase “A or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
The description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
The term “coupled with,” along with its derivatives, may be used herein. “Coupled” may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term “directly coupled” may mean that two or elements are in direct contact.
Various operations may be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent.
As used herein, the term “module” may refer to, be part of, or include an application specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, or other suitable components that provide the described functionality.
Various embodiments may include any suitable combination of the above-described embodiments including alternative (or) embodiments of embodiments that are described in conjunctive form (and) above (e.g., the “and” may be “and/or”). Furthermore, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described embodiments. Moreover, some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above-described embodiments.
The above description of illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or limiting as to the precise forms disclosed. While specific implementations of, and examples for, various embodiments or concepts are described herein for illustrative purposes, various equivalent modifications may be possible, as those skilled in the relevant art will recognize. These modifications may be made in light of the above detailed description, the Abstract, the Figures, or the claims.
This application is related to and claims the benefit of priority under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application No. 63/063,560 entitled “SYSTEM AND METHOD TO COMPENSATE FOR FEEDBACK DELAYS IN DIGITAL CLASS-D MODULATORS” filed on Aug. 10, 2020, which is hereby incorporated by reference in its entirety.
Number | Date | Country | |
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63063560 | Aug 2020 | US |