System and method to reduce audio artifacts from an audio signal dispersed among multiple audio channels by reducing the order of each control loop by selectively activating multiple integrators located within each control loop

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustration of a filter system;

FIG. 2 is an illustration of output signals characteristic of the circuit of FIG. 1;

FIG. 3 is an illustration of a timing diagram of an output signal of the system of FIG. 1 before and after output is disconnected;

FIG. 4 is an illustration of output dither;

FIG. 5 is an up/down circuit;

FIG. 6 is an illustration of factor/average circuits according to the invention; and

FIG. 7 is a flow diagram of a method according to the invention.

DETAILED DESCRIPTION

The invention is directed to a system and method that solves the audio artifact problem discussed above. The system implements a method of tracking the average value of the signal presented to the Class driver stage (the “bridge” or “bridge chip”) of the audio system and indicates to the shut down means the correct time at which to switch to the disconnected stage such that no click or pop is created. An example of a typical system to which the invention applies is shown in FIG. 1.

The invention provides a system for use in an audio signal processor to remove sound artifacts from an audio signal during shutdown of the output, which includes an input for receiving an audio input signal, a noise shaping modulator to reduce the input bit width having an order of two or more, a circuit by which the reduced bit representation is converted to a single bit time domain output as may be done by a PWM element, multiple channels where two or more share a common output enable signal, a circuit by which the time of zero average value of a given channel output may be found, a circuit by which the output of the channel may be replaced with a fixed signal representative of a silent audio signal, a circuit by which the time of the occurrence of the zero average output value may be compared to the predictable time of the zero average value output of the fixed signal, a circuit by which channels are in succession compared to prior channels and switched to share the fixed output signal, and a circuit by which upon finding the last channel is at the zero average value in synchrony with the prior channel or channels the output of the entire group of channels may be simultaneously disconnected.

The system according to one embodiment of the invention is directed to a system for use in an audio signal processor to remove sound artifacts from an audio signal during shutdown of the output that has an input for receiving an audio input signal, a noise shaping modulator to reduce the input bit width having an order of two or more, a circuit by which the reduced bit representation is converted to a single bit time domain output as may be done by a PWM element, a circuit by which a filtered or average value of the output single bit time domain stream may be performed, a circuit, within or separate from the above filter, whereby the significance of the PWM samples as assessed by the filter varies with time such as may be described by the filter having a variable impulse response, a circuit by which the average value may be found to be zero or sufficiently close to zero as determined by the resolution of the filter output, a circuit by which the filter average value being zero or close to zero is used to disconnect (or equivalently change impedance or power) of the device or devices rendering the PWM signal into the analog domain as may be implemented by a Class D bridge chip and disconnection circuitry.

The example shown is a third order sigma delta loop driving a pulse wave modulator (PWM) element. The intention is to convert an input signal expressed over many bits (typically 24) into a single bit stream of data output from the PWM element to be connected to a Class D power driver. The invention is directed to determining the best moment in which to disconnect the power driver from the output stream such that no click or pop is heard in the loudspeakers. The reason that a click or pop is heard is due to the average value of the signal not being zero at the time of disconnection. The invention is directed to assessing the average value of the signal for the purpose of indicating the ideal time for a shutdown of the output signal. I practice, this is non-trivial because the output signal is bounded and the average of the output signal oscillates. The actual phase of the oscillation of the average value depends upon the time at which the averaging process was started.

Therefore, a clear indication of the ideal time for shutdown cannot depend upon a simply derived average value. FIG. 2 illustrates this problem, where the two different triangular waves, A1 and A2, are shown off phase. A1 is the accumulation (the integral) of the signal—the integration process for A1 is started at S1. A2 is another accumulation, but this time the integration process is started at S2. Each of these signals passes though zero, indicating the time when the average value is zero. But clearly each signal does not indicate the same time—they cannot both be correct. Empirical data shows that the ideal time for disconnection when a continuous 50:50 duty cycle is output is a point half way through either the high or low period—as shown in FIG. 3.

This is empirically found to be the ideal time—it corresponds to the average shown in A2 of FIG. 4. FIG. 3 shows a waveform that has a 50:50 duty cycle. However, only in the case of a first order modulator would the signal be exactly fixed. In a higher order modulator the exact transition times of the output are not fixed at the 50:50 points. There is dither in the output that causes the edges to move slightly as shown here in FIG. 4.

The invention is directed to a method of determining the time when the average value of the high order modulated signal (and hence not exactly repeating 50:50) is zero independently of the choice of starting time. If the output pulses of the PWM from the high order modulator are applied to an up/down counter such that the counter counts up when the signal is high and counts down when the signal is low, a digital representation of the average value can be created. FIG. 5 illustrates an example.

FIG. 5
a is the up/down (U/D) counter, where, if the wire labeled U/D is high, the next clock edge will cause the average number to increase. In contrast, if it is low, it will decrease. The average value on the output bus of the U/D counter is seen to represent the average value of the PWM output as sampled by the clock. This demonstrates that an up down counter is sufficient to asses the average value of the output, but this up/down counter method would suffer from the problem of its dependency on the start point to indicate the correct result (i.e. it suffers from the problem shown in FIG. 2. that the start point influences the result).

FIGS. 6
a and 6b illustrate an up/down counter that is modified to accept an amount by which it is incremented or decremented, where the up/down counter changes by ±1, this configuration changes by ± a variable amount.

As illustrated in another embodiment, FIG. 6b, the circuit 600 includes a PWM 602 that multiplies a FACTOR by ±1 by multiplier 604 and that factor is then used to adjust the average value with adder 606 that outputs an average to D input of flip flop 608, that outputs Q output to adder 606. The sum output of the adder is the AVERAGE. FIG. 6a shows the multiplier as an explicit element. Multiplication is commonly a complex operation that uses significant resources. However, in the case where one of the multiplicands is a single bit, a set of simple exclusive-or gates can create the one's complement that can be adjusted to be the ideal 2's complement by use of the otherwise unused carry input of the adder in the accumulator. FIG. 6b illustrates this useful feature of the circuit, where the FACTOR is input to an exclusive OR gate along with the PWM output. The output is added in adder 610 with the output of flip flop 612, where the PWM input clocks the input CIN of the adder. The output Q of the flip flop 612 is added with the output of the flip flop 612.

On aspect of the invention the ramp indicated in the drawing. At the start of the integration process the factor value is zero. Over time it slowly increases to a significant value, 100 for example. Thus, as the stream of PWM data emerge from the loop they are averaged in this block, but the weight attached to the averaging process is not fixed—for the early samples the weight is low, the weight increased with time to a final value significantly more than its initial value. This procedure then delivers a zero crossing in the average value that does indeed correspond to the time when the average is zero and the output may be disconnected.

FIG. 7 illustrates a flow chart format of one implementation of the invention as follows. When it is desired to shut down a high order modulator's PWM output as used in high performance Class D circuits. Simply, the process is as follows:

1) In Step 702, Initialize the variables “Factor” and “Average” and “timer” to 0—next go to 704.
2) In step 704, Wait for a positive edge of the master clock—go to 706
3) In 706, query whether the PWM output high? If yes go to 710, else go to 708.
4) In 710, Increment the “Average” value by “Factor”—go to 712
5) In 708, Decrement the “Average” value by “Factor”—go to 712
6) In 712, query whether factor equal to 1000?—If yes go to 716 else go to 714
7) In 714 Increment “Factor” by 1—go to 718
8) In 716 Increment “timer” by 1—go to 718
9) In 718, query whether timer equal to 10000? If yes go to 720, else go to 704
10) In 720, query whether the absolute value of “Average” less than or equal to “Factor”?—if yes go to 722 else goto 704
11) In 722, Stop—this is now the time to shutdown the output.

The flow chart of FIG. 7 gradually increments the factor value so adding more and more weight to the averaging process until the factor reaches 1000 at which point all PWM cycle contribute equally to the output. Then a time (10,000 clock cycles in this case) is waited after which the next zero crossing of the average value is used to indicate the output can now be disconnected. Note the zero crossing is assessed to within the “factor” value as is needed since at the end “average” is incrementing and decrementing by “factor”.

The invention is directed to a system and method that solves the audio artifact problem discussed above in a multi-channel system. Each of the channels in the multi-channel audio system is derived from a high order modulator. A high order modulator (with order greater than one) has an output that does not settle down to a precise 50:50 duty cycle for no input data—the output always “jitter”s due to nature of the high order noise shaping loop. An example of a typical channel in the system to which this invention applies is shown in FIG. 1 discussed above. The example shown is a third order ΣΔ loop driving a PWM element. The intention is directed to converts an input signal expressed over many bits (typically 24) into a single bit stream of data output from the PWM element to be connected to a Class D power driver. The challenge is to find the single best moment to disconnect the power driver from the output stream on a collection of such channels so that no click or pop is heard in the loudspeakers of any challenge. The reason that a click or pop is heard is due to the average value of the signal not being zero at the time of disconnection.

In flow chart format, one implementation of the invention is as follows. When it is desired to shut down a high order modulator's PWM output as used in high performance Class D circuits.:

Flowchart #1:

1) Initialize the variables “Factor” and “Average” and “timer” to 0—goto 2

2) Wait for a positive edge of the master clock—goto 3

3) Is the PWM output high? If yes goto 4, else goto 5

4) Increment the “Average” value by “Factor”—goto 6

5) Decrement the “Average” value by “Factor”—goto 6

6) Is factor equal to 1000?—If yes goto 8 else goto 7

7) Increment “Factor” by 1—goto 9

8) Increment “timer” by 1—goto 9

9) Is timer equal to 10000? If yes goto 10 else goto 2

10) Is the absolute value of “Average” less than or equal to “Factor”?—if yes goto 11 else goto 2

11) Stop—this is now the time to shutdown the output.

The above description allows the point of average zero out to be found. In the above embodiments, it has been suggested that at this point the output may be disconnected, however this would not be possible if more than one channel is connected to single shutdown pin on the driver chip. Consequently, the embodiment of Figure the key aspect of this disclosure is to now not switch off (disconnect) the driver but instead to, at this point on this channel, switch to a 50:50 duty cycle. There will be no “click” at this point since the average was zero and the signal we are now applying (the 50:50 signal) also has a zero average value. So the first channel has now switched to a 50:50 duty cycle with no click, but the output is still enabled to the loudspeaker—we have not attempted to disconnect it. However, because the channel has switched to a 50:50 duty cycle it is no longer necessary to apply a complex procedure to find the point of zero average output value—such a point occurs two times in a cycle—at the point halfway along the low period and again at the point halfway along the high period. Attention now turns to the second channel—a means is applied to find the point zero average output value, but we ignore all results until that point of zero average output value falls at a time when we know the first channel has a zero average output value. At this point, the system switches to the second channel to the 50:50 duty cycle as well. Attention now turns to the third and any successive channel that share the same shutdown signal. When at the last such channel, the shutdown process is activated. This must occur at the point where all channels are now at the ‘click-less” point and we have achieved our goal. The following flow chart in one implementation of the invention is as follos. A 50:50 duty cycle are the rate of the PWM output is used.

1) Initialize a “current channel” to the first channel in the group with a common shutdown signal—goto 2
2) Use Flowchart #1 referring to the current channel to find the zero-average value point—goto 3
3) Does the zero point found occur at the zero point of the first channel? If yes goto 4 else goto 2
4) Is the current channel the last in the group? If yes goto 7 else goto 5
5) Connect the 50:50 duty cycle to the current channel—goto 6
6) Increment the current channel pointer to point to the next channel in the group—goto 2
7) Active the shutdown signal for the whole group.—goto 8
8) Stop—operation is now complete

The invention has been described in the context of a system and method of removing artifacts from an audio signal during shutdown of the output. However, the embodiments described herein are not intended as limiting of the spirit and scope of the invention, which is defined by the appended claims.

Claims

1. A system for use in an audio signal processor to remove sound artifacts from an audio signal during shutdown of the output, comprising: an input for receiving an audio input signal;a noise shaping modulator to reduce the input bit width having an order of two or more;a means by which the reduced bit representation is converted to a single bit time domain output as may be done by a PWM element;multiple channels where two or more share a common output enable signala means by which the time of zero average value of a given channel output may be found;a means by which the output of the channel may be replaced with a fixed signal representative of a silent audio signal;a means by which the time of the occurrence of the zero average output value may be compared to the predictable time of the zero average value output of the fixed signala means by which channels are in succession compared to prior channels and switched to share the fixed output signal; anda means by which upon finding the last channel is at the zero average value in synchrony with the prior channel or channels the output of the entire group of channels may be simultaneously disconnected.

System and method to reduce audio artifacts from an audio signal dispersed among multiple audio channels by reducing the order of each control loop by selectively activating multiple integrators located within each control loop

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