Claims
- 1. An internal bus testing method that provides testing control and visibility of an internal PCI bus state utilizing an on board internal PCI bus tester, comprising the steps of;a communicating information related to test vectors between external devices and internal testing agent; b transmitting said information related to said test vectors to said internal PCI bus; c executing said test vectors over said internal PCI bus via an internal testing agent coupled to said internal PCI bus; and d capturing information related to said test vectors on said internal PCI bus via said internal testing agent coupled to said internal bus.
- 2. The method of claim 1 wherein step a further comprises the steps of:loading raw test vectors in a direct access testing agent; and moving refined test vectors into a high level testing agent such as an initiator testing agent or a target testing agent.
- 3. The method of claim 1 wherein step a further comprises the steps of:transferring information related to the test vectors to an internal PCI bus from an initiator testing agent; and conveying information related to a test vector to an internal PCI bus from a target testing agent.
- 4. The method of claim 1 wherein step a further comprises the steps of:engaging in a PCI bus transaction with an internal target by an initiator testing agent; and responding to a PCI bus transaction of an internal target agent attempting to access a target testing agent.
- 5. The method of claim 1 wherein step a further comprises the steps of:placing the information related to test vectors in a direct access testing agent; and depositing information related to test vectors in an input/output shift register.
- 6. The method of claim 1 wherein said internal testing agent comprises a PCI serial scan direct access agent adapted to process raw test vectors comprised of binary ones and zeroes that fully define the state of said internal bus.
- 7. The method of claim 1 wherein said internal testing agent comprises a PCI serial scan initiator agent adapted to generate PCI transactions and obtain control of internal PCI bus.
- 8. The method of claim 1 wherein said internal testing agent comprises a PCI serial scan target agent adapted to respond to access attempts from a PCI initiator coupled to said PCI bus.
Parent Case Info
This is a continuation of application Ser. No. 09/177,789 filed on Oct. 22, 1998 U.S. Pat. No. 6,324,663 which is hereby incorporated by reference to this specification.
US Referenced Citations (10)
Continuations (1)
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Number |
Date |
Country |
Parent |
09/177789 |
Oct 1998 |
US |
Child |
09/944876 |
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US |