Patent Application
20180336111
Embodiments relate to power management of a system, and more particularly to power management of a multicore processor.
Advances in semiconductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and/or complete systems on individual integrated circuits. Additionally, as the density of integrated circuits has grown, the power requirements for computing systems (from embedded systems to servers) have also escalated. Furthermore, software inefficiencies, and its requirements of hardware, have also caused an increase in computing device energy consumption. In fact, some studies indicate that computing devices consume a sizeable percentage of the entire electricity supply for a country, such as the United States of America. As a result, there is a vital need for energy efficiency and conservation associated with integrated circuits. These needs will increase as servers, desktop computers, notebooks, Ultrabooks™, tablets, mobile phones, processors, embedded systems, etc. become even more prevalent (from inclusion in the typical computer, automobiles, and televisions to biotechnology.
In various embodiments, techniques are provided to analyze in real-time during normal processor operation in the field (as implemented in a given computing platform), degradation of a processor or other system on chip (SoC) over time, by periodically running diagnostic testing to monitor aging progress, without compromising mission critical quality of service (QoS) and, in case of detection of degradation and/or failure, to alert as to an upcoming failure ahead of time (or an existing failure).
Although the following embodiments are described with reference to energy conservation and energy efficiency in specific integrated circuits, such as in computing platforms or processors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described. herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to any particular type of computer systems. That is, disclosed embodiments can be used in many different system types, ranging from server computers (e.g., tower, rack, blade, micro-server and so forth), communications systems, storage systems, desktop computers of any configuration, laptop, notebook, and tablet computers (including 2:1 tablets, phablets and so forth), and may be also used in other devices, such as handheld devices, systems on chip (SoCs), and embedded applications. Some examples of handheld devices include cellular phones such as smartphones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications may typically include a microcontroller, a digital signal processor (DSP), network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, wearable devices, or any other system that can perform the functions and operations taught below. More so, embodiments may be implemented in mobile terminals having standard voice functionality such as mobile phones, smartphones and phablets, and/or in non-mobile terminals without a standard wireless voice function communication capability, such as many wearables, tablets, notebooks, desktops, micro-servers, servers and so forth. Moreover, the apparatuses, methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for energy conservation and efficiency. As will become readily apparent in the description below, the embodiments of methods, apparatuses, and systems described herein (whether in reference to hardware, firmware, software, or a combination thereof) are vital to a ‘green technology’ future, such as for power conservation and energy efficiency in products that encompass a large portion of the US economy.
Referring now to
As seen, processor 110 may be a single die processor including multiple cores 120a-120n. In addition, each core may be associated with an integrated voltage regulator (IVR) 125a-125n which receives the primary regulated voltage and generates an operating voltage to be provided to one or more agents of the processor associated with the IVR. Accordingly, an IVR implementation may be provided to allow for fine-grained control of voltage and thus power and performance of each individual core. As such, each core can operate at an independent voltage and frequency, enabling great flexibility and affording wide opportunities for balancing power consumption with performance. In some embodiments, the use of multiple IVRs enables the grouping of components into separate power planes, such that power is regulated and supplied by the IVR to only those components in the group. During power management, a given power plane of one IVR may be powered down or off When the processor is placed into a certain low power state, while another power plane of another IVR remains active, or fully powered.
Still referring to
Also shown is a power control unit (PCU) 138, which may include hardware, software and/or firmware to perform power management operations with regard to processor 110. As seen, PCU 138 provides control information to external voltage regulator 160 via a digital interface to cause the voltage regulator to generate the appropriate regulated voltage. PCU 138 also provides control information to IVRs 125 via another digital interface to control the operating voltage generated (or to cause a corresponding IVR to be disabled in a low power mode). In various embodiments, PCU 138 may include a variety of power Management logic units to perform hardware-based power management. Such power management may be wholly processor controlled (e.g., by various processor hardware, and which may be triggered by workload and/or power, thermal or other processor constraints) and/or the power management may be performed responsive to external sources (such as a platform or management power management source or system software).
In embodiments herein, PCU 138 may be configured to control entry into in-field self-testing to monitor aging progress. As discussed herein, in some cases PCU 138 may trigger such diagnostic testing for a given core in connection with a low power state entry such that the given core is isolated from other cores and circuitry of processor 110. Still further, based on the results of such testing, PCU 138 may dynamically, over time, update one or more operating voltages for the core, by way of guard band voltage updates that account for aging and other degradation mechanisms.
While not shown for ease of illustration, understand that additional components may be present within processor 110 such as uncore logic, and other components such as internal memories, e.g., one or more levels of a cache memory hierarchy and so forth. Furthermore, while shown in the implementation of
Note that the power management techniques described. herein may be independent of and complementary to an operating system (OS)-based power management (OSPM) mechanism. According to one example OSPM technique, a processor can operate at various performance states or levels, so-called P-states, namely from P0 to PN. In general, the P1 performance state may correspond to the highest guaranteed performance state that can be requested by an OS. In addition to this P1 state, the OS can further request a higher performance state, namely a P0 state. This P0 state may thus be an opportunistic or turbo mode state in which, when power and/or thermal budget is available, processor hardware can configure the processor or at least portions thereof to operate at a higher than guaranteed frequency. In many implementations a processor can include multiple so-called bin frequencies above the P1 guaranteed maximum frequency, exceeding to a maximum peak frequency of the particular processor, as fused or otherwise written into the processor during manufacture. In addition, according to one OSPM mechanism, a processor can operate at various power states or levels. With regard to power states, an OSPM mechanism may specify different power consumption states, generally referred to as C-states, C0, C1 to Cn states. When a core is active, it runs at a C0 state, and when the core is idle it may be placed in a core low power state, also called a core non-zero C-state (e.g., C1-CC6 states), with each C-state being at a lower power consumption level (such that C0 is a deeper low power state than C1, and so forth).
Understand that many different types of power management techniques may be used individually or in combination in different embodiments. As representative examples, a power controller may control the processor to be power managed by some form of dynamic voltage frequency scaling (DVFS) in which an operating voltage and/or operating frequency of one or more cores or other processor logic may be dynamically controlled to reduce power consumption in certain situations. In an example, DVFS may be performed using Enhanced Intel SpeedStep™ technology available from Intel Corporation, Santa Clara, Calif., to provide optimal performance at a lowest power consumption level. In another example, DVFS may be performed using Intel TurboBoost™ technology to enable one or more cores or other compute engines to operate at a higher than guaranteed operating frequency based on conditions (e.g., workload and availability).
Another power management technique that may be used in certain examples is dynamic swapping of workloads between different compute engines. For example, the processor may include asymmetric cores or other processing engines that operate at different power consumption levels, such that in a power constrained situation, one or more workloads can be dynamically switched to execute on a lower power core or other compute engine Another exemplary power management technique is hardware duty cycling (HDC), which may cause cores and/or other compute engines to be periodically enabled and disabled according to a duty cycle, such that one or more cores may be made inactive during an inactive period of the duty cycle and made active during an active period of the duty cycle. Although described with these particular examples, understand that many other power management techniques may be used in particular embodiments.
Embodiments can be implemented in processors for various markets including server processors, desktop processors, mobile processors and so forth. Referring now to
The various cores may be coupled via an interconnect 215 to a system agent or uncore 220 that includes various components. As seen, the uncore 220 may include a shared cache 230 which may be a last level cache. In addition, the uncore may include an integrated memory controller 240 to communicate with a system memory (not shown in
In addition, by interfaces 250a-250n, connection can be made to various off-chip components such as peripheral devices, mass storage and so forth. While shown with this particular implementation in the embodiment of
Referring now to
In general, each core 310 may further include low level caches in addition to various execution units and additional processing elements. In turn, the various cores may be coupled to each other and to a shared cache memory formed of a plurality of units of a last level cache (LLC) 3400-340n. In various embodiments, LLC 340 may be shared amongst the cores and the graphics engine, as well as various media processing circuitry. As seen, a ring interconnect 330 thus couples the cores together, and provides interconnection between the cores, graphics domain 320 and system agent circuitry 350. In one embodiment, interconnect 330 can be part of the core domain. However in other embodiments the ring interconnect can be of its own domain. As further shown, a plurality of core perimeter logics 3120-312n each. may be associated with a given core and may provide for efficient storage and retrieval of context information, e.g., as used during low power entry and exit situations. In the illustration of
As further seen, system agent domain 350 may include display controller 352 which may provide control of and an interface to an associated display. As further seen, system agent domain 350 may include a power control unit 355 which can include logic to perform the power management techniques described herein. More specifically, PCU 355 includes a self-test control circuit 356 which, as described above, may be used to schedule in-field self-testing of given cores while the core is isolated. from other circuitry of processor 300 (such that this core appears to core-external circuitry as being in a low power state). Control circuit 356 may further update operating voltages based on this in-field diagnostic testing.
As farther seen in
Referring to
In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.
A core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and others are dedicated to an architectural state, the line between the nomenclature of a hardware thread and core overlaps. Yet often, a core and a hardware thread are viewed by an operating system as individual logical processors, where the operating system is able to individually schedule operations on each logical processor.
Physical processor 400, as illustrated in
As depicted, core 401 includes two hardware threads 401a and 401b, which may also be referred to as hardware thread slots 401a and 401b. Therefore, software entities, such as an operating system, in one embodiment potentially view processor 400 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers 401a, a second thread is associated with architecture state registers 401b, a third thread may be associated with architecture state registers 402a, and a fourth thread may be associated with architecture state registers 402b. Here, each of the architecture state registers (401a, 401b, 402a, and 402b) may be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers 401a are replicated in architecture state registers 401b, so individual architecture states/contexts are capable of being stored for logical processor 401a and logical processor 401b. In core 401, other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block 430 may also be replicated for threads 401a and 401b. Some resources, such as re-order buffers in reorder/retirement unit 435, ILTB 420, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB 415, execution unit(s) 440, and portions of out-of-order unit 435 are potentially fully shared.
Processor 400 often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. In
Core 401 further includes decode module 425 coupled to fetch unit 420 to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots 401a, 401b, respectively. Usually core 401 is associated with a first ISA, which defines/specifies instructions executable on processor 400. Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as art opcode), which references/specifies an instruction or operation to be performed. Decode logic 425 includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. For example, decoders 425, in one embodiment, include logic designed or adapted to recognize specific instructions, such as transactional instruction. As a result of the recognition by decoders 425, the architecture or core 401 takes specific, predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions.
In one example, allocator and renamer block 430 includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads 401a and 401b are potentially capable of out-of-order execution, where allocator and renamer block 430 also reserves other resources, such as reorder buffers to track instruction results. Unit 430 may also include a register renamer to rename program/instruction reference registers to other registers internal to processor 400. Reorder/retirement unit 435 includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and. later in-order retirement of instructions executed out-of-order.
Scheduler and execution unit(s) block 440, in one embodiment, includes a scheduler unit to schedule instructions/operation on execution units. For example, a floating point instruction is scheduled on a port of an execution unit that has an available floating point execution unit. Register files associated with the execution units are also included to store information instruction processing results. Exemplary execution units include a floating point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.
Lower level data cache and data translation buffer (D-TLB) 450 are coupled to execution unit(s) 440. The data cache is to store recently used/operated on elements, such as data operands, which are potentially held in memory coherency states. The D-TLB is to store recent virtual/linear to physical address translations. As a specific example, a processor may include a page table structure to break physical memory into a plurality of virtual pages.
Here, cores 401 and 402 share access to higher-level or further-out cache 410, which is to cache recently fetched elements. Note that higher-level or further-out refers to cache levels increasing or getting further away from the execution unit(s). In one embodiment, higher-level cache 410 is a last-level data cache—last cache in the memory hierarchy on processor 400—such as a second or third level data cache. However, higher level cache 410 is not so limited, as it may be associated with or includes an instruction cache. A trace cache—a type of instruction cache—instead may be coupled after decoder 425 to store recently decoded traces.
In the depicted configuration, processor 400 also includes bus interface module 405 and a power controller 460, which may perform power management in accordance with an embodiment of the present invention. In this scenario, bus interface 405 is to communicate with devices external to processor 400, such as system memory and other components.
A memory controller 470 may interface with other devices such as one or many memories. In an example, bus interface 405 includes a ring interconnect with a memory controller for interfacing with a memory and a graphics controller for interfacing with a graphics processor. In an SoC environment, even more devices, such as a network interface, coprocessors, memory, graphics processor, and any other known computer devices/interface may be integrated on a single die or integrated circuit to provide small form factor with high functionality and low power consumption.
Referring now to
As seen in
Coupled between from end units 510 and execution units 520 is an out-of-order (OOO) engine 515 that may be used to receive the micro-instructions and prepare them for execution. More specifically OOO engine 515 may include various buffers to re-order micro-instruction flow and allocate various resources needed for execution, as well as to provide renaming of logical registers onto storage locations within various register files such as register file 530 and extended register file 535. Register file 530 may include separate register files for integer and floating point operations. For purposes of configuration, control, and additional operations, a set of machine specific registers (MSRs) 538 may also be present and accessible to various logic within core 500 (and external to the core). For example, power limit information may be stored in one or more MSR and be dynamically updated as described herein.
Various resources may be present in execution units 520, including, for example, various integer, floating point, and single instruction multiple data (SIMD) logic units, among other specialized hardware. For example, such execution units may include one or more arithmetic logic units (ALUs) 522 and one or more vector execution units 524, among other such execution units.
Results from the execution units may be provided to retirement logic, namely a reorder buffer (ROB) 540. More specifically, ROB 540 may include various arrays and logic to receive information associated with instructions that are executed. This information is then examined by ROB 540 to determine whether the instructions can be validly retired and result data committed to the architectural state of the processor, or whether one or more exceptions occurred that prevent a proper retirement of the instructions. Of course, ROB 540 may handle other operations associated with retirement.
As shown in
Referring now to
A floating point pipeline 630 includes a floating point register file 632 which may include a plurality of architectural registers of a given bit with such as 128, 256 or 512 bits. Pipeline 630 includes a floating point scheduler 634 to schedule instructions for execution on one of multiple execution units of the pipeline. In the embodiment shown, such execution units include an ALU 635, a shuffle unit 636, and a floating point adder 638. In turn, results generated in these execution units may be provided back to buffers and/or registers of register file 632. Of course understand while shown with these few example execution units, additional or different floating point execution units may be present in another embodiment.
An integer pipeline 640 also may be provided. In the embodiment shown, pipeline 640 includes an integer register file 642 which may include a plurality of architectural registers of a given bit with such as 128 or 256 bits. Pipeline 640 includes an integer scheduler 644 to schedule instructions for execution on one of multiple execution units of the pipeline. In the embodiment shown, such execution units include an ALU 645, a shifter unit 646, and a jump execution unit 648. In turn, results generated in these execution units may be provided back to buffers and/or registers of register file 642. Of course understand While shown with these few example execution units, additional or different integer execution units may be present in another embodiment.
A memory execution scheduler 650 may schedule memory operations for execution in an address generation unit 652, which is also coupled to a TLB 654. As seen, these structures may couple to a data cache 660, which may be a L0 and/or L1 data cache that in turn couples to additional levels of a cache memory hierarchy, including an L2 cache memory.
To provide support for out execution, an allocator/renamer 670 may be provided, in addition to a reorder buffer 680, which is configured to reorder instructions executed out of order for retirement in order. Although shown with this particular pipeline architecture in the illustration of
Note that in a processor having asymmetric cores, such as in accordance with the micro-architectures of
Referring to
With further reference to
Referring to
Also shown in
Decoded instructions may be issued to a given one of multiple execution units. In the embodiment shown, these execution units include one or more integer units 835, a multiply unit 840, a floating point/vector unit 850, a branch unit 860, and a load/store unit 870. In an embodiment, floating point/vector unit 850 may be configured to handle SIMD or vector data of 128 or 256 bits. Still further, floating point/vector execution unit 850 may perform IEEE-754 double precision floating-point operations. The results of these different execution units may be provided to a writeback unit 880. Note that in some implementations separate writeback units may be associated with each of the execution units. Furthermore, understand that while each of the units and logic shown in
Note that in a processor having asymmetric cores, such as in accordance with the micro-architectures of
A processor designed using one or more cores having pipelines as in any one or more of
In the high level view shown in
Each core unit 910 may also include an interface such as a bus interface unit to enable interconnection to additional circuitry of the processor. In an embodiment, each core unit 910 couples to a coherent fabric that may act as a primary cache coherent on-die interconnect that in turn couples to a memory controller 935. As also described herein, each core unit 910 may include a mailbox interface to enable interaction with a corresponding core perimeter logic (not specifically shown in
In addition to core units, additional processing engines are present within the processor, including at least one graphics unit 920 which may include one or more graphics processing units (GPUs) to perform graphics processing as well as to possibly execute general purpose operations on the graphics processor (so-called GPGPU operation). In addition, at least one image signal processor 925 may be present. Signal processor 925 may be configured to process incoming image data received from one or more capture devices, either internal to the SoC or off-chip.
Other accelerators also may be present. In the illustration of
Each of the units may have its power consumption controlled via a power manager 940, which may include control logic to perform the various power management techniques described herein, including the control of in-field self-testing of cores while in an isolation mode.
In some embodiments, SoC 900 may further include a non-coherent fabric coupled to the coherent fabric to which various peripheral devices may couple. One or more interfaces 960a-960d enable communication with one or more off-chip devices. Such communications may be via a variety of communication protocols such as PCIe™, GPIO, USB, I2C, UART, MPI, SDIO, DDR, SPI, HDMI, among other types of communication protocols. Although shown at this high level in the embodiment of
Referring now to
As seen in
With further reference to
As seen, the various domains couple to a coherent interconnect 1040, which in an embodiment may be a cache coherent interconnect fabric that in turn couples to an integrated memory controller 1050. Coherent interconnect 1040 may include a shared cache memory, such as an L3 cache, in some examples. In an embodiment, memory controller 1050 may be a direct memory controller to provide for multiple channels of communication with an off-chip memory, such as multiple channels of a DRAM (not shown for ease of illustration in
In different examples, the number of the core domains may vary. For example, for a low power SoC suitable for incorporation into a mobile computing device, a limited number of core domains such as shown in
In yet other embodiments, a greater number of core domains, as well as additional optional IP logic may be present, in that an SoC can be scaled to higher performance (and power) levels for incorporation into other computing devices, such as desktops, servers, high performance computing systems, base stations forth. As one such example, 4 core domains each having a given number of out-of-order cores may be provided. Still further, in addition to optional GPU support (which as an example may take the form of a GPGPU), one or more accelerators to provide optimized hardware support for particular functions (e.g. web serving, network processing, switching or so forth) also may be provided. In addition, an input/output interface may be present to couple such accelerators to off-chip components.
Referring now to
In turn, a GPU domain 1120 is provided to perform advanced graphics processing in one or more GPUs to handle graphics and compute APIs. A DSP unit 1130 may provide one or more low power DSPs for handling low-power multimedia applications such as music playback, audio/video and so forth, in addition to advanced, calculations that may occur during execution of multimedia instructions. In turn, a communication unit 1140 may include various components to provide connectivity via various wireless protocols, such as cellular communications (including 3G/4G LTE), wireless local area protocols such as Bluetooth™, IEEE 802.11, and so forth.
Still further, a multimedia processor 1150 may be used to perform capture and playback of high definition video and audio content, including processing of user gestures. A sensor unit 1160 may include a plurality of sensors and/or a sensor controller to interface to various off-chip sensors present in a given platform. An image signal processor 1170 may be provided with one or more separate ISPs to perform image processing with regard to captured content from one or more cameras of a platform, including still and video cameras.
A display processor 1180 may provide support for connection to a high definition display of a given pixel density, including the ability to wirelessly communicate content for playback on such display. Still thither, a location unit 1190 may include a GPS receiver with support for multiple GPS constellations to provide applications highly accurate positioning information obtained using as such GPS receiver. Understand that while shown with this particular set of components in the example of
Referring now to
In turn, application processor 1210 can couple to a user interface/display 1220, e.g., a touch screen display. In addition, application processor 1210 may couple to a memory system including a non-volatile memory, namely a flash memory 1230 and a system memory, namely a dynamic random access memory (DRAM) 1235. As further seen, application processor 1210 further couples to a capture device 1240 such as one or more image capture devices that can record video and/or still images.
Still referring to
As further illustrated, a near field communication (NFC) contactless interface 1260 is provided that communicates in a NFC near field via an NFC antenna 1265. While separate antennae are shown in
A power management integrated circuit (PMIC) 1215 couples to application processor 1210 to perform platform level power management. To this end, PMIC 1215 may issue power management requests to application processor 1210 to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC 1215 may also control the power level of other components of system 1200.
To enable communications to be transmitted and received, various circuitry may be coupled between baseband processor 1205 and an antenna 1290. Specifically, a radio frequency (RI) transceiver 1270 and a wireless local area network (WLAN) transceiver 1275 may be present. In general, RF transceiver 1270 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as 3G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol. In addition a GPS sensor 1280 may be present. Other wireless communications such as receipt or transmission of radio signals, e.g., AM/FM and other signals may also be provided. In addition, via WLAN transceiver 1275, local wireless communications can also be realized.
Referring now to
A variety of devices may couple to SoC 1310. In the illustration shown, a memory subsystem includes a flash memory 1340 and a DRAM 1345 coupled to SoC 1310. In addition, a touch panel 1320 is coupled to the SoC 1310 to provide display capability and user input via touch, including provision of a virtual keyboard on a display of touch panel 1320. To provide wired network connectivity, SoC 1310 couples to an Ethernet interface 1330. A peripheral hub 1325 is coupled to SoC 1310 to enable interfacing with various peripheral devices, such as may be coupled to system 1300 by any of various ports or other connectors.
in addition to internal power management circuitry and functionality within SoC 1310, a PMIC 1380 is coupled to SoC 1310 to provide platform-based power management, e.g., based on Whether the system is powered by a battery 1390 or AC power via an AC adapter 1395. In addition to this power source-based power management, PMIC 1380 may further perform platform power management activities based on environmental and usage conditions. Still further, PMIC 1380 may communicate control and status information to SoC 1310 to cause various power management actions within SoC 1310.
Still referring to
As further illustrated, a plurality of sensors 1360 may couple to SoC 1310. These sensors may include various accelerometer, environmental and other sensors, including user gesture sensors. Finally, an audio codec 1365 is coupled to SoC 1310 to provide an interface to an audio output device 1370. Of course understand that while shown with this particular implementation in
Referring now to
Processor 1410, in one embodiment, communicates with a system memory 1415. As an illustrative example, the system memory 1415 is implemented via multiple memory devices or modules to provide for a given amount of system memory.
To provide for persistent storage of information such as data, applications, one or more operating systems and so forth, a mass storage 1420 may also couple to processor 1410. In various embodiments, to enable a thinner and lighter system design as well as to improve system responsiveness, this mass storage may be implemented via a SSD or the mass storage may primarily be implemented using a hard disk drive (HDD) with a smaller amount of SSD storage to act as a SSD cache to enable non-volatile storage of context state and other such information during power down events so that a fast power up can occur on re-initiation of system activities. Also shown in
Various input/output (I/O) devices may be present within system 1400. Specifically shown in the embodiment of
For perceptual computing and other purposes, various sensors may be present within the system and may be coupled to processor 1410 in different manners. Certain inertial and environmental sensors may couple to processor 1410 through a sensor hub 1440, e.g., via an I2C interconnect. In the embodiment shown in
Also seen in
System 1400 can communicate with external devices in a variety of manners, including wirelessly. In the embodiment shown in
As further seen in
In addition, wireless wide area communications, e.g., according to a cellular or other wireless wide area protocol, can occur via a WWAN unit 1456 which in turn may couple to a subscriber identity module (SIM) 1457. In addition, to enable receipt and use of location information, a GPS module 1455 may also be present. Note that in the embodiment shown in
An integrated camera module 1454 can be incorporated in the lid. To provide for audio inputs and outputs, an audio processor can be implemented via a digital signal processor (DSP) 1460, which may couple to processor 1410 via a high definition audio (HDA) link. Similarly, DSP 1460 may communicate with km integrated coder/decoder (CODEC) and amplifier 1462 that in turn may couple to output speakers 1463 which may be implemented within the chassis. Similarly, amplifier and CODEC 1462 can be coupled to receive audio inputs from a microphone 1465 which in an embodiment can be implemented via dual array microphones (such as a digital microphone array) to provide for high quality audio inputs to enable voice-activated control of various operations within the system. Note also that audio outputs can be provided from amplifier/CODEC 1462 to a headphone jack 1464. Although shown with these particular components in the embodiment of
Embodiments may be implemented in many different system types. Referring now to
Still referring to
Furthermore, chipset 1590 includes an interface 1592 to couple chipset 1590 with a high performance graphics engine 1538, by a P-P interconnect 1539. In turn, chipset 1590 may be coupled to a first bus 1516 via an interface 1596. As shown in
In general, an operating voltage for a given operating frequency is defined by a sum of a required operating voltage and a guard band voltage that thus increases the operating voltage higher than that actually required for operation. This guard band is included because silicon degrades over time, requiring a higher voltage to operate at the same frequency as a processor ages. In some processors without an embodiment, the guard band is determined at manufacture, based on part testing at beginning of life and after stressing samples to realize accelerated aging. Based on this aging and subsequent testing, a voltage guard band is determined assuming a certain amount of in-field usage models and in-field expected degradation. However there can be a number of issues with this methodology; including: using conservative assumptions such as 90% percentile heavy usage (which drives high guard bands); concerns that real emerging usages will stress parts more than expected and cause high failure rates; and new wear-out mechanisms in new processes have more random defect degradations that are hard to detect at beginning of life testing and are not gradual over lifetime.
Embodiments may be used in a wide variety of semiconductor devices including processors and other SoCs for various applications. In some cases, embodiments may be incorporated in products for industrial and automotive markets (e.g., autonomous driving cars) where there can be harsh environments that may exacerbate lifetime-related issues. For example, in some systems operation at extended temperature ranges introduces both high accelerated temperatures (e.g., between 125° Celsius (C.) and −40° C.) which can drive extreme inverse temperature dependency (ITD) and new failure mechanisms In addition, some products may have more demanding reliability targets (e.g., a failure while performing autonomous driving may have a harsh outcome), such that a core cannot be compromised while performing mission critical tasks.
In some embodiments, degradation-based testing can be performed on a core when it is isolated from normal operation, such as responsive to entry of the core into a given low power state, such as a native C6 low power state. In this regard, a native core C6 low power state (CC6) entry flow can be used to save core context, and update voltage for performing the diagnostic testing, perform the diagnostic testing, report results to a power management agent of the processor, and thereafter to actually enter the low power state (in which an integrated voltage regulator for the core may be powered off). After this low power state, the core may return to an active state by re-powering the voltage regulator to receive an operating voltage and restore pre-testing context.
Referring now to
In the high level shown in
In an embodiment, storage 1615 may be configured to remain powered on while the core is in certain low power states. As an example, storage 1615 may maintain information while a core is in a given low power state (e.g., C6) and the processor package is in a package active state (C0). However, in other low power states, such power may not be available, and the context information. may be sent to other storages. Core 1610 further includes air intra-die interconnect (IDI) interface 1618 to interface with an IDI 1670. Although not shown for ease of illustration, understand that IDI 1670 may couple core 1610 with various other circuitry within the processor (not shown for ease of illustration in
To enable core 1610 to enter into particular and deeper low power states when available, a first core perimeter logic, namely FIL 1620, is coupled to core 1610. FIL 1620 may be of a first sustain power domain, in that it is provided with power and clock signals when, at least portions of the processor are in a low power state. As seen, FIL 1620 couples to core 1610 via both DI 1670 and a second interconnect 1675, which in an embodiment is a control register interconnect (CRi). Interconnect 1675 may be a relatively simple and low performance interconnect to provide for communication of state information during save and restore operations for low power state entry and exit.
In the embodiment shown in
Still referring to
In the embodiment shown, CAB unit 1630 includes PMA 1634, a fuse puller logic 1636 that may include one or more finite state machines (FSMs) to perform save and restore operations, both with regard to storage 1622 and more distant portions of a memory hierarchy (e.g., a system memory) when CAB unit 1630 itself is to be placed into a low power state. For example, the information stored in storage 1622 may be flushed to system memory when the processor package enters a still deeper package low power state (e.g., a package C10 state). Note that PMA 1634 may be a portion of power management logic of a processor that may be active when CAB unit 1630 is powered on. In some cases, PMA 1634 may interface with a main power controller of a processor such as a PCU or other power management entity. CAB unit 1630 further includes an event blocking logic 1638, which may be configured to block incoming events When the processor is in particular low power states, including during the isolation mode described herein. Still further, CAB unit 1630 also includes a sideband interface 1639, which may interface with sideband interconnect 1690.
In an embodiment, storage 1632 of CAB unit 1630 may be allowed to be accessed. by PMA 1634 or by a verified access received via sideband interface 1639. In one such embodiment, this interface may include a security attribute identifier (SAI) logic to determine whether an access request to storage 1632 has a valid SAI security protection (e.g., a SAI value received with the request matches a SAI value associated with the storage location to be accessed). As such, storage 1632 may be secured to store sensitive content.
Understand that a processor may include additional components and circuitry. In the illustration of
In some cases, a PCU or other power controller may periodically force a given core into the isolation mode (e.g., by a special instruction to trigger the testing and post-testing entry into a core C6 state), to cause it to run diagnostic tests and perform any update of voltage guard bands, if needed. This trigger for the isolation mode may be referred to herein as a trigger into CC6 state with a reset type self-test signal. In-other cases, the PCU can cause the testing to be performed at a system processor state entry (e.g., an S3 state). When the core is in this isolation mode (and may be executing at one or more testing voltages and/or frequencies), core-external entities may consider the core in the low power state. For example, core perimeter logic such as FIL 1620 continue to ignore snoops, delay interrupts and PMA 1634 will block events. As such, when in the isolation mode, the core under has no interaction with external components.
Since each core (or cluster of cores) has a dedicated FIVR (shown in
In embodiments, the core may obtain one or more tests from, e.g., a shared cache (e.g., a mid-level cache), and store the tests for execution within a local cache of the core. Note that these tests may be stored in a special storage, e.g., RAM, ROM or system memory. Note that the test suite stored in this shared C6 DRAM is the same for all cores. As such, these tests are stored in a shared memory array that every core can access. In some embodiments, these tests may be a subset of diagnostic/stress tests used in a manufacturing facility to perform manufacturing testing or hypothetical use testing. In such cases, a pre-silicon collection of diagnostic tests may be performed to identify an appropriate subset of these tests to ensure proper die coverage. In some cases, a given test suite case be executed in a Single iteration of the isolation mode as a single pass, or different tests or chunks can be split into multiple iterations of small chunks of micro-tests.
In embodiments, the test suite may include one or more tests that can be used to identify or define a minimum voltage at which the core can correctly operate (which is a needed voltage and a guard band). If some tests are not amenable to interface using MLC-based testing without any interaction with core-external entities, they can be converted using a hardware padding mechanism to the MLC model. In a particular embodiment, approximately 10 tests can be used to determine a minVCC. If such tests are not able to fit within a capacity of a given cache, e.g., a MLC, such tests can be reduced or concatenated to fewer tests to fit within the MLC capacity. Thus in some embodiments, a small. set of test patterns can be selected to cover large portions of the die, which may enhance defect per millions (DPM) identification. In this way, where, e.g., 90% of the die or even more (as weighted for activity) is covered by a test suite as described herein, an order of magnitude reduction in DPM can be realized. This is so, as assuming random distribution of defect detecting, 90% of X DPM offers 10× reduction in DPM. In this way, a device using an embodiment can be designed with reduced area and power consumption, as intensive measures such as error correction coding (FCC) on many arrays and interconnects can be avoided. Embodiments may also detect defects as they develop in the field, such that mitigation arid user communication as to failure and/or potential failure conditions can be provided.
In some cases, a PCU or other controller may include a scheduler it to start the test as a function of the time from a last run of the test, SoC and/or system power state transitions (e.g., Cx, Sx entry), or demand-based (e.g., start a test if the last one was more than a threshold time duration ago, if the core enters natively deep C-state or is forced to power down, and/or test if core utilization is small). In an automotive example, an automotive computer is placed into a given system low power state (e.g., S3 or S0ix) every parking or switching off of the car, to allow a fast boot. These may be native test points for an isolation mode as described herein. As another example, an isolation mode may be performed when a car is stopped at a traffic light, which can be another low QoS demand point. In another use case, embodiments may be implemented in processors for servers that run 24×7, with isolation mode triggered to perform periodic testing while entering a given processor low power state (e.g., C6, C1e or forced C6).
In an embodiment, a PCU or other controller may include a timer per core that can be used to indicate when this core is to run the diagnostics described herein. When a given core counter reaches a threshold, the PCU triggers the core to enter the isolation mode. The PCU selects a given core V/F (e.g., less than a current operating voltage for the core) and then causes the core to execute the test suite a portion thereof). If the test concludes correctly, no update to the V/F for the core is indicated, and the core enters into the C6 state and then back to an active state. Instead, if one or more tests result in a failure, the PCU may increase the guard band voltage, e.g., via adding a partial guard band according to a predefined table. Thereafter the diagnostics may be run again. Such operation may proceed iteratively until the test suite passes, such that a given operating voltage is set for the core.
Referring now to
Next, control passes to block 1720 where the, timer count is incremented. Next it is determined at diamond 1725 whether the timer value is less than the minimum wait time of T2. If so, control passes back to block 1720 where the timer value is incremented. Otherwise when it is determined whether that the timer value is not less than the minimum wait time, control passes to diamond 1730 to determine whether the timer value is greater than the maximum allowed time. If so, control passes to block 1740 where the given core is forced into a low power state (e.g., a core C6). More specifically, this forced low power state entry is for the purpose of in-field core self-testing, which may be indicated by way of a self-test or isolation mode signal sent from the power controller to the given core. As such, the core may perform the self-testing within the isolation mode. Note this this core isolation mode causes the core to appear to other entities of a processor (such as other cores, graphics units, OS and so forth) as being in a low power state, such as a core C6 state. This is so, even though the core is active and in execution of one or more diagnostic/stress tests. As illustrated, after this testing control next passes back to block 1715, where the timer is reinitialized.
Still with reference to
Instead if it is determined that a native power down is to occur, control passes to block 1760 where the isolation mode or self-test signal is sent to cause the core to perform the self-testing, In addition, the timer is re-initialized. After the core performs the self-testing, it enters the given native power down state (at block 1770). Next it is determined whether the core is to exit the power down state (according to a given timer expiration, or indication of request to exit the low power state) (diamond 1780). If so, control passes back to block 1720, discussed above. Otherwise, control passes to block 1790 where the timer value is incremented (or not if the sleep state does not count for testing). Understand while shown at this high level in the embodiment of
Referring now to
In any event, control passes to block 1820 where an isolation mode signal is sent to the core to cause the core to enter into the isolation mode to perform the self-testing described herein. Still further at block 1820 an updated voltage command may be sent to the voltage regulator associated with this core to cause the voltage regulator to output a voltage to the core at this updated or reduced voltage level. Next, control passes to block 1830 where a report is received from the core. Note that this report may be sent from the core at the conclusion of the self-testing. From the report it can be determined whether the core passes the self-test (as determined at block 1840). If so, control next passes to diamond 1860 to determine whether a guard band flag has been set. If not, no further operation occurs and method 1800 concludes for this self-test. Further details regarding this guard band flag are described below.
Still with reference to
Still with reference to
In an embodiment, in response to the reset-type self-test signal, the core may execute microcode to obtain one or more tests of the test suite, e.g., from a special location in system memory (referred to as a C6 DRAM) and store it in, e.g., a MLC. The tests may then be executed. At a conclusion of he testing, if all tests are completed correctly, the core indicates a pass and sends a pass signal to, e.g., the PMA, which in turn will report this pass to the PCU. If instead. something went wrong such as a failure or a time out, a fail signal is sent to the PMA.
Referring now to
Next it is determined at diamond 1940 whether the test suite passes. If so, a pass report is sent to the power controller (block 1950). If instead the core fails the test suite, a fail report is sent to the power controller (block 1960). Note that this determination of pass or fail may be in response to execution of the self-testing to obtain a set of results (e.g., a set of results of various computations), which may then be compared to predetermined result information (e.g., the correct values for the tests). If the comparison indicates complete matches, a pass is indicated, and otherwise a fail is indicated, in one embodiment. Note that in other cases, the raw results of the test suite execution instead may be passed to the power controller to enable the power controller to identify whether a pass/fail occurs. In any event after sending a given report to the power controller, control passes to block 1970 where the core may enter a given low power state (e.g., a C6 state). Understand while shown at this high level in the embodiment of
Using an embodiment, processors may operate in the field with a lower guard band voltage, not only based on statistical parameters, but also based on real in-field aging and power delivery characteristics of a given product. Still further, embodiments may be used to resolve new failure mechanisms such as due to random defects or extended temperature related failures. Based on the testing described herein, alerts may be issued as to upcoming failures, which may be used to initiate maintenance action. In this way, a processor is adapted such that it does not have silent failures. Stated another way, a processor can detect an actual failure and not tolerate defects (e.g., as DPM), i.e., if a failure occurs it will be detected and an alert is raised, rather than waiting for an observed total system crash, which may improve reliability and survivability. Embodiments may also increase safety by lowering undetected DPMs. Note also that depending on the market segment in which a given processor or other SoC is incorporated, embodiments can be used for any combination of the above features. For example, in server and automotive environments, safety and reliability may be more relevant than guard band voltage minimization. In contrast, client systems, and mobile systems in particular, may seek to reduce voltage guard bands and hard failures, and can tolerate an occasional rare system crash.
Embodiments may enable a processor to gain 1-2 bins of frequency gain (e.g., for P1 frequency) which is approximately 3%-5% frequency improvement, in some cases. Additionally, embodiments may transform most of the silent crashes to visible alerts which improves reliability and survivability.
With an embodiment, a processor may operate over time with a changing operating voltage. However, this change in voltage (e.g., increase) may occur according to a non-linear function. As such, embodiments may reduce guard bands (which translate to higher operating frequencies) and further enhance reliability of an SoC or other processor.
Program code may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.
One or more aspects of at least one embodiment may be implemented by representative instructions stored on a non-transitory machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores” may be stored on a tangible non-transitory, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor. Accordingly, embodiments of the invention also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.
In some cases, an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction to one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof The instruction converter may be on processor, off processor, or part on and part off processor.
The following examples pertain to further embodiments.
In one example, a processor includes a core and a power controller coupled to the core and including a self-test control circuit. The self-test circuit may be configured to: isolate the core during field operation; cause the core to execute at least one diagnostic test at a first operating voltage to identify a guard band voltage for the core; and cause the core to enter into a low power state after the execution of the at least one diagnostic test.
In an example, the self-test control circuit is to isolate the core in response to expiration of a first timer, the first timer to identify a maximum duration between diagnostic tests for the core.
In an example, the self-test control circuit is to isolate the core in response to a request for the core to enter into the low power state.
In an example, the self-test control circuit is to isolate the core in response to an indication that a system including the processor is to enter into a system low power state.
In an example, the core is to obtain the at least one diagnostic test from a shared memory accessible to a plurality of cores of the processor and store the at least one diagnostic test in a local cache memory of the core.
In an example, the core is to execute the at least one diagnostic test while in an isolation mode in which the core appears to core-external circuitry of the processor as in the low power state.
In an example, the self-test control circuit is to instruct a voltage regulator associated with the core to provide the first operating voltage to the core, the first operating voltage less than a normal operating voltage for the core.
In an example, in response to a failure of the at least one diagnostic test at the first operating voltage, the power controller is to increase a guard band voltage for the core.
In an example, in response to a failure of the at least one diagnostic test at the first operating voltage, the power controller is to cause the core to re-execute the at least one diagnostic test at a second operating voltage, the second operating voltage higher than the first operating voltage, and in response to a pass of the at least one diagnostic test at the second operating voltage, to update a normal operating voltage for the core to a higher voltage than a previous normal operating voltage for the core.
In an example, the processor further comprises a plurality of cores, where each core of the plurality of cores has an independent guard band voltage based on diagnostic testing of the corresponding core.
In another example, a method comprises: selecting a reduced operating voltage for a first core of a multicore processor; sending an isolation mode signal to the first core to cause the first core to execute one or more in-field self-tests at the reduced operating voltage; and updating an operating voltage level for the first core and storing the updated operating voltage level in a table of the processor, in response to an indication from the first core of at least one failure during execution of the one or more in-field self tests at the reduced operating voltage.
In an example, the method further comprises setting a flag in response to the indication of the at least one failure, to cause an updated guard band voltage to be determined for the first core.
In an example, the method further comprises determining the updated guard band voltage based at least in part on multiple guard band voltages stored in a storage.
In an example, the method further comprises: after setting the flag, causing the first core to re-execute, the one or more in-field self-tests at a higher operating voltage than the reduced operating voltage; and determining the updated guard band voltage after the re-executed one or more in-field self-tests pass in the first core.
In an example, the method further comprises causing the first core to execute the one or more in-field self-tests while one or more other cores of the processor are in an active state, where the first core appears to the one or more other cores as being in a low power state.
In an example, the method further comprises: controlling the first core to operate at an increased operating voltage corresponding to the updated operating voltage level, the increased operating voltage including a first guard band value; and controlling a second core of the multicore processor to operate at a second operating voltage, the second operating voltage including a second guard band value, the second guard band voltage less than the first guard band voltage.
In another example, a computer readable medium including instructions is to perform the method of any of the above examples.
In another example, a computer readable medium including data is to be used by at least one machine to fabricate at least one integrated circuit to perform the method of any one of the above examples.
In another example, an apparatus comprises means for performing the method of any one of the above examples.
In yet another example, a system comprises a multicore processor including a plurality of cores to execute operations and a power controller coupled to the plurality of cores, where a first core of the plurality of cores is to enter into an isolation mode in response to a signal from the power controller while at least some other cores of the plurality of cores continue to execute the operations in the isolation mode, the first core to execute a self-test suite at a test operating voltage and report a result of the execution of the self-test suite to the power controller, the test operating voltage lower than a normal operating voltage, where the power controller is to update a guard band voltage of the first core based at least in part on the result report. The system may further include a system memory to store the self-test suite.
In an example, the system comprises an automotive vehicle computing system, and Where the power controller is to send the signal to the first core when at least a portion of the automotive vehicle computing system is in a system low power state.
In an example, the power controller is to send the signal in response to: expiration of a timer, the timer to indicate a maximum duration between in-field self-tests; a request for the first core to enter into a low power state, be system into a low power state.
In an example, the power controller is to send a second signal to a voltage regulator to cause the voltage regulator to provide the test operating voltage to the first core, and where in the isolation mode, the first core is to execute the self-test suite and appear to the at least some other cores of the plurality of cores as in a low power state.
In a still further example, an apparatus comprises: means for selecting a reduced operating voltage for a first core means of the multicore processor means; means for sending an isolation mode signal to the first core means for causing the first core means to execute one or more in-field self-tests at the reduced operating voltage; means for updating an operating voltage level for the first core means in response to an indication from the first core means of at least one failure during execution of the one or more in-field self-tests at the reduced operating voltage; and means for storing the updated operating voltage level.
In an example, the apparatus further comprises means for determining the updated guard band voltage based at least in part on multiple guard band voltages stored in a storage means.
In an example, the apparatus further comprises means for causing the first core means to re-execute the one or more in-field self-tests at a higher operating voltage than the reduced operating voltage.
In an example, the apparatus further comprises means for determining the updated guard band voltage after the re-executed one or more in-field self-tests pass in the first core means.
In an example, the apparatus further comprises voltage regulator means associated with the first core means for providing the reduced operating voltage to the first core means.
Understand that various combinations of the above examples are possible.
Note that the terms “circuit” and “circuitry” are used interchangeably herein. As used herein, these terms and the term “logic” are used to refer to alone or in any combination, analog circuitry, digital circuitry, hard wired circuitry, programmable circuitry, processor circuitry, microcontroller circuitry, hardware logic circuitry, state machine circuitry and/or any other type of physical hardware component. Embodiments may be used in many different types of systems. For example, in one embodiment a communication device can be arranged to perform the various methods and techniques described herein. Of course, the scope of the present invention is not limited to a communication device, and instead other embodiments can be directed to other types of apparatus for processing instructions, or one or more machine readable media including instructions that in response to being executed on a computing device, cause the device to carry out one or more of the methods and techniques described herein.
Embodiments may be implemented in code and may be stored on a non-transitory storage medium having stored thereon instructions which can be used to program a system to perform the instructions. Embodiments also may be implemented in data and may be stored on a non-transitory storage medium, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform one or more operations. Still further embodiments may be implemented in a computer readable storage medium including information that, when manufactured into a SoC or other processor, is to configure the SoC or other processor to perform one or more operations. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, solid state drives (SSDs), compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic. random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
