System bus control apparatus, integrated circuit and data processing system

Abstract

The present invention provides a system bus control apparatus that effectively utilizes a system bus to the full and realizes efficient data transfer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a system bus control apparatus according to the present invention;

FIG. 2 is a block diagram of a bus-master-side control section constituting the system bus control apparatus according to the present invention;

FIG. 3 is a block diagram of a bus arbiter constituting the system bus control apparatus according to the present invention;

FIG. 4 is a timing chart of a division transfer according to the system bus control apparatus of the present invention;

FIG. 5 is a timing chart of a combined transfer according to the system bus control apparatus of the present invention;

FIG. 6 is a timing chart of a priority transfer according to the system bus control apparatus of the present invention;

FIG. 7 is a flowchart of a division transfer according to the system bus control apparatus of the present invention;

FIG. 8 is a flowchart of a combined transfer according to the system bus control apparatus of the present invention;

FIG. 9 is a flowchart of a priority transfer according to the system bus control apparatus of the present invention;

FIG. 10 is a time chart of a normal transfer according to the system bus control apparatus of the present invention;

FIG. 11 is a timing chart of a division transfer according to the system bus control apparatus of the present invention;

FIG. 12 is a timing chart of a combined transfer according to the system bus control apparatus of the present invention; and

FIG. 13 is a conventional timing chart.

Claims

1. A system bus control apparatus comprising: a system bus that is a path of data transferred from a bus master;a bus condition monitoring section that monitors a used condition or unused condition of the system bus;a bus allocating section that allocates a bus width permitted to be transferred by the bus master based on the used condition or unused condition of the system bus monitored by the bus condition monitoring section, when the bus master issues a transfer request; anda bus width variable section that changes the bus width of the data transferred from the bus master in accordance with the allocated bus width.

2. A system bus control apparatus according to claim 1, wherein the bus condition monitoring section detects the used condition or unused condition of each bus of the system bus, or holds the used condition or unused condition of the system bus from the bus width and amount of the data that is requested to be transferred by the bus master.

3. A system bus control apparatus according to claim 1, wherein the bus width variable section has a function of dividing the data from the bus master in accordance with the allocated bus width when the bus width of the data requested to be transferred by the bus master is greater than the bus width allocated by the bus allocating section, and of combining the data from the bus master in accordance with the allocated bus width when the bus width of the data requested to be transferred by the bus master is smaller than the bus width allocated by the bus allocating section.

4. A system bus control apparatus according to claim 1, further comprising a data storage section that stores data when the data requested to be transferred by the bus master cannot be transferred, wherein when the bus condition monitoring section detects a bus not in use in an event that the data is stored in the data storage section, or when the bus condition monitoring section deduces a bus not in use from the held used condition or unused condition, the bus width variable section changes the bus width of the data stored in the data storage section so as to agree with a bus width corresponding to the bus width not in use.

5. A system bus control apparatus according to claim 1, wherein the bus width allocated by the bus allocating section is a fractional multiple of 2 or 1/(two factorial) of the bus width of the data requested to be transferred.

6. A system bus control apparatus according to claim 1, wherein the bus condition monitoring section has a completion expecting section that calculates an expected completion timing of the data transfer from the bus width and the amount of the data requested to be transferred by the bus master.

7. A system bus control apparatus according to claim 1, wherein, when a transfer request having a high order of priority is issued from the bus master, the bus allocating section reduces the bus width of the data currently being transferred by the bus width of the transfer-requested data having the high order of priority, and allocates the system bus to the bus master issuing the transfer request having the high order of priority.

8. A system bus control apparatus according to claim 7, wherein the order of priority is allocated beforehand to the bus master or to the bus width variable section corresponding to the bus master.

9. A system bus control apparatus according to claim 7, wherein the order of priority is allocated depending upon the amount of the data requested to be transferred by the bus master.

10. An integrated circuit comprising: a system bus that is a path of data transferred from a bus master;a bus condition monitoring section that monitors a used condition or unused condition of the system bus;a bus allocating section that allocates a bus width to be permitted to be transferred by the bus master based on the used condition or unused condition of the system bus monitored by the bus condition monitoring section, when the bus master issues a transfer request; anda bus width variable section that changes the bus width of the data transferred from the bus master in accordance with the allocated bus width.

11. A data processing system comprising: a system bus that transfers data;plural bus masters that are connected to the system bus, and have a buffer temporarily storing the data to be transferred and a bus width variable section changing a bus width; anda bus arbiter that is connected to the system bus, and has a bus condition monitoring section monitoring a used condition or unused condition of the system bus and a bus allocating section allocating a bus width permitted to be transferred by the bus master based on the used condition or unused condition of the system bus monitored by the bus condition monitoring section when the bus master issues a transfer request.