Claims
- 1. A wireless receiver which receives digital data from a remote transmitter via a radiofrequency communications link comprised of a plurality of data frames, which wireless receiver is comprised of:
a counter with a count input that is derived from a system clock signal generated within the wireless receiver, the counter also including a latch input that is derived from a frame synchronisation signal generated during each data frame; a loop filter with an input derived from the counter output; a loop gain block, which gain block receives an input derived from the loop filter output; a frequency-tuneable oscillator which receives the output of the loop gain block and generates the system clock signal, the frequency of the system clock signal being dependent upon the loop gain block output; whereby the frequency of the system clock signal is synchronized with the remote transmitter.
- 2. The wireless receiver of claim 1, in which the loop gain block input is comprised of the output of a summing block, the summing block having a first input derived from the loop filter output and a second input which receives a calibration value.
- 3. The wireless receiver of claim 1, in which the frequency-tuneable oscillator is comprised of:
a digital-to-analog converter which receives a digital input signal derived from the output of the loop gain block and generates an analog control signal; and a voltage-controlled crystal oscillator which receives the analog control signal and outputs the system clock signal, where the frequency of the system clock signal is dependent upon the analog control signal.
- 4. The wireless receiver of claim 3, in which the voltage-controlled crystal oscillator is comprised of:
a varactor which receives the analog control signal as its tuning input; and a crystal connected in parallel with the varactor.
- 5. A wireless receiver which receives digital data from a remote transmitter via a radiofrequency communications link comprised of a plurality of data frames and stores at least some of the received digital data within a buffer, the wireless receiver being comprised of:
the buffer having a load input to which a signal is applied causing data to be loaded into the buffer, and having a transfer out input to which a signal is applied causing data to be read out of the buffer; an up/down counter circuit which counts up when a signal is applied to a first input derived from the buffer load input and counts down when a signal is applied to a second input derived from the buffer transfer out input, the counter also including a latch input that is derived from a frame synchronisation signal generated during each data frame; a loop filter with an input derived from the counter output; a summing block that includes a first input which receives a calibration value and a second input derived from the loop filter output; a loop gain block, which gain block receives an input derived from the loop filter output; a frequency-tuneable oscillator which receives the output of the loop gain block and generates the system clock signal, the frequency of the system clock signal being dependent upon the loop gain block output; whereby the frequency of the system clock signal is synchronized with the remote transmitter.
- 6. The wireless receiver of claim 5, in which the loop gain block input is comprised of the output of a summing block, the summing block having a first input derived from the loop filter output and a second input which receives a calibration value.
- 7. The wireless receiver of claim 5, in which the frequency-tuneable oscillator is comprised of:
a digital-to-analog converter which receives a digital input signal derived from the output of the loop gain block and generates an analog control signal; and a voltage-controlled crystal oscillator which receives the analog control signal and outputs the system clock signal, where the frequency of the system clock signal is dependent upon the analog control signal.
- 8. The wireless receiver of claim 7, in which the voltage-controlled crystal oscillator is comprised of:
a varactor which receives the analog control signal as its tuning input; and a crystal connected in parallel with the varactor.
- 9. A method for synchronising a first system clock frequency within a first wireless device with a second system clock within a second wireless device, the first device and the second device communicating via a radiofrequency communications link comprised of a plurality of data frames, the method comprising the steps of:
receiving periodically a frame synchronisation signal by the first wireless device from the second wireless device, the frame synchronisation signal being indicative of the arrival of a data frame; measuring the number of cycles of the first system clock that occur between each frame synchronisation signal; adjusting the frequency of the system clock such that the number of cycles measured is equal to a predetermined value.
- 10. A method for controlling the frequency of an oscillator in a first wireless device which communicates via a radiofrequency communications link, the method comprising the steps of:
receiving digital data by the first wireless device via the communications link; storing the received data into a buffer within the first wireless device; reading data out from the buffer at a rate determined by a system clock signal generated within the first wireless device; determining the amount of data present within the buffer; increasing the frequency of the system clock signal when the amount of data within the buffer exceeds a predetermined level; decreasing the frequency of the system clock signal when the amount of data within the buffer falls below a predetermined level.
Priority Claims (1)
Number |
Date |
Country |
Kind |
0100094.2 |
Jan 2001 |
GB |
|
Parent Case Info
[0001] This application is a continuation application of U.S. patent application Ser. No. 10/038,963, presently pending.
Continuations (1)
|
Number |
Date |
Country |
Parent |
10038963 |
Jan 2002 |
US |
Child |
10205459 |
Jul 2002 |
US |