Claims
- 1. In an image processing apparatus, a finite impulse response digital filter bank for performing an N-point discrete cosine transform on N pixels of an image, where N is an integer, comprises:
- a circuit for receiving signal samples representing said N pixels;
- N FIR digital filters coupled to said circuit for performing said discrete cosine transform on said signal samples, each of said N FIR digital filter comprising registers and logic circuits for performing arithmetic operations, wherein the k.sup.th filter of said N FIR digital filters has, the Z-transform representation, a system function of the form, ##EQU18## where k=0, 1, 2 . . . , N-1, and wherein k.sup.th filter comprises a plurality of cascaded FIR digital filters, each cascaded FIR digital filter implementing at least one zero of said system function.
- 2. A FIR digital filter bank as in claim 1 for computing an N-point discrete cosine transform, wherein said plurality of cascaded FIR digital filters of said k.sup.th filter are each a node of a binary tree of FIR digital filters, said binary tree of FIR digital filters constituting said FIR digital filter bank.
- 3. A FIR digital filter bank as in claim 2 for computing an N-point discrete cosine transform, where said binary tree of FIR digital filters has 1+log.sub.2 N levels, such that the m.sup.th level of said 1+log.sub.2 N levels comprises 2.sup.m filters, said filters of said m.sup.th level being of order N/2.sup.m-1, where m is an integer.
- 4. A FIR digital filter bank as in claim 3, wherein the value of N is 8.
- 5. A FIR digital filter bank as in claim 4, wherein said binary tree of FIR digital filters comprises:
- a first level of FIR filters having system functions H(z)=z.sup.8 +1 and H(z)=z.sup.8 -1;
- a second level of FIR digital filters having system functions H(z)=z.sup.4 +1, H(z)=z.sup.4 -1, ##EQU19## a third level of FIR digital filters having system functions H(z)=z.sup.2 +1, H(z)=z.sup.2 -1, ##EQU20## a fourth level of FIR digital filters having system functions ##EQU21##
- 6. An apparatus for computing an 8-point discrete cosine transform for a sequence of signal samples x[0] . . . x[7], each sample representing a pixel of an image, comprising:
- a first circuit for receiving said signal sample sequence;
- means, coupled to said first circuit, for providing signals representing first quantities a[0] . . . a[3], such that
- a[0]=x[0]+x[7],
- a[1]=x[1]+x[6],
- a[2]=x[2]+x[5],
- a[3]=x[3]+x[4],
- means, coupled to said first circuit, for providing signals representing second quantities b[0] . . . b[3], such that
- b[0]=x[0]+x[7],
- b[1]=x[1]+x[6],
- b[2]=x[2]+x[5],
- b[3]=x[3]+x[4],
- means, coupled to receive said signals representing said first quantities, for providing signals representing third quantities c[0] and c[1], such that
- c[0]=a[0]+a[3],
- c[1]=a[1]+a[2],
- means, coupled to receive said signals representing said first quantities, for providing signals representing fourth quantities d[0] and d[1], such that
- d[0]=a[0]-a[3],
- d[1]=a[1]-a[2],
- means, coupled to receive said signals representing said second quantities, for providing signals representing fifth quantities e[0] and e[1], such that ##EQU22## means, coupled to receive said signals representing said second quantities, for providing signals representing sixth quantities f[0[ and f[1], such that ##EQU23## means, coupled to receive said signals representing said third quantities, for providing signals representing a seventh quantity g[0], such that g[0]=c[0]+c[1];
- means, coupled to receive said signals representing said third quantities, for providing signals representing an eight quantity h[0], such that h[0]=c[0]-c[1];
- means, coupled to receive said signals representing said fourth quantities, for providing signals representing a ninth quantity i[0], such that ##EQU24## means, coupled to receive said signals representing said fourth quantities, for providing signals representing a tenth quantity j[0], such that ##EQU25## means, coupled to receive said signals representing said fifth quantities, for providing signals representing an eleventh quantity l[0], such that ##EQU26## means, coupled to receive said signals representing said fifth quantities ad for providing signals representing a twelve quantity m[0], such that ##EQU27## means, coupled to receive said signals representing said sixth quantity, for providing signals representing a thirteenth quantity n[0], such that ##EQU28## means, coupled to receive said signals representing said sixth quantity, for providing a signals representing a fourteenth quantity o[0], such that ##EQU29## means, coupled to receive said signals representing said seventh, eight, ninth, tenth, eleventh, twelfth, thirteen ad fourteenth quantities, for providing output signals representing discrete cosine transform coefficients X[0] . . . X[8], such that ##EQU30## wherein each of said means for providing signals comprises registers and logic circuits for performing arithmetic operations.
- 7. A method for computing a 8-point discrete cosine transform for a signal sample sequence x[0] . . . x[7], each sample representing a pixel of an image, comprising the steps of:
- receiving said signal sample sequence and providing a circuit for computing quantities a[0] . . . a[3], such that
- a[0]=x[0]+x[7],
- a[1]=x[1]+x[6],
- a[2]=x[2]+x[5],
- a[3]=x[3]+x[4],
- providing a circuit for computing first quantities b[0] . . . b[3], such that
- b[0]=x[0]+x[7],
- b[1]=x[1]+x[6],
- b[2]=x[2]+x[5],
- b[3]=x[3]+x[4],
- providing a circuit for computing second quantities c[0] and c[1], such that
- c[0]=a[0]+a[3],
- c[1]=a[1]+a[2],
- providing a circuit for computing third quantities d[0] and d[1], such that
- d[0]=a[0]-a[3],
- d[1]=a[1]-a[2],
- providing a circuit for computing fourth quantities e[0] and e[1], such that ##EQU31## providing a circuit for computing fifth quantities f[0] and f[1], such that ##EQU32## providing a circuit for computing a sixth quantity g[0], such that e[0]=c[0]+c[1];
- providing a circuit for computing a seventh quantity h[0], such that h[0]=c[0]-c[1];
- providing a circuit for computing an eight quantity i[0], such that ##EQU33## providing a circuit for computing a ninth quantity j[0], such that ##EQU34## providing a circuit for computing a tenth quantity l[0], such that ##EQU35## providing a circuit for computing a eleventh quantity m[0], such that ##EQU36## providing a circuit for computing a twelfth quantity n[0], such that ##EQU37## providing a circuit for computing a thirteenth quantity o[0], such that ##EQU38## and providing signals representing discrete cosine transform coefficients X[0] . . . X[8], such that ##EQU39## wherein each of said steps of providing a circuit provides a circuit comprising registers and logic circuits for arithmetic operations.
Parent Case Info
This application is a continuation application of U.S. patent application, Ser. No. 07/495,583 filed on Mar. 16, 1990, entitled "System for Compression and Decompression of Video Data using Discrete Cosine Transform and Coding Techniques," now abandoned, which is a continuation-in-part application of U.S. patent application, Ser. No. 07/494,242 filed on Mar. 14, 1990, also entitled "System for Compression and Decompression of Video Data Using Discrete Cosine Transform and Coding Techniques."
US Referenced Citations (5)
Non-Patent Literature Citations (1)
Entry |
Matsumura et al., "An Array Processor for 2-D Discrete Cosine Transforms", Signal Processing III: Theory and Applications, Elsevier Science Publishers B.V. (North Holland) 1986 pp. 1283-1286. |
Continuations (1)
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495583 |
Mar 1990 |
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Continuation in Parts (1)
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494242 |
Mar 1990 |
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