Patent Application
20240235504
This description relates generally to systems for detecting an external reference resistor in a voltage supply path.
In industrial, automotive, petrochemical, fire control, communications and power systems, sensors are used to detect critical information. The sensors may, for example, be temperature sensors, pressure sensors, or motion sensors. Generally, to operate sensors properly, it is necessary to draw a required amount of current from the sensors or to provide a required amount of current into the sensors.
An external component (such as a resistor, capacitor and/or inductor) may be used with a programmable device that provides current to or draws current from another device. Based on the value of the external component, the programmable device provides a particular amount of current. For example, a user may connect an external reference resistor to an interface or buffer so as to “program” the amount of current sourced to/drawn from a circuit (such as a sensor). The resistance of the external reference resistor may be sensed, and a corresponding current is generated by the interface or buffer circuit. Based on the current, the interface or buffer circuit may draw from the sensors or supply current to the sensors.
Some existing solutions for sensing the resistance of an external reference resistor require a dedicated pin or a terminal of an integrated circuit (IC) for a connection to the external reference resistor. A known voltage or a known current is applied to the external reference resistor and its resistance is sensed.
It is desirable to reduce the number of pins or terminals of ICs required to sense the external reference resistor, and thus decrease the size of IC packages.
In one aspect, a system includes a system input and a system output. The system includes an operational amplifier which includes a first amplifier input coupled to the system input and includes a second amplifier input and an amplifier output. The system includes a first switch which includes a first terminal and includes a second terminal coupled to the first amplifier input. The system includes a second switch which includes a first terminal coupled to the first amplifier input and a second terminal coupled to the second amplifier input. The system includes a first bias current source coupled between the first amplifier input and a common potential and includes a second bias current source coupled between the first terminal of the first switch and the common potential. The system includes a third switch which includes a first terminal coupled to the amplifier output and includes a second terminal. The system includes a first transistor which includes a first current terminal, a second current terminal coupled to the common potential and a control terminal coupled to the second terminal of the third switch. The system includes a fourth switch which includes a first terminal coupled to the system input and a second terminal coupled to the first current terminal of the first transistor.
In an additional aspect, the system includes a first capacitor coupled between the second amplifier input and the common potential and a second capacitor coupled between the control terminal of the first transistor and the common potential.
In an additional aspect, the system includes a second transistor which includes a first current terminal coupled to the system output, a second current terminal coupled to the common potential and a control terminal coupled to the second terminal of the third switch.
In an additional aspect, the system includes a first resistor coupled between the system input and the first amplifier input.
In an additional aspect, an external resistor detection circuit includes an operational amplifier which includes a first amplifier input adapted to be coupled to the external resistor and includes a second amplifier input and an amplifier output. The circuit includes a first switch which includes a first terminal and includes a second terminal coupled to the first amplifier input. The circuit includes a second switch which includes a first terminal coupled to the first amplifier input and a second terminal coupled to the second amplifier input. The circuit includes a first bias current source coupled between the first amplifier input and a common potential and a second bias current source coupled between the first terminal of the first switch and the common potential. The circuit includes a third switch which includes a first terminal coupled to the amplifier output and includes a second terminal. The circuit includes a first transistor which includes a first current terminal, a second current terminal coupled to the common potential, and a control terminal coupled to the second terminal of the third switch. The circuit includes a fourth switch which includes a first terminal coupled to the system input and a second terminal coupled to the first terminal of the first transistor. The circuit includes a first capacitor coupled between the second amplifier input and the common potential and a second capacitor coupled between the control terminal of the first transistor and the common potential.
In an additional aspect, a circuit includes an external terminal adapted to be coupled to an external resistor. The circuit includes an operational amplifier which includes a first amplifier input coupled to the external terminal and includes a second amplifier input and an amplifier output. The circuit includes a first capacitor coupled between the second amplifier input and a common potential. The circuit includes a feedback path which includes a first terminal coupled to the amplifier output and a second terminal coupled to the external terminal. The feedback path is configured to provide an output current corresponding to the resistance of the external resistor.
The same reference numerals or other reference designators are used in the drawings to designate the same or similar (functionally and/or structurally) features.
System 100 includes system input 120 and system input/output 122. In some example embodiments, system input 120 and system input/output 122 may be connected to external terminals of an IC. The external terminals may be pins, leads (e.g., J-leads), balls (such as in a ball-grid array) or leadless terminals. The external terminals allow connections between system 100 and other circuitry or systems.
System 100 includes detector 104 which includes detector input 124 coupled to system input 120 and incudes detector output 126. System 100 includes input buffer 108 which includes buffer input 128 coupled to detector output 126 and includes buffer output 130 coupled to system output 122. In some example embodiments, input buffer 108 may include an analog-to-digital (A/D) converter (not shown in
Input buffer 108 may be coupled to sensor 112. Sensor 112 includes sensor input/output 132 coupled to system input/output 122. Sensor 112 may, for example, be a temperature sensor, a pressure sensor or a motion sensor. Sensor 112 provides output signal Spur at sensor output 134 which may represent a measured quantity such as a temperature, a pressure or a motion. Sensor output 134 may be coupled to processor and/or other analog or digital circuitry (which may be included in system 100 or another system).
System 100 is configured to detect a resistance of an external reference resistor REXT (e.g., between around 700 ohms to around 4K ohms) in a supply path. Here, the supply path refers to a conduction path between voltage supply VCC (e.g., around 24V) and system input 120. External reference resistor REXT includes first terminal 134 coupled to system input 120 and includes second terminal 136. Voltage supply VCC includes first terminal 138 coupled to second terminal 136 of REXT and includes second terminal 140 coupled to common potential 150 (e.g., ground). When system input 120 is coupled to voltage supply VCC via REXT, voltage AVDD appears at system input 120.
To operate sensor 112 properly, input buffer 108 draws a particular amount of current from sensor 112 or provides a particular amount of current into sensor 112. In some example embodiments, detector 104 determines a resistance of REXT and based on the resistance value provides output current IOUT (which corresponds to the resistance value of REXT). Based on the value of IOUT, input buffer 108 draws current IIN from sensor 112 or provides current IIN into sensor 112. A user may, for example, connect REXT in the supply path between system input 120 and supply voltage VCC, and based on the resistance value of REXT, detector 104 provides a corresponding IOUT to input buffer 108. In response to the value of IOUT, input buffer 108 current draws IIN from sensor 112 or provides current IIN to sensor 112. As such, system 100 provides a current programmability based on REXT.
Detector 200 includes operational amplifier A1 which includes first amplifier input 204 (e.g., non-inverting input), second amplifier input 206 (e.g., inverting input) and amplifier output 208. First amplifier input 204 is coupled to detector input 124 via resistor RINT (e.g., around 500K ohms) (may also be referred to as the “first resistor”). Detector 200 includes first switch S1 which includes first terminal 210 and includes second terminal 212 coupled to first amplifier input 204. When S1 is closed (e.g., S1 is conducting such that terminal 210 is connected to terminal 212), and thus a conduction path is provided for a current through S1. When S1 is opened (e.g., S1 is non-conducting such that terminal 210 is electrically isolated from terminal 212) current does not flow through S1. Detector 200 includes second switch S2 which includes first terminal 214 coupled to first amplifier input 204 and includes second terminal 216 coupled to second amplifier input 206. S1 and S2 may be implemented using similar (or identical) components. In some example embodiments, S1 and S2 are implemented with transistors (e.g., n-channel transistors or NMOS transistors).
Detector 200 includes first bias current source IBIAS1 (e.g., around 40 micro-amps) coupled between first amplifier input 204 and common potential 150 (e.g., ground). Detector 200 includes second bias current source IBIAS2 (e.g., around 1 micro-amp) coupled between first terminal 210 of first switch S1 and common potential 150.
Detector 200 includes third switch S3 which includes first terminal 218 coupled to amplifier output 208 and includes second terminal 220. Detector 200 includes first transistor M1 (e.g., NMOS transistor) which includes first current terminal 222 (e.g., drain), second current terminal 224 (e.g., source) coupled to common potential 150, and control terminal 226 (e.g., gate) coupled to second terminal 220 of third switch S3.
Detector 200 includes fourth switch S4 which includes first terminal 240 coupled to system input 120 (and also coupled to detector input 124) and second terminal 242 coupled to first current terminal 222 of first transistor M1. In some example embodiments, S3 and/or S4 are implemented with transistors (e.g., NMOS transistors).
Detector 200 includes first capacitor C1 (e.g., around 5 pico-farads) coupled between second amplifier input 206 and common potential 150 and includes second capacitor C2 (e.g., around 15 pico-farads) coupled between control terminal 226 of first transistor M1 and common potential 150.
In some example embodiments, detector 200 includes second transistor M2 (e.g., NMOS transistor) which includes first current terminal 230 (e.g., drain) coupled to detector output 126 which is coupled to system output 122 via input buffer 108 (illustrated in
A user may couple external reference resistor REXT between system input 120 and voltage supply VCC in the supply path. As a result, voltage Av DD appears at system input 120.
In some example embodiments, detector 200 operates in three phases. The states of switches S1, S2, S3 and S4 in phases 1, 2 and 3 are shown in
In phase 1, illustrated in
In phase 1, voltage AVDD (graph 250) is approximately 24V. Because in phase 1 first amplifier input 204 and second amplifier input 206 are shorted together, the voltage at first amplifier input 204 (graph 252) and the voltage at second amplifier input 206 (graph 254) are at the same potential (e.g., around 1.95V). Also, in phase 1, because switch S3 is opened and capacitor C2 is not charged, the voltage across control terminal 226 and second current terminal 224 of M1 (graph 256) is approximately zero.
In phase 2, illustrated in
Thus, in phase 2, voltage AVDD (graph 250) remains approximately the same (e.g., around 24V); the voltage at first amplifier input (graph 252) rises by around 500 mV; and the voltage at second amplifier input (graph 254) is held constant. Because in phase 2, switch S3 remains open, capacitor C2 is not charged. Thus, the voltage across control terminal 226 and second current terminal 224 of M1 (graph 256) is approximately zero.
In phase 3, illustrated in
ΔV=(IBIAS2)*(RINT) (1)
where ΔV is the rise in the voltage across REXT.
Because current IM1 through transistor M1 is correlated to the voltage across control terminal 226 and second current terminal 224 of M1 (e.g., gate-to-source voltage VGS of M1), the voltage across control terminal 226 and second current terminal of M1 may be measured from the voltage across capacitor C2. Based on the voltage across capacitor C2, current IM1 through M1 is determined, and the resistance of REXT is determined from IM1 and ΔV.
In some example embodiments, transistors M1 and M2 are identical to one another (e.g., M1 and M2 have the same characteristics). Because control terminal 226 of M1 is coupled to control terminal 234 of M2, and second current terminal 224 of M1 and second current terminal 232 of M2 are both coupled to common potential 150, M1 and M2 conduct equal amount of current. Thus, current IOUT through M2 is equal to current IM1 through M1. In response to IOUT, input buffer 108 (shown in
In phase 3, voltage AVDD (graph 250) falls by approximately 500 mV to around 23.5V, the voltage at first amplifier input (graph 252) falls by 500 mV to around 1.95V and the voltage at second amplifier input (graph 254) is held constant. Because in phase 3, switch S3 is closed, capacitor C2 is charged. Thus, the voltage across control terminal 226 and second terminal 224 of M1 (graph 256) rises (e.g., voltage rises to around 1.32V).
In some example embodiments, input buffer 108 may include an A/D converter (not shown in
Detector 400 includes first bias current source IBIAS1 coupled between first amplifier input 204 and common potential 150. In some example embodiments, IBIAS1 is implemented with transistor M10 (e.g., NMOS transistor), switch S10 and capacitor C13. Transistor M10 includes first current terminal 402 (e.g., drain) coupled to first amplifier input 204, second current terminal 404 (e.g., source) coupled to common potential 150 and includes control terminal 406 (e.g., gate). Switch S10 includes first terminal 408 coupled to control terminal 406 of M10 and includes second terminal 410 coupled to first current terminal 402 of M10. Capacitor C13 is coupled between control terminal 406 of M1 and common potential 150. When switch S10 is closed, first current terminal 402 and control terminal 406 of M1 are coupled together, and, as such, M10 has a diode connection and capacitor C13 is charged. When switch S10 is opened, capacitor C13 maintains a constant voltage across control terminal 406 and second current terminal 404 of M10, and, as such, a constant current (e.g., IBIAS1) flows through M10. In some example embodiments, capacitor C13 is charged to a voltage level necessary to operate M10 in a saturation region so that a constant current (e.g., IBIAS1) flows through M10. In some example embodiments, switch S10 is periodically opened and closed to recharge capacitor C13, thus replenishing any charge which may be lost in capacitor C13 due to leakage. In some example embodiments, current source IBIAS2 may be implemented in similar or substantially similar manner as current source IBIAS1.
Detector 400 includes switch S4 which is implemented with transistor M11 (e.g., NMOS transistor) and switch S11. Transistor M11 includes first current terminal 420 (e.g., drain) coupled to detector input 124, second current terminal 422 (e.g., source) coupled to first current terminal 222 of transistor M1 and includes control terminal (e.g., gate). Switch S11 includes first terminal 426 coupled to voltage supply VDD and includes second terminal 428 coupled to control terminal 424 of M11. When switch S11 is closed, control terminal 424 of M11 is coupled to voltage supply VDD, and, as such, M11 conducts. Thus, first current terminal 222 of M1 is coupled to detector input 124 via M11. When switch S11 is opened, VDD is disconnected from control terminal 424 of M11, and, as such, M11 does not conduct, and first current terminal 222 of M1 is disconnected from detector input 124.
In some example embodiments, resistor R2 (e.g., around 50K ohms) is coupled between control terminal 226 of M1 and capacitor C2. Resistor R2 includes first terminal 430 coupled to control terminal 226 of M1 and includes second terminal 432. Capacitor C2 includes first terminal 434 coupled to second terminal 432 of resistor R2 and includes second terminal 436 coupled to common potential 150.
In some example embodiments, detector 400 includes capacitor C10 coupled between control terminal 234 of M2 and common potential 150. Detector 400 includes switch S12 which includes first terminal 440 coupled to first terminal 434 of capacitor C2 and includes second terminal 442 coupled to control terminal 234 of M2. When switch S12 is closed, control terminal 234 of M2 is coupled to control terminal 226 of M1 and capacitor C10 is charged. As such, transistor M2 conducts and draws current IOUT. The voltage across control terminal 226 and second current terminal 224 of M1 (e.g., gate-to-source voltage VGS of M1) is approximately at the same level as the voltage across control terminal 234 and second current terminal 232 of M2. Thus, M1 and M2 conduct the same amount of current (e.g., IOUT is equal to IM1). When switch S12 is opened, the voltage across control terminal 234 and second current terminal 232 of M2 is held at a constant voltage by capacitor C10, thus allowing transistor M2 to continue to conduct. In some example embodiments, switch S12 is periodically opened and closed to recharge capacitor C10, thereby replenishing any charge which may be lost in capacitor C10 due to leakage.
To protect detector 400 from an instantaneous surge in voltage supply VCC, surge resistor RSURGE (e.g., around 1K ohms) is coupled in series in the supply path. Resistor RSURGE includes first terminal 460 coupled to first terminal 138 of VCC and includes second terminal 462 coupled to second terminal 136 of resistor REXT. Resistor RSURGE limits current flowing in the supply path. Capacitor C11 (e.g., around 1 micro-farad) is coupled between second terminal 462 of RSURGE and common potential 150. At high frequencies, capacitor C11 acts as a short circuit (e.g., capacitor C11 has a very low impedance at high frequencies), thereby providing a path for any instantaneous surge current to flow to ground. At low frequencies, capacitor C11 acts as an open circuit (e.g., capacitor C11 has a very high impedance at low frequencies), thereby coupling VCC to system input 120.
In some example embodiments, capacitor C12 (e.g., around 1 micro farad) is coupled between system input 120 and common potential 150. Capacitor C12 maintains a stable DC voltage (e.g., AVDD) at system input 120 by reducing AC ripple.
Because detectors 100, 200 and 400 are configured to sense and determine the resistance of an external resistor (e.g., REXT) coupled in the supply path without requiring an additional pin in an IC, the number of pins in an IC package is reduced. As a result, the size of an IC package is reduced, thereby reducing fabrication cost of an IC package.
The circuits described herein may include one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors and/or inductors), and/or one or more sources (such as voltage and/or current sources). The circuits may include only semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, such as by an end-user and/or a third party. While some example embodiments may include certain elements implemented in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and/or some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term “integrated circuit” means one or more circuits that are: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and/or (iv) incorporated in/on the same printed circuit board.
In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal provided by device A. Also, in this description, a device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof. Furthermore, in this description, a circuit or device that includes certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, such as by an end-user and/or a third party.
As used herein, the terms “terminal”, “node”, “interconnection”, “ball” and “pin” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronics or semiconductor component.
While some example embodiments suggest that certain elements are included in an integrated circuit while other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and/or some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term “integrated circuit” means one or more circuits that are: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and/or (iv) incorporated in/on the same printed circuit board.
While the use of particular transistors are described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, a metal-oxide-silicon FET (“MOSFET”) (such as an n-channel MOSFET, nMOSFET, or a p-channel MOSFET, pMOSFET), a bipolar junction transistor (BJT—e.g. NPN or PNP), insulated gate bipolar transistors (IGBTs), and/or junction field effect transistor (JFET) may be used in place of or in conjunction with the devices disclosed herein. The transistors may be depletion mode devices, drain-extended devices, enhancement mode devices, natural transistors or other type of device structure transistors. Furthermore, the devices may be implemented in/over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).
While certain elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and/or some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term “integrated circuit” means one or more circuits that are: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and/or (iv) incorporated in/on the same printed circuit board.
While certain components may be described herein as being of a particular process technology, these components may be exchanged for components of other process technologies. Circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to functionality available before the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series or in parallel between the same two nodes as the single resistor or capacitor. Also, uses of the phrase “ground” or “ground terminal” in this description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. Unless otherwise stated, “about”, “approximately”, or “substantially” preceding a value means +/−10 percent of the stated value, or, if the value is zero, a reasonable range of values around zero.
| Number | Date | Country | |
|---|---|---|---|
| 20240136989 A1 | Apr 2024 | US |
