BRIEF DESCRIPTION OF THE DRAWINGS
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIGS. 1A to 1F are cross sections of an embodiment of a method for fabricating a system for displaying images incorporating a thin film transistor device.
FIG. 2 is a cross section of an embodiment of a thin film transistor device.
FIG. 3 schematically shows another embodiment of a system for displaying images.
DETAILED DESCRIPTION OF THE INVENTION
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
Systems for displaying images and fabrication methods for same are provided. FIGS. 1F and 2 illustrate exemplary embodiments of such a system. Specifically, the system incorporates a thin film transistor (TFT) device 200 comprising a substrate 100 comprising a driving circuit region D and a pixel region P. A buffer layer 102 may be optionally disposed on the substrate 100 to serve as an adhesion layer or a contamination barrier layer between the substrate 100 and the subsequent active layer.
A first active layer 112 is disposed on the substrate 100 of the driving circuit region D and a second active layer 114 on the substrate 100 of the pixel region P. The first active layer 112 may comprise a channel region 113a and a pair of source/drain regions 113b separated by the channel region 113a. The second active layer 114 may also comprise a channel region 115a and a pair of source/drain regions 115b separated by the channel region 115a. In this embodiment, the first and second active layers 112 and 114 may comprise low temperature polysilicon, in which the first active layer 112 has a grain size greater than that of the second active layer 114.
Fabrication of two gate structures are disposed on the first and second active layers 112 and 114, respectively, thus TFTs are complete. The TFT in the pixel region P (i.e. pixel TFT) may comprise an NMOS or a CMOS. The TFT in the driving circuit region D (i.e. driving TFT) may comprise an NMOS, a PMOS, or a CMOS. The gate structure disposed on the first active layer 112 comprises a stack of a gate dielectric layer 116 and a gate layer 118. The gate structure disposed on the active layer 114 also comprises a stack of the gate dielectric layer 116 and a gate layer 120.
A reflector 105, such as a metal layer, is disposed on the substrate 100 under the first active layer 112. Moreover, the reflector 105 is insulated from the first active layer 112 by an insulating layer 106, such as a silicon oxide, a silicon nitride or a combination thereof. In this embodiment, the first active layer 112 may be substantially aligned to the reflector 105, as shown in FIG. 1F. In some embodiments, the reflector 105 may completely cover the substrate 100 of the driving circuit region D, as shown in FIG. 2.
Referring to FIGS. 1A to 1F, which illustrate an embodiment of a method for fabricating a system for displaying images incorporating a thin film transistor device 200. In FIG. 1A, a substrate 100 comprising a driving circuit region D and a pixel region P is provided. The substrate 100 may comprise glass, quartz, or plastic. A buffer layer 102 may be optionally formed on the substrate 100 to serve as an adhesion layer or a contamination barrier layer between the substrate 100 and the subsequent layer formed thereon. The buffer layer 102 may be a single layer or multiple layers. For example, the buffer layer 102 may comprise silicon oxide, silicon nitride, or a combination thereof.
A reflective layer 104 is formed on the substrate 100. The reflective layer 104 may comprise metal, such as aluminum (Al), copper (Cu), molybdenum (Mo) or an alloy. Moreover, the reflective layer 104 may have a thickness of more than 100 Å and be formed by conventional deposition, such as sputtering or CVD.
In FIG. 1B, the reflective layer 104 is patterned by conventional lithography and etching, to form a reflector 105 on the substrate 100 of the driving circuit region D. In this embodiment, the reflector 105 is located at a region in the driving circuit region D for definition of the active layer in subsequent process steps. In some embodiments, the substrate 100 in the driving circuit region D may be completely covered by the formation of the reflector 105.
In FIG. 1C, an insulating layer 106 and an amorphous layer (not shown) are successively formed on the substrate 100 of the driving circuit and pixel region D and P to cover the reflector 105, such that the amorphous layer can be insulated from the reflector 105 by the insulating layer 106. In this embodiment, the insulating layer 106 may be a single layer or multiple layers. For example, the insulating layer 106 may comprise silicon oxide, silicon nitride, or a combination thereof.
Next, a laser annealing treatment 109 is performed on the amorphous layer, such that the amorphous silicon layer is transformed into a polysilicon layer 108. In conventional low temperature polysilicon (LTPS) fabrication, the polysilicon layer is formed by excimer laser annealing (ELA). Reduction of the sub-threshold swing of driving TFTs is, however, difficult because the grain size of the polysilicon layer formed by the excimer laser typically having a wavelength of about 248 nm to 351 nm is not large enough. Accordingly, in this embodiment, a laser beam having a wavelength of not less than 400 nm, such as a solid-state laser beam, is employed for the laser annealing treatment 109, which has better penetration than excimer laser beam for an amorphous material. Accordingly, the laser beam having a wavelength of not less than 400 nm can be repeatedly reflected from the reflector 105 through the amorphous layer and the insulating layer 106, so as to provide a higher crystallization temperature on the portion 110 of the polysilicon layer 108 directly above the reflector 105. That is, the portion 110 of the polysilicon layer 108 directly above the reflector 105 has a grain size greater than that of other portions. Typically, the grain size of the polysilicon material is inversely proportional to the grain-boundary capacitance. Conversely, the grain-boundary capacitance is proportional to the sub-threshold swing. Accordingly, a lower sub-threshold swing can result when the grain size of the polysilicon layer serving as an active layer for a thin film transistor (TFT) is increased. Next, a channel doping process may be optionally performed on the polysilicon layer 108.
In FIG. 1D, the polysilicon layer 108 shown in FIG. 1C is subsequently patterned to form a polysilicon pattern layer 112 overlying the reflector 105 in the driving circuit region D and a polysilicon pattern layer 114 overlying the substrate 100 of the pixel region P. Particularly, the polysilicon pattern layer 112 is substantially aligned to the reflector 105 polysilicon pattern layer 112. The polysilicon pattern layers 112 and 114 serve as first and second active layers for TFTs in the pixel region P and in the driving circuit region D, respectively. Since the first active layer 112 substantially aligned to the reflector 105 is formed at a higher crystallization temperature than that of the formation of the second active layer 114, the first active layer 112 has a grain size greater than that of the second active layer 114.
In FIG. 1E, an insulating layer 116 and a conductive layer (not shown) are successively formed on the first and second active layers 112 and 114 and the insulating layer 106. In this embodiment, the insulating layer 116 serves as a gate dielectric and may be a single layer or multiple layers. For example, the insulating layer 116 may comprise silicon oxide, silicon nitride, or a combination thereof. The insulating layer 116 can be formed by conventional deposition, such as CVD. The conductive layer may comprise metal, such as molybdenum (Mo) or Mo alloy. The conductive layer can be formed by CVD or sputtering. The conductive layer is subsequently etched to form gate layers 118 and 120 overlying the first and second active layers 112 and 114, respectively.
In FIG. 1F, heavy-ion implantation 121 is subsequently performed in the first and second active layers 112 and 114 using the gate layers 118 and 120 as implantation masks. After completion of the heavy-ion implantation 121, a channel region 113a is formed in the first active layer 112 under the gate layer 118 and a pair of source/drain regions 113b is formed in the first active layer 112 and separated by the channel region 113a. A channel region 115a is also formed in the second active layer 114 under the gate layer 120 and a pair of source/drain regions 115b is formed in the second active layer 114 and separated by the channel region 115a. Thus, a thin film transistor device 200 of the invention is complete.
According to the invention, since the second active layer 114 in the pixel regions P has a smaller grain size than that of the first active layer 112 in the driving circuit region D, the pixel TFT can have a higher sub-threshold swing than the driving TFT in the driving circuit region D. Accordingly, the TFT device 200 can have different electrical characteristics in the driving circuit and pixel regions D and P. That is, a relatively high sub-threshold swing for the pixel TFT can be obtained to increase gray scale inversion of display device, thereby providing high contrast ratio for display devices. At the same time, relatively high carrier mobility and relatively low sub-threshold swing for the driving TFT can be obtained, thereby providing fast response.
FIG. 3 schematically shows another embodiment of a system for displaying images which, in this case, is implemented as a flat panel display (FPD) device 300 or an electronic device 500 such as a laptop computer, a mobile phone, a digital camera, a personal digital assistant (PDA), a desktop computer, a television, a car display or a portable DVD player. The described TFT device can be incorporated into the flat panel display device 300 that can be an LCD or OLED panel. As shown in FIG. 3, the FPD device 300 may comprise a TFT device, such as a TFT device 200 shown in FIG. 1F or 2. In some embodiments, the TFT device 300 can be incorporated into the electronic device 500. As shown in FIG. 3, the electronic device 500 comprises the FPD device 300 and an input unit 400. Moreover, the input unit 400 is coupled to the FPD device 300 and operative to provide input signals (e.g. image signals) to the FPD device 300 to generate images.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Patent Application
20080042131
