Claims
- 1. A computer system comprising:a plurality of nodes interconnected in a serial ringlet network topology; wherein each of said plurality of nodes is configured to: maintain a first set of information indicating a sequence of a plurality of transmitted packets sent by each of a first portion of said plurality of nodes; maintain a second set of information indicating a sequence of a plurality of received acknowledgements received by each of said first portion of said plurality of nodes; detect an error condition wherein a sent packet has not resulted in an acknowledgement; and retry a sequence of ordered packets sent from a given node prior to the detection of said error condition, wherein said sequence of ordered packets begins with a last good ordered packet prior to said sent packet and extends through a last packet.
- 2. The computer system as recited in claim 1, wherein each of said plurality of nodes is further configured to maintain a third set of information indicating whether a sequence number of a given received packet is a valid sequence number.
- 3. The computer system as recited in claim 2, wherein each of said plurality of nodes is further configured to maintain a fourth set of information indicating whether said given received packet may be accepted or rejected by the node and a type of acknowledgment to return.
- 4. The computer system as recited in claim 3, wherein said third set of information and said fourth set of information is maintained for each sending node of said plurality of nodes.
- 5. The computer system as recited in claim 1, wherein each of said plurality of nodes is configured to maintain said sequence in strong sequential ordering between all connected pairs of nodes in said serial ringlet network.
- 6. The computer system as recited in claim 1, wherein a given node of said plurality of nodes is configured to maintain unaltered state information of said given node in response to receiving another instance of a previously received nonidempotent packet.
- 7. The computer system as recited in claim 1, wherein each of said plurality of nodes is connected to said serial ringlet network via a pair of unidirectional signal paths.
- 8. The computer system as recited in claim 1, wherein said serial ringlet network is compatible with P1394.2 Serial Express technology, characterized by each of said plurality of nodes including a bypass buffer configured to shunt a received packet from a first path of said pair of unidirectional signal paths to a second path of said pair of unidirectional signal paths.
- 9. The computer system as recited in claim 8, wherein each of said plurality of nodes further includes an insertion buffer configured to store new packets prior to said new packets being inserted into said serial ringlet network.
- 10. The computer system as recited in claim 9, wherein said new packets stored in said insertion buffer are prevented from being inserted if said bypass buffer is full.
- 11. The computer system as recited in claim 10, wherein all packets are 64 bytes or less.
Parent Case Info
This a continuation of Ser. No. 08/674,033, filed Jul. 1, 1996.
US Referenced Citations (12)
Non-Patent Literature Citations (2)
Entry |
Dijkstra, “Solution of a Problem in Concurrent Programming Control,” Sep. 1965, p. 569. |
Gustavson, “The Scalable Coherent Interface and Related Standards Projects,” Feb. 1992, pp. 10-22. |
Continuations (1)
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Number |
Date |
Country |
Parent |
08/674033 |
Jul 1996 |
US |
Child |
09/512957 |
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US |