Claims
- 1. A method of producing a double diffused semiconductor device to minimize performance impact of end cap regions, comprising the steps of:
providing a moat region; providing an oxide region overlappingly disposed over the moat region; and providing a double-diffusion region, disposed within the oxide region, having end cap regions thereto that are effectively deactivated.
- 2. The method of claim 1, wherein the end cap regions are disposed within the oxide region but outside the moat region.
- 3. The method of claim 1, wherein the end cap regions are disposed within the oxide and moat regions.
- 4. The method of claim 2, wherein a portion of the double-diffusion within the moat region is formed having substantially straight edges.
- 5. The method of claim 2, wherein a portion of the double-diffusion within the moat region is formed having concave edges flaring out towards the end cap regions.
- 6. The method of claim 3, wherein the double diffusion region is formed having minimal width and minimal length end cap regions.
- 7. The method of claim 3, wherein the end cap regions are effectively deactivated by implanting them with an opposite type material.
- 8. The method of claim 7, wherein the double diffusion region comprises an n-type material and a p-type material is implanted in the end cap regions.
- 9. The method of claim 8, wherein the double diffusion region comprises Arsenic and Boron is implanted in the end cap regions.
- 10. The method of claim 8, wherein the double diffusion region comprises Arsenic and PSD is implanted in the end cap regions.
- 11. The method of claim 9, wherein the Boron is implanted before poly deposition.
- 12. A double diffused semiconductor device comprising:
a moat region; an oxide region overlappingly disposed over the moat region; and a double-diffusion region, disposed within the oxide region, having end cap regions thereto that are effectively deactivated.
- 13. The device of claim 12, wherein the end cap regions are disposed within the oxide region but outside the moat region.
- 14. The device of claim 12, wherein the end cap regions are disposed within the oxide and moat regions.
- 15. The device of claim 13, wherein a portion of the double-diffusion within the moat region is formed having substantially straight edges.
- 16. The device of claim 13, wherein a portion of the double-diffusion within the moat region is formed having concave edges flaring out towards the end cap regions.
- 17. The device of claim 14, wherein the double diffusion region is formed having minimal width and minimal length end cap regions.
- 18. The device of claim 14, wherein the end cap regions are implanted with an opposite type material.
- 19. The device of claim 18, wherein the double diffusion region comprises an n-type material and a p-type material is implanted in the end cap regions.
- 20. A double diffused MOS transistor comprising:
a moat region; an oxide region laterally and overlappingly disposed over the moat region; a double-diffusion region, having semi-spherical end cap regions at opposite ends, disposed within the oxide and moat regions; a source contact formed within the double diffusion region; a drain contact formed within the moat region outside the double diffusion region; and opposite type implants disposed within the end cap regions.
PRIORITY CLAIM
[0001] This patent application claims priority of U.S. Provisional Application No. 60/344512, filed on Dec. 28, 2001.
Provisional Applications (1)
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Number |
Date |
Country |
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60344512 |
Dec 2001 |
US |