System for linear amplitude modulation

Abstract

System for linear amplitude modulation. Apparatus is provided for linear amplitude modulation of an amplifier. The apparatus includes a processing circuit that receives an amplitude modulation signal and produces one or more amplifier control signals that are coupled to the amplifier. The apparatus also includes a feedback circuit that generates a feedback signal from an output of the amplifier that is input to the processing circuit; and a network that controls a bias of the amplifier in response to the feedback signal to linearize the amplifier's amplitude control.

Description

FIELD

This application relates generally to power amplifiers, and more particularly, to a system for efficient and highly linear amplitude modulation.

BACKGROUND

Modern communication systems increasingly employ modulation methods such as 8-PSK, 16-QAM, 64-QAM, and OFDM to increase data speeds and to improve spectrum efficiency. This added complexity invariably increases the amplitude (or envelope) fluctuations of the transmit signal—generally measured by the transmit signal's peak-to-average (pk/ave) ratio. As a result, the radio transmitter sees higher peaks and tends to generate more distortion. To minimize distortion, most linear circuits operate at a bias current proportional to the largest amplitude or peak of the transmit signal. This can be very inefficient in systems that produce signals with a large peak-to-average ratio.

A radio transmitter generally uses a power amplifier to close the link to the receiver. The power amplifier typically dissipates more power than any other circuit so its efficiency is critical. It would therefore be advantageous to have a system for operating a power amplifier at lower power levels while keeping distortion low.

SUMMARY

In one or more embodiments, a system for linear amplitude modulation is provided. In one embodiment, the system comprises a very efficient amplifier that can be used with any type of modulated signal, including signals modulated with constant and envelope-varying techniques.

In one embodiment, apparatus is provided for linear amplitude modulation of an amplifier. The apparatus comprises a processing circuit that receives an amplitude modulation signal and produces one or more amplifier control signals that are coupled to the amplifier. The apparatus also comprises a feedback circuit that generates a feedback signal from an output of the amplifier that is input to the processing circuit, and a network that controls a bias of the amplifier in response to the feedback signal to linearize the amplifier's amplitude control.

In one embodiment, apparatus is provided for linear amplitude modulation of an amplifier. The apparatus comprises means for receiving an amplitude modulation signal and producing one or more amplifier control signals that are coupled to the amplifier. The apparatus also comprises means for generating a feedback signal from an output of the amplifier that is input to the means for receiving, and means for controlling a bias of the amplifier in response to the feedback signal to linearize the amplifier's amplitude control.

Other aspects of the embodiments will become apparent after review of the hereinafter set forth Brief Description of the Drawings, Detailed Description, and the Claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects of the embodiments described herein will become more readily apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings wherein:

FIG. 1 shows a block diagram of a radio transmitter;

FIG. 2 shows a power amplifier gain stage;

FIG. 3 shows a graph that illustrates transistor output curves for the power amplifier shown in FIG. 2 when driven by a sinusoidal input waveform;

FIG. 4 shows a graph that illustrates various operating modes for an amplifier;

FIG. 5 shows a block diagram of a polar modulator;

FIG. 6 shows a block diagram of a phase/frequency synthesizer for use with a polar modulator;

FIG. 7 shows a diagram of an amplifier that supports amplitude modulation through the supply;

FIG. 8 shows a diagram of an amplifier that supports amplitude modulation through a bias network;

FIG. 9 shows one embodiment of a polar modulator with system calibration for improved amplitude modulation;

FIG. 10 shows another embodiment of a polar modulator that comprises a feedback circuit for improved amplitude modulation;

FIG. 11 shows one embodiment of an amplitude modulation architecture that comprises a feedback loop;

FIGS. 12 a-d show a detailed diagram of one embodiment of a processing circuit for use in the modulation architecture of FIG. 11, and associated graphs;

FIG. 13 shows a graph that illustrates the power spectral density with and without alignment of the phase and amplitude modulation signals;

FIG. 14 shows one embodiment of a system for aligning the phase and amplitude signals in a polar modulator;

FIG. 15 shows graphs that illustrate power spectral density of frequency and amplitude modulation signals;

FIG. 16 shows one embodiment of a system for aligning the phase and amplitude signals in a polar modulator;

FIG. 17 shows one embodiment of a system for aligning the phase and amplitude signals in a polar modulator;

FIGS. 18 a-d show graphs that illustrate one embodiment of a method to compensate for the effects of a narrow filter;

FIG. 19 shows one embodiment of an EXP circuit;

FIG. 20 shows a graph that illustrates the operation of the EXP circuit shown in FIG. 19;

FIG. 21 shows one embodiment of a minimum circuit;

FIG. 22 shows a graph that illustrates the operation of the minimum circuit shown in FIG. 21;

FIG. 23 show a maximum circuit;

FIG. 24 shows a graph illustrates the operation of the maximum circuit shown in FIG. 23;

FIG. 25 shows one embodiment of a detector;

FIG. 26 shows a graph that illustrates the operation of the detector of FIG. 25;

FIG. 27 shows a graph that illustrates the operation of the detector of FIG. 25;

FIG. 28 shows one embodiment of a circuit that replicates the linear detector of FIG. 25 and provides a temperature compensated reference;

FIG. 29 shows another embodiment of a detector based on MOS technology;

FIG. 30 shows one embodiment of a transconductance amplifier; and

FIG. 31 shows a graph that illustrates the operation of the transconductance amplifier shown in FIG. 30.

DETAILED DESCRIPTION

FIG. 1 shows a block diagram of a radio transmitter. It includes an RF modulator, synthesizer, variable gain amplifier (VGA), and power amplifier (PA). The RF modulator up-converts a message signal to an RF carrier signal created by the synthesizer, which then drives the variable gain amplifier and power amplifier to produce a transmit signal. With this architecture, both the variable gain amplifier and the power amplifier need to operate linearly with high efficiency.

It's important that the power amplifier and each gain stage operate linearly at the peaks of the transmit signal. This situation places the greatest demands on the power amplifier and actually defines its operating parameters as described below.

FIG. 2 shows a power amplifier gain stage. It includes input and output matching networks and uses an RF choke (inductor L₁) to allow the output voltage V_out to swing above the positive supply V₊. The output voltage swing is maximized when the optimum load resistance (R_opt) is presented to the gain stage and thus;

$R_{\mathrm{opt}}=\frac{2V_{+}}{I_{\max }}$ where I_max is the maximum collector current of transistor Q₁. The maximum current is important because, in practice, the active device (Q₁) should operate at a nominal level that is about one-half the maximum level to ensure linear operation.

FIG. 3 shows a graph that illustrates transistor output curves for the power amplifier shown in FIG. 2 when driven by a sinusoidal input waveform. At the nominal level, the output current flows continuously or nearly continuously. It follows that the loadline resistance (R_opt) and maximum current (I_max) are therefore defined by;

$R_{\mathrm{opt}}\frac{{\left(2V_{+}\right)}^2}{P_{\mathrm{out}\left(\mathrm{pk}\right)}}\mathrm{and}{I}_{\max }=\frac{2V_{+}}{R_{\mathrm{opt}}}$ where P_out(pk) is the instantaneous peak output power.

At lower power levels and smaller signal peaks, it's possible to reduce the nominal operating current of the active device. However, it's important to keep the loadline resistance fixed, otherwise the output match and performance of the power amplifier suffers.

The efficiency of an amplifier is defined as an amplifier's ability to convert dc (or battery) power to radio energy;

$\eta =\frac{P_{\mathrm{RF}}}{P_{\mathrm{dc}}}$ where P_RF is the RF output power and P_dc is the dc power used. The described linear amplifier—with continuous output current flow—achieves at best 50% efficiency. It's possible to lower the dc power used and thereby improve efficiency by limiting the time the output current flows.

FIG. 4 shows a graph that illustrates various operating nodes for an amplifier. For example, the graph shows how efficiency may be improved by limiting the time the output current flows in an amplifier. Here, the conduction angle—defined as twice the cutoff point of the waveform—indicates the amount of time the output current flows for a sinusoidal signal. It follows that the conduction angle is 2π for class A operation (current flows continuously), from π to 2π for class AB mode, exactly π for class B bias, and less than π for class C operation.

The operating point of RF amplifiers can also be affected by the input signal. This effect, known as self-bias, occurs at large input signal amplitudes. The large signal peaks exponentially increase the transistor's output current. This phenomenon potentially compensates for typical gain compression effects and therefore actually helps class AB amplifiers operate more linearly than class A amplifiers.

Class B and C amplifiers are generally labeled switched amplifiers since the active device is turned on and off. As a result, this type of amplifier is inherently nonlinear and therefore unsuitable for use with most digitally modulated signals. It is however very efficient. Furthermore, its efficiency remains almost constant at different output power levels. This contrasts with linear amplifiers, where the efficiency falls off dramatically at low to moderate power levels.

FIG. 5 shows a block diagram of a polar modulator. The overall efficiency of the radio transmitter improves when a polar modulation architecture is used. This type of architecture separates the message signal into equivalent phase and amplitude components, allowing direct phase modulation at the synthesizer 502 and amplitude modulation at the power amplifier 504 as shown in FIG. 5. It advantageously eliminates mixer circuits and enables the use of nonlinear and more efficient compressed amplifiers.

FIG. 6 shows a block diagram of a phase/frequency synthesizer 600 for use with a polar modulator. For example, the synthesizer 600 shown in FIG. 6 is suitable for use as the synthesizer 502 shown in FIG. 5. The synthesizer 600 comprises a phase modulator that utilizes a fractional-N phase-locked loop (PLL) and dual-port voltage-controlled oscillator (VCO). The separate VCO ports are used to set the RF carrier frequency and to inject phase/frequency modulation. This eases the design since their responses can be independently optimized. Since the frequency modulation is applied directly to the VCO, it's important for the modulation port to be very linear. It is also important to use a correction signal to offset feedback effects and thus to allow direct modulation.

The output of the synthesizer 600 at the VCO is a constant-envelop phase-modulated signal. Ideally, this signal is buffered using compressed amplifiers and then connected to the power amplifier, whereat amplitude modulation is applied. For example, the phase-modulated signal may be applied to the power amplifier 504 shown in FIG. 5. In practice, the amplitude modulation is applied either through the supply or via a bias network. Each approach has its own advantages and issues as described below.

FIG. 7 shows a diagram of an amplifier that provides amplitude modulation through the supply. The amplitude modulation is applied at the positive supply as shown in FIG. 7. Since the loadline resistance is fixed by the output matching network 702, the output power (P_out) simply becomes proportional to the supply voltage and is expressed as;

$P_{\mathrm{out}}=\frac{V_{\mathrm{am}}^2}{R_{\mathrm{opt}}}$ where V_am is the amplitude modulation (AM) signal. This relationship is extremely linear—even more so than the gain relationship of class A/AB amplifiers. Unfortunately, as the amplitude modulation voltage V_am is reduced, the gain stage and active device eventually saturate. This proves problematic for bipolar transistors (because it forward biases the base-collector junction which may harm the device) and for field effect transistors (since the device pushes into its linear region where its gain drops). Therefore the collector voltage for bipolar transistors and the drain voltage of field affect transistors must be limited. Severe phase shifts to the signal also occur near saturation and must be avoided because these produce spectral re-growth. As a result, the useful range for this type of amplitude modulation is approximately 20 dB.

FIG. 8 shows a diagram of an amplifier that supports amplitude modulation through a bias network. For example, amplitude modulation is introduced through the amplifier's bias network 802, and this affects its linear gain. This is partly because the small-signal gain of a bipolar transistor (g_m) tracks its collector bias current (I_CQ); although, at larger signal levels other effects such as gain compression and self-bias take over. As such, the gain of an amplifier stage depends on both the bias current and the input signal amplitude—which becomes a complex relationship at large signal levels. Nevertheless, bias control supports an amplitude modulation range of approximately 20 dB.

Some modern communication systems such as CDMA and OFDM bundle multiple carriers together to deliver high data rates. This tends to increase the fluctuations in the transmit signal and generally produces very large peaks. As a result, the dynamic range of the amplitude modulation signal can reach 40 dB.

It's clear that amplitude modulation by a single stage amplifier—either through the supply or bias network—falls short of the requirements set by modern communication systems. This problem becomes even more acute when adaptive power control needs are considered. That's because the ideal point for amplitude modulation changes. At high output power levels, the amplitude modulation is best applied at the last stages of the power amplifier. In this way, the preceding gain stages can operate nonlinearly and thus very efficiently. As the output power of the radio transmitter decreases, the ability to apply amplitude modulation through the last power amplifier stage disappears. This is because an amplifier possesses an absolute lower limit to its modulation range (due to saturation and phase linearity) as well as it generally offers very little control at low power levels. Consequently, the amplitude modulation must shift to earlier gain stages and this further complicates the situation.

The amplitude modulation shift impacts both switched (FIG. 7) and linear (FIG. 8) power amplifiers. For switched amplifiers at high power levels, the input drive must be strong enough to fully switch the amplifier. In contrast, at low power levels, the input signal must be small enough to allow the switched amplifier to operate linearly. For linear amplifiers, the situation is somewhat different. At high power levels, the power amplifier is self-biased and as such the bias network is unable to affect the amplifier's gain. This means the input power must decrease initially (before the amplifier's gain is adjusted) and must continually shrink as the amplifier's gain is reduced. Otherwise, the amplifier will distort the input signal. Regardless of the approach, amplitude modulation must be linear. This dictates a system with calibration and/or feedback.

FIG. 9 shows one embodiment of a polar modulator with system calibration for improved amplitude modulation. The system calibration comprises a mapping function (MAP) that maps an amplitude modulation signal to control signals having the appropriate values needed to linearly control one or more power amplifier gain stages. The mapping function introduces pre-distortion and supports open-loop operation. But, the mapping function differs for each power amplifier and therefore utilizes several measurements. Effects from temperature and frequency should also be minimized.

FIG. 10 shows another embodiment of a polar modulator that comprises a feedback circuit for improved amplitude modulation. The feedback circuit provides a feedback loop that creates closed-loop control of the output power level. As such, the amplitude modulation signal(s) are corrected to drive the output signal to the proper amplitude. This feedback loop becomes challenging for wide dynamic range systems and even more complicated for elaborate systems needing phase/amplitude tracking.

In one embodiment, the feedback circuit operates to provide a feedback loop that operates around a group comprising the high-power amplifier stages, since these stages are difficult to predict (sensitive to input signal amplitude, supply voltage, and bias current). This requires the response of the variable gain amplifier(s) to be linear or at least very predictable, which is practical with variable attenuators and current-steered variable gain amplifiers.

FIG. 11 shows one embodiment of an amplitude modulation architecture that comprises a feedback loop. The feedback loop comprises a detector (DET), signal processing circuit, a pair of low pass filters (LPF) (1102, 1104), a bias circuit (Bias), and a summing circuit (+). The feedback loop operates to generate control signals that are used to control the operation of a VGA and power amplifier. The detector operates over the gain control range of the amplifier stages enclosed by the feedback loop. In practice, it is the detector range that limits the maximum control range of the power amplifier. The amplitude modulation drives two points—one which sets the input level to the power amplifier by controlling the VGA, and a second which controls the power amplifier. In essence, the processing circuit split the amplitude modulation signal (AM) into the two control signals (VGA* and PA*). In one or more embodiments, the feedback loop operates with either of the amplitude modulation approaches discussed above—supply or bias.

In one embodiment, the signal processing circuit actually slides the amplitude modulation, depending on the transmit output power level set by the TX control signal. The processing circuit also considers two important power levels that describe the power amplifier. The first level (P₁) indicates the power level where the control through the supply or bias network becomes practical. It's related to the amplifier's design and varies with the peak-to-average ratio of the transmit waveform, which is readily available from the digital modulator using the radio configuration parameters or by means of some straightforward analysis. (Note that P₁ is the maximum output power level for the switched amplifier, but somewhat less for the linear amplifier due to self-bias effects.) The second level (P₂) marks the absolute lower limit of the power amplifier's modulation range;P₂=P_MAX−ΔP₂ where P_MAX identifies the maximum output power level and ΔP₂ corresponds to the detector range.

FIG. 12 a shows one embodiment of a processing circuit 1200 suitable for use in the amplitude modulation architecture shown in FIG. 11. The processing circuit 1200 uses minimum (min) and maximum (max) functions to properly steer and scale the amplitude modulation signal (AM). These functions limit both the low and high ends of the AM signal routed to the power amplifier control signal (PA*). Its minimum threshold is P₂—TX while its maximum threshold is P₁−TX. As a result the PA* control signal is defined as;

${\mathrm{PA}}^{*}=\{\begin{array}{c}{P}_2\mathrm{for}AM<\left(P_2-\mathrm{TX}\right)\\ \mathrm{AM}+\mathrm{TX}\mathrm{for}\left(P_2-\mathrm{TX}\right)\ge AM\le \left(P_1-\mathrm{TX}\right)\\ P_1\mathrm{for}AM>\left(P_1-\mathrm{TX}\right)\end{array}$ which essentially describes the AM signal in the range of P₁ to P₂.

The min and max functions also scale the AM signal to produce the variable gain amplifier control signal (VGA*). The VGA* control signal primarily covers the range outside of P₁ to P₂, but it also affects the range from P₁ to P₂. In this region, it varies the input signal to the power amplifier by using a scaled version of the PA* signal, resulting in;

${\mathrm{VGA}}^{*}=\{\begin{array}{c}\mathrm{AM}\mathrm{for}\mathrm{AM}<\left(P_2-\mathrm{TX}\right)\\ P_2+\mu \left({\mathrm{PA}}^{*}\right)\mathrm{for}\left(P_2-\mathrm{TX}\right)\ge \mathrm{AM}\le \left(P_1-\mathrm{TX}\right)\\ P_2+\mu \left({\Delta P}_2\right)+\left(\mathrm{AM}-P_1\right)\mathrm{for}\mathrm{AM}>\left(P_1-\mathrm{TX}\right)\end{array}$ where μ is the scaling factor. It's possible that the scaling factor better fits a logarithmic function whereby the VGA* signal becomes;μ(PA*)→(PA*)^μIn either case, the scaling factor μ is always less than one.

It should be noted that the processing circuit 1200 use the same limits for splitting the AM signal to the VGA* and PA* control signals. As such, it reduces any discontinuities in the transfer functions for these control signals as illustrated in the graph of FIG. 12b. These responses in turn produce the PA* and VGA* control signals shown in FIG. 12c. FIG. 12d shows an AM signal and resulting PA and VGA output signals.

The amplitude feedback loop also includes a low pass filter to ensure stability as well as to further attenuate the RF carrier signal that leaks through the peak detector. Its design is important because the phase and amplitude signals in a polar modulator must align, otherwise the modulated signal becomes distorted and spectral re-growth occurs as shown in the graph provided in FIG. 13. The signals plotted in FIG. 13 show the power spectral density (psd) of an ideal modulation signal, and a signal produced when the modulation signals (frequency and amplitude) are offset in time by a small amount.

Referring to the feedback loop shown in FIG. 11, its operation can be described by the following transfer function;

$\frac{i_{\det }}{i_{\mathrm{AM}}}=\frac{\frac{k}{\left(1+s/p_1\right)}}{1+\frac{\alpha k}{\left(1+s/p_1\right)\left(1+s/p_2\right)}}$ where k is the power amplifier control gain, α is the detector gain, and p₁-p₂ are the pole frequencies of the low pass filter 1104 and detector filter, respectively. The power amplifier gain is set by the control current (i_PA) and is defined by;

$k=\frac{v_{\mathrm{rf}\left(\mathrm{pk}\right)}}{i_{\mathrm{PA}}}$ where v_rf(pk) is the peak transmit signal, less any coupling loss. Likewise, the detector is characterized by;

$\alpha =\frac{i_{\det }}{v_{\mathrm{rf}\left(\mathrm{pk}\right)}}$ which is a linear relationship. Note that the pole frequency p₂ of the detector (and any other circuit) is intentionally set much higher than the pole frequency p₁ of the low pass filter. As a result, the transfer function for the feedback loop simplifies to;

$\frac{i_{\det }}{i_{\mathrm{AM}}}=\frac{\beta }{1+\frac{s}{p_1\left(1+\alpha k\right)}}$ where β is the dc gain equal to;

$\beta =\frac{k}{1+\alpha k}$ and p₁(1+αk) is the effective or dominant pole frequency of the system. With these conditions, the low pass filter not only stabilizes the feedback loop but also removes the carrier signal extracted by the detector. Furthermore, this effective pole frequency sets the delay of the amplitude modulation signal.

The feedback loop is active only between power levels P₁ to P₂. This is important because the detector is linear only in this range. Outside this range, the detector, the feedback loop, and the power amplifier become very nonlinear. Therefore, in one embodiment, the limit functions restrict and actually prevent the operation of the feedback loop outside the range of P₁ to P₂.

FIG. 14 shows one embodiment of a system for aligning the phase and amplitude signals in a polar modulator. The digital phase and amplitude input signals are captured by latches (L) and then applied to digital-to-analog (D/A) converters. In practice, the amplitude modulation must be delayed one-half cycle compared to the frequency modulation signal to realize the VCO phase shift. The latches align the digital data and thereby remove any prior or existing timing differences. In one embodiment, the phase modulation signal—in analog form—is filtered and then applied directly to the voltage-controlled oscillator (VCO) operating at the carrier frequency. This generates a constant-envelope phase-modulated signal that is then buffered by the variable gain driver (VGA). The delay of these circuits t_D can be approximated by;

$t_D\sim \frac{1}{2.5f_{3\mathrm{dB}}}$ where the 3 dB bandwidth (f_{3 dB}) is necessarily greater than the carrier frequency. This results in an insignificant delay compared to the rate of the amplitude modulation signal. Simultaneously, the amplitude modulation signal (in analog form) is also applied to the analog signal processing circuit and power amplifier control loop.

Now, to align the modulation signals, the phase modulation signal must be delayed by the same amount as the amplitude modulation signal. In one embodiment, a duplicate low pass filter 1402 is inserted in the phase modulation path prior to the voltage-controlled oscillator. Its transfer function is simply;

$\frac{v_{\mathrm{out}}}{i_{\mathrm{in}}}=\frac{1}{\left(1+s/p_3\right)}$ where p₃ represents the pole frequency and equals p₁ (1+αfl ). This also corresponds to the pole frequency for the low pass filter 1404 connecting to the variable gain amplifier since it operates outside the feedback loop.

Some communication systems use modulation schemes with exceptionally wide frequency modulation as shown in the graphs illustrated in FIG. 15. (It's possible in some cases for the bandwidth of the frequency modulation to approach several times the bandwidth of the transmit signal.) This wide bandwidth causes problems and makes the design of the feedback loop difficult. Interestingly, the bandwidth of the amplitude modulation signal generally follows the spectrum of the transmit signal. As a result, the design of the feedback loop may be eased by setting the pole frequency of the amplitude and frequency modulation paths differently. The challenge then becomes alignment of the phase and amplitude modulation signals.

FIG. 16 shows one embodiment of a system for aligning the phase and amplitude signals in a polar modulator that comprises a digital delay circuit 1602 that allows the timing of the frequency modulation signal to be adjusted. It's expected that the narrower bandwidth of the amplitude feedback loop introduces additional delay that needs to and can be compensated for by the delay element 1602.

FIG. 17 shows one embodiment of a system for aligning the phase and amplitude signals in a polar modulator that comprises a digital delay circuit that uses a phase equalization filter 1702 before the VCO to exactly match the delay of the filter in the amplitude feedback loop.

FIGS. 18 a-d show graphs that illustrate the operation of one embodiment of a method to compensate for the effects of a narrow filter. For example, systems with narrow filters that attenuate the modulation signals generally need compensation or pre-distortion. That's because these filters severely limit the nulls in the modulation signal as shown in the graph of FIG. 18a. The nulls occur when the signal trajectory abruptly passes through the I/Q origin and thus maps to higher frequencies. It's possible to counteract this effect by advancing the signal as shown in the graph of FIG. 18b, and then shifting the signal towards zero as shown in the graph of FIG. 18c. The resulting signal can also be rescaled to recover any lost signal amplitude. This advantageously reduces spectral re-growth as illustrated by the graph shown in FIG. 18d.

The feedback loop and processing circuit shown in FIG. 11 utilize a variety of functions to split and/or process the amplitude modulation signal. These functions can be realized as digital and/or analog circuits. Any digital implementation is generally straightforward while an analog implementation is more challenging as described below. The first of these circuits is an exponential generator (EXP), which translates the TX control signal (typically in dB) to linear format.

FIG. 19 shows one embodiment of an EXP circuit and FIG. 20 shows a graph of its operation. Referring to FIG. 19, a current I₁ develops a base-emitter voltage across transistor Q₁ that mirrors to transistor Q₂ through resistor R₁. The resulting loop equation is;V_be1=I_TxR₁+V_be2 where I_Tx is the power control signal (and is proportional to the required gain). This equation can be rewritten as;

$I_{\exp }=I_1\exp \left(-\frac{I_{\mathrm{Tx}}{R}_1}{V_T}\right)$ where V_T is the thermal voltage. FIG. 20 illustrates the resulting exponential current (I_exp).

Referring again to FIG. 19, the transistor loop comprising devices Q₃-Q₄ and transistors P₁-P₂, biases transistor Q₁, while transistor N₁ provides the base current for transistor Q₂. Resistor R₂ provides a current source for transistor N₁.

By design, the exponential current I_exp maps to the same scale as the amplitude modulation signal and above-defined power levels P₁ and P₂. This is important because it allows the signals to be easily compared by the min and max circuits described above.

FIG. 21 shows one embodiment of a minimum (min) circuit. It prevents the input current from falling below the current I_min. A set of three current mirrors establishes current I_in in transistor N₂ and current I_min in transistors N₄ and P₂. The diode D₁ remains biased off until the current I_in exceeds the current I_min, at which point, the excess current I_in-I_min flows through the diode D₁ from the output. As a result, the output current I_out follows the current I_in at high levels but flattens out (to the level of I_min) at low levels of current I_in as shown in the graph provided in FIG. 22.

FIG. 23 shows one embodiment of a maximum (max) circuit. It limits the output current to a maximum level equal to the current I_max. A current mirror establishes the current I_in in devices N₂ and N₃. A similar current mirror (transistors P₁-P₂) sets the current I_max. The diode D₁ provides a path for the excess current when current I_max is larger than current I_in and sets the voltage at the non-inverting input to the operational amplifier (plus the voltage at the drain of transistor N₃). When the current I_in exceeds the current I_max, transistor N₂ is pushed into triode region to limit its current to I_max. The operational amplifier forces the voltage at the drain of transistor N₃ to follow the voltage at the drain of transistor N₂ so that transistor N₃ also limits to the current I_max. Degeneration resistors are added to the NMOS current mirrors (devices N₁-N₃) to increase the sensitivity of the network as the drain-source voltage decreases (in triode region). As a result, the output current I_out equals the input current I_in to a maximum level of I_max, where it flattens out as shown in a graph provided in FIG. 24.

Referring again to FIG. 11, the detector (DET) is a ver) important functional element in the feedback loop. Ideally, it provides a linear response and thereby follows the envelope of the transmit output signal.

FIG. 25 shows one embodiment of a detector. Transistor Q₁ rectifies the input signal according to;

$i_{C1}=I_{S1}\exp \left(\frac{v_{\mathrm{rf}}+V_B-v_{\det }}{V_T}\right)$ where i_C1 and I_S1 are the collector and saturation currents of the transistor, respectively, v_rf is the input signal with amplitude A, V_B is the base bias voltage, and v_det is the output voltage developed across capacitor C₁. The peaks of the input signal are held by capacitor C₁, although some droop Δv occurs between these peaks, with;

${\Delta v}_{\det }=-\frac{I_1}{C_1}\Delta t$

I₁ is the bias current, and Δt is approximately one-half of the carrier (or radio) frequency. Some droop is acceptable, since the envelope of the radio frequency signal changes slowly compared to the carrier signal. The circuit strives for equilibrium where the average current flowing through transistor Q₁ is simply I₁. This requires the voltage held by capacitor C₁ to track the positive peaks (and effectively the envelope) of the radio signal as shown in the graph provided by FIG. 26. As a result, the detector responds linearly to input signals over a range of about 20 dB and adheres to the expression;

$v_{\det }=A+V_B-V_{\mathrm{beq}}+V_T\ln \sqrt{\frac{2\pi A}{V_T}}$ as shown in the graph provided by FIG. 27. Ideally, the bias voltage V_B shown in FIG. 25 cancels the quiescent base-emitter voltage of transistor Q₁. Alternatively, FIG. 28 shows one embodiment of a circuit that replicates the linear detector and provides a temperature compensated reference (V_ref). FIG. 29 shows another embodiment of a detector based on MOS technology.

The detector output voltage may be translated to an output current so that it readily interfaces to the processing circuits described herein. FIG. 30 shows one embodiment of a transconductance amplifier that operates to translate the detector output voltage to an output current. For example, the circuits shown in FIG. 25 and FIG. 28 feed the transconductance amplifier shown in FIG. 30. Transistor. Q₃ and Q₄, resistor R₃, and current sources I₃ and I₄ form a linear differential gain stage with output currents described by;i₃=I₃+i_det i₄=I₄−i_det where i₃ and i₄ are the collector currents of transistors Q₃ and Q₄, respectively. The current i_det is described by;

$i_{\det }=\frac{v_{\det }-V_{\mathrm{ref}}}{R_3}$ for v_det less than or equal to I₄R₃.

Transistors Q₃ and Q₄ with current source I₅ form a simple differential pair where

$i_5=\frac{I_5}{1+\exp \left(\frac{V_{\mathrm{ref}}-v_{\det }}{V_T}\right)}{i}_6=\frac{I_5}{1+\exp \left(\frac{v_{\det }-V_{\mathrm{ref}}}{V_T}\right)}$ which is cross-coupled to the previous outputs (i₃ and i₄). Since current source I₅ is significantly smaller than current sources I₃ and I₄, the cross-coupled currents actually reduce the transconductance amplifier's gain at low input levels. This in turn effectively reduces the offset produced by the detector and extends its range beyond 30 dB to approximately 35 dB as illustrated by the graph shown in FIG. 31. In other embodiments, it is also possible to use MOS transistors to realize the transconductance amplifier.

In one or more embodiments, a system for linear amplitude modulation is provided that improves the efficiency of power amplifiers that can be used for various types of modulated signals, including constant and envelope-varying schemes. The system utilizes a feedback loop to linearize the response of these power amplifiers as well as an advanced gain control system to scale the amplitude modulation. The result is a robust and very efficient amplitude modulation system that may be used in radio transmitters or any other system or application that requires linear amplitude modulation.

Accordingly, while one or more embodiments of a system for linear amplitude modulation have been illustrated and described herein, it will be appreciated that various changes can be made to the embodiments without departing from their spirit or essential characteristics. Therefore, the disclosures and descriptions herein are intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.

Claims

1. Apparatus for linear amplitude modulation of a multi-stage amplifier, the apparatus comprising: a processing circuit that receives an amplitude modulation signal and a transmit control signal and produces at a first output a first amplifier control signal to control a first stage of the multi-stage amplifier and at a second output a second amplifier control signal to control a second stage of the multi-stage amplifier;a detector circuit coupled to the output of the multi-stage amplifier to generate, at an output, a signal representing the output of the multi-stage amplifier;a summing circuit having a first input coupled to the second output of the processing circuit to receive the second amplifier control signal and a second input coupled to the output of the detector circuit; anda network coupled to an output of the summing circuit to controls a bias or a gain signal of the multi-stage amplifier to linearize the amplifier's amplitude control.

2. The Apparatus of claim 1 further comprising a first lowpass filter coupled to the first output of the processing circuit and a first stage of the multi-stage amplifier.

3. The Apparatus of claim 2 wherein the first stage is a VGA stage.

4. The Apparatus of claim 1 wherein the network comprises a lowpass filter and a bias circuit, wherein the lowpass filter is coupled to the output of the summing circuit and an input of the bias circuit and wherein an output of the bias circuit is coupled to a second stage of the multi-stage amplifier.

5. The Apparatus of claim 4 wherein the second stage of the multi-stage amplifier comprises a power amplifier stage.

6. The Apparatus of claim 1 wherein the processing circuit comprises a plurality of min and max circuits configured to generate the first amplifier control signal and the second amplifier control signal.

7. The Apparatus of claim 6 wherein the first amplifier control signal is designated VGA* and the second amplifier control signal is designated PA*, with VGA* generated in accordance with a relationship governed by: VGA*=AM for AM<(P2−TX);VGA*=P2+u(PA*) for (P2−TX)>=AM<=(P1−TX); andVGA*=P2+u(Delta P2)+(AM−P1) for AM>(P1−TX); andwherein AM is a signal proportional to the amplitude modulation signal, P1 is a power level at which amplifier control through the bias network or voltage supply may be effected, P2 is the absolute lower limit of the amplifier's modulation range, u is a scaling factor, and TX is the transmit output power level set by the transmit control signal.

8. The Apparatus of claim 6 wherein the second amplifier control signal is designated PA*, with PA* generated in accordance with a relationship governed by: PA*=P2 for AM<(P2−TX)PA*=AM+TX for (P2−TX)>=AM<=(P1−TX); andPA*=P1 for AM>(P1−TX); andwherein AM is a signal proportional to the amplitude modulation signal, P1 is a power level at which amplifier control through the bias network or voltage supply may be effected, P2 is the absolute lower limit of the amplifier's modulation range, and TX is the transmit output power level set by the transmit control signal.

9. The Apparatus of claim 1 further comprising: a duplicate lowpass filter coupled between a phase or frequency modulated input signal and a VCO coupled to the multi-stage amplifier, wherein the network comprises a lowpass filter, and wherein said duplicate lowpass filter is configured to match a set of filter characteristics of the lowpass filter.

10. The Apparatus of claim 1 further comprising: an alignment circuit coupled to an input AM signal, an input PM or FM signal, the processing circuit and a VCO coupled to the multi-stage amplifier, wherein said amplitude alignment circuit is configured to delay the input AM signal or input PM or FM signal to compensate for time delays in the AM or PM or FM signal paths.

11. The Apparatus of claim 10 wherein the alignment circuit comprises a delay circuit configured to adjust the timing of the PM or FM signal.

12. The Apparatus of claim 11 wherein the delay circuit comprises a digital delay circuit.

13. The Apparatus of claim 10 wherein the alignment circuit comprises a digital delay circuit including a phase equalization filter coupled to the VCO and the FM or PM signal to match the delay of a filter in the network.

14. The Apparatus of claim 10 wherein the alignment circuit is configured to compensate for narrowband AM distortion.

15. The Apparatus of claim 14 wherein the alignment circuit is configured to compensate for narrowband AM distortion by: receiving an original AM signal;advancing the original AM signal; andshifting the advanced signal towards a zero value to generate a compensated AM signal.

16. The Apparatus of claim 15 wherein the alignment circuit is further configured to rescale the compensated AM signal to approximate the original AM signal amplitude.

17. The Apparatus of claim 1 wherein the detector circuit is configured to provide a linear response signal to follow the envelope of the multi-stage amplifier output signal.

18. The Apparatus of claim 17 wherein the detector comprises: an input capacitor coupled to a voltage signal, said voltage signal replicating the multi-stage amplifier output signal;a resistor coupled to the capacitor and a bias voltage signal;a transistor coupled to the input capacitor and resistor;a diode coupled to the transistor; andan output capacitor coupled to the transistor and diode to hold the peaks of the voltage signal.

19. The Apparatus of claim 18 wherein the transistor comprises a bipolar junction transistor (BJT).

20. The Apparatus of claim 18 wherein the transistor comprises a field effect transistor (FET).

21. The Apparatus of claim 17 further comprising a temperature compensated reference.

22. The Apparatus of claim 17 further comprising a transconductance circuit coupled to the detector circuit to translate a detector output voltage to an output current.

23. A method for amplitude modulating a multi-stage amplifier, comprising: receiving, at a processing circuit, an amplitude modulation signal and a transmit control signal;providing a first output from the processing circuit to a first stage of the multi-stage amplifier to selectively amplitude modulate the first stage;providing a second output from the processing circuit to a summing circuit;combining, in the summing circuit, the second output with an output of a detector circuit coupled to an output of the multi-stage amplifier to generate a summing circuit output; andproviding the summing circuit output to a network and the second stage to selectively amplitude modulate the second stage;wherein the first output signal is designated VGA* and the second amplifier control signal is designated PA*, with VGA* generated in accordance with a relationship governed by: VGA*=AM for AM<(P2−TX);VGA*=P2+u(PA*) for (P2−TX)>=AM<=(P1−TX); andVGA*=P2+u(Delta P2)+(AM−P1) for AM>(P1−TX); andwherein AM is a signal proportional to the amplitude modulation signal, P1 is a power level at which amplifier control through the bias network or voltage supply may be effected, P2 is the absolute lower limit of the amplifier's modulation range, u is a scaling factor, and TX is the transmit output power level set by the transmit control signal.

24. The method of claim 23 further comprising aligning the amplitude modulation signal with a corresponding PM or FM signal to compensate for time delays in the AM or FM or PM signal paths.

25. The method of claim 24 wherein said aligning is performed by a delay circuit configured to delay the PM or FM signal.

26. The method of claim 25 further comprising applying the FM or PM signal to a phase equalization filter coupled to the VCO to match the delay of a filter in the network.

27. The method of claim 24 wherein said aligning is performed to compensate for narrowband AM distortion.

28. The method of claim 27 wherein the aligning includes: receiving an original amplitude modulation signal;advancing the original amplitude modulation signal to generate an advanced AM signal; andshifting the advanced AM signal towards a zero value to generate a compensated AM signal.

29. The method of claim 28 wherein the aligning further includes rescaling the compensated AM signal to approximate the original AM signal amplitude.

30. The method of claim 23 wherein the detector circuit provides an output as a linear response signal generated to follow the envelope of the multi-stage amplifier output signal.

31. The method of claim 30 further comprising providing, in the detector circuit, a temperature compensated reference.

32. The method of claim 23 further comprising translating the detector output from a voltage to a current, and providing the current to the summing circuit.

33. A method for amplitude modulating a multi-stage amplifier, comprising: receiving, at a processing circuit, an amplitude modulation signal and a transmit control signal;providing a first output from the processing circuit to a first stage of the multi-stage amplifier to selectively amplitude modulate the first stage;providing a second output from the processing circuit to a summing circuit;combining, in the summing circuit, the second output with an output of a detector circuit coupled to an output of the multi-stage amplifier to generate a summing circuit output; andproviding the summing circuit output to a network and the second stage to selectively amplitude modulate the second stage;wherein the second output signal is designated PA*, with PA* generated in accordance with a relationship governed by: PA*=P2 for AM<(P2−TX)PA*=AM+TX for (P2−TX)>=AM<=(P1−TX); andPA*=P1 for AM>(P1−TX); andwherein AM is a signal proportional to the amplitude modulation signal, P1 is a power level at which amplifier control through the bias network or voltage supply may be effected, P2 is the absolute lower limit of the amplifier's modulation range, and TX is the transmit output power level set by the transmit control signal.

34. The method of claim 33 further comprising aligning the amplitude modulation signal with a corresponding PM or FM signal to compensate for time delays in the AM or FM or PM signal paths.

35. The method of claim 34 wherein said aligning is performed by a delay circuit configured to delay the PM or FM signal.

36. The method of claim 35 further comprising applying the FM or PM signal to a phase equalization filter coupled to the VCO to match the delay of a filter in the network.

37. The method of claim 34 wherein said aligning is performed to compensate for narrowband AM distortion.

38. The method of claim 37 wherein the aligning includes: receiving an original amplitude modulation signal;advancing the original amplitude modulation signal to generate an advanced AM signal; andshifting the advanced AM signal towards a zero value to generate a compensated AM signal.

39. The method of claim 38 wherein the aligning further includes rescaling the compensated AM signal to approximate the original AM signal amplitude.

40. The method of claim 33 wherein the detector circuit provides an output as a linear response signal generated to follow the envelope of the multi-stage amplifier output signal.

41. The method of claim 40 further comprising providing, in the detector circuit, a temperature compensated reference.

42. The method of claim 33 further comprising translating the detector output from a voltage to a current, and providing the current to the summing circuit.