Claims
- 1. A method for converting a program designed to be executed on a computer system employing a first memory order to a program which is executable on a computer system employing a second memory order, the second memory order being the reverse of the first memory order, the method comprising the steps of:
- (a) finding all instructions in the program which operate on bytes of data, each of said bytes of data having a byte address, each byte address having two least significant bits;
- (b) combining the two least significant bits of each byte address with binary three using an exclusive-OR logic function, thereby generating two complementary bits for each byte address; and
- (c) replacing the two least significant bits of each byte address with the two complementary bits, thereby generating a new byte address for each of said bytes of data.
- 2. The method of claim 1 further comprising the step of detecting whether the program is designed to be executed on a computer system employing the first memory order.
- 3. The method of claim 2 further comprising the step of detecting the two least significant bits of each byte address.
- 4. The method of claim 1 wherein the first memory order comprises big endian order, and the second memory order comprises little endian order.
- 5. The method of claim 1 wherein the first memory order comprises little endian order, and the second memory order comprises big endian order.
- 6. A computer system employing a first memory order which converts and executes programs designed to be executed on computer systems employing a second memory order, the second memory order being the reverse of the first memory order, comprising:
- means for finding all instructions in the program which operate on bytes of data, each of said bytes of data having a byte address, each byte address having two least significant bits;
- means for combining the two least significant bits of each byte address with binary three, using an exclusive-OR logic function, thereby generating two complementary bits for each byte address; and
- means for replacing the two least significant bits of each byte address with the two complementary bits, thereby generating a new byte address for each of said bytes of data.
- 7. The computer system of claim 2 further comprising:
- means for detecting whether the program is designed to be executed on a computer system employing a second memory order; and
- means for detecting the two least significant bits of each byte address.
- 8. The computer system of claim 2 wherein the first memory order comprises bit endian order, and the second memory order comprises little endian order.
- 9. The computer system of claim 2 wherein the first memory order comprises little endian order, and the second memory order comprises big endian order.
Parent Case Info
This is a continuation of application Ser. No. 07/564,923, filed Aug. 9, 1990, now abandoned.
US Referenced Citations (14)
Non-Patent Literature Citations (2)
Entry |
Kirrman; "Data Format and Bus Compatibility in Multiprocessors"; IEEE Micro Aug. 1983, pp. 32-47. |
David V. James; "Multiplexed Buses; The Erdian Wars Continue"; IEEE Jun. 1990 pp. 9-20. |
Continuations (1)
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Number |
Date |
Country |
Parent |
564923 |
Aug 1990 |
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