System for resolving velocity ambiguity in pulse-doppler radar

BACKGROUND OF THE INVENTION
This invention relates to coherent pulse-doppler tracking radar, and more particularly to a system for resolving the ambiguity in target velocity estimates made from doppler shift measurements.
The concept of pulse transmission has been basic to most tracking radar systems because range can be easily measured by the time delay of each pulse round trip. Information as to the relative radial velocity of the target is determined by measuring the doppler frequency shift between transmitted and reflected waves of each pulse, and information as to the angular coordinates of the target is determined by relating received energy properties to the sensitivity and directivity patterns of the antenna.
A relative high pulse repetition frequency (PRF) is commonly employed to provide unambiguous velocity (doppler shift) determination, but range is then usually ambiguous. To resolve the range ambiguity, it is common practice to use a staggered PRF, i.e., to alternate the period of the radar pulse cycle. Both range and doppler shift can then be tracked without ambiguity. However, it is often desirable to use a medium PRF, namely a PRF that is not sufficiently high in relation to the largest expected values of doppler-shift for velocity to be tracked unambiguously. If doppler shift cannot be unambiguously tracked, the target's velocity relative to the velocity of the aircraft carrying the radar system cannot be determined except by the range tracking loop, i.e., by effectively taking the first derivative of range measurements. Doppler-shift measurements provide more accurate determination of velocity. Moreover, the determination can be made on the basis of the most recent radar return alone. The problem is to provide a radar tracking system with the facility for resolving the ambiguity in velocity.
A typical tracking system in a tactical aircraft performs two principle functions. First, it positions the antenna and the range and velocity gates of the radar signal processor, so as to keep the target accurately centered within the "field of view" of those elements. Second, it generates estimates of the target's position and motion for use in fire-control and aircraft-steering computations. These functions must be accurately performed over an extremely broad range of operating conditions, ranging from highly dynamic dog-fight encounters at short-range to very low signal-to-noise ratios at long range.
Several factors must be dealt with in the design of the tracking system in order to obtain the required accuracies and performance capabilities. First, there is the problem of measurement errors due to factors such as noise, target scintillation, and radome refraction. Maneuvers of the target and deception techniques (countermeasures) employed by targets to prevent tracking are the second class of problems which must be dealt with.
Due to the large variations in the characteristics and magnitudes of these error sources over the wide spectrum of operating conditions, variable parameter filters are necessary to meet tracking accuracy requirements of high performance aircraft. For example, narrow bandwidth filtering is required for tracking targets at long range with low signal-to-noise ratios. But rapid response is necessary for tracking highly maneuverable targets at short range. These factors, plus the requirement for generating high accuracy estimates of target line-of-sight (LOS) rates, and the desirability of employing one unified set of general filter equations to handle any radar mode --high PRF, medium PRF, low PRF, and so forth-- have led to the use of a new approach in the design of the tracking filter using Kalman filtering.
A system employing this new approach is like a typical radar tracking system in that a target reflects pulses to an antenna which analyses the return pulses and provides the desired information. A transmitter and receiver is operated in accordance with a predetermined mode in regard to frequency and PRF, both of which are often selected automatically or by an operator for a particular target to avoid velocity and range blind zones. The receiver provides video signals to a radar signal processor which produces signals that are measurements of range, range rate (radial velocity) and angular coordinates (elevation and azimuth deflection) of the target. These measurement signals are then applied to standard antenna controllers for positioning the antenna and to range and velocity controllers for positioning range and velocity gates. A typical radar tracking is thus a multiple closed-loop feedback system. Two loops for tracking in azimuth and elevation, and two loops for tracking in range and velocity. Standard servomechanism design procedures are both applicable and practical to each of these loops, but optimal results are not always achieved by such procedures.
The difference between this new approach and the prior art is that the prior art tracking loops have employed classical single control loops, using low-pass filtering to remove noise from measurement signals, whereas the new approach employs more advanced control loops employing filters for estimating quantities from measured differences between estimates and actual measurements, such as .DELTA.R.sub.m = R - R.sub.m. The timing of a range gate, R.sub.G, represents the range estimate, R, and the time of arrival of a round-trip radar pulse represents the measured range, R.sub.m. The difference then is the discriminant, .DELTA.R.sub.m. The range servo-loop continually updates the range estimate R to drive .DELTA.R.sub.m toward zero. Analogous servomechanism procedures drive the velocity discriminant, V.sub.m, toward zero and the azimuth and elevation discriminants, .DELTA..eta..sub.m and .DELTA..epsilon..sub.m, toward zero.
In accordance with this new approach, an airborne system is provided with electromagnetic energy sensors for tracking moving targets is some or all of range, radial velocity, elevation and azimuth. Energy received from the system sensors is processed to develop signals representing actual discriminants of range, .DELTA.R.sub.m, radial velocity, .DELTA.V.sub.m, elevation, .DELTA..epsilon..sub.m, and azimuth, .DELTA..eta..sub.m. These measurements are used to generate predictions of the next measurements from current estimates of system states, where the states are vectors X.sub.R (i), X.sub.V (i), X.sub.e (i) and X.sub.d (i), using for each state an equation of the general form
X.sub.i.sub.+l = .phi..sub.i X.sub.i + L.sub.i + K.sub.i (Y.sub.i - H.sub.i X.sub.i) (1)
where X is a state vector, .phi. is a transition matrix, L is a vector of dynamical aiding terms to compensate for rotational rates and inertial acceleration of the antenna, K is a gain factor, Y is the output of a measurement structure for the dynamical system and H is a system scaling factor which accounts for the gain in the measurement structure. The four channels implemented in accordance with this general equation are cross-coupled by using outputs of one or more channels as parameters in the remaining channels. For the range channel
R.sub.TPR X.sub.R = V.sub.TPR a.sub.TPR
thus generating estimates of predicted target range, R.sub.TPR, radial velocity, V.sub.TPR, and radial acceleration, a.sub.TPR. For the velocity (doppler) channel
V.sub.TPV X.sub.V = a.sub.TPV
thus generating estimates of predicted doppler velocity V.sub.TPV and acceleration a.sub.TPV. For the antenna angle channels
.epsilon..sub.Pe .epsilon..sub.Pd .omega..sub.LSPe .omega..sub.LSPdX.sub.e = a.sub.Td X.sub.d = a.sub.Te S.sub.e S.sub.d
thus generating estimates of pointing errors, .epsilon..sub.e,d, target line-of-sight rates, .omega..sub.LSPe,d, target accelerations normal to the line of sight, a.sub.Td,e, and target angular scintillation, S.sub.e,d, all referenced directly to antenna coordinates. The pointing error estimates, .epsilon..sub.Pe and .epsilon..sub.Pd, and the target line-of-sight rates .omega..sub.LSPe and .omega..sub.LSPd are used to produce antenna elevation and azimuth commands .omega..sub.Ce and .omega..sub.Cd. The range estimate R.sub.TPR and the velocity estimate V.sub.TPV are used to produce a range gate command, R.sub.GC, and a velocity gate command, V.sub.GC, both to be used by a radar controller.
In operation of the tracking system, measurements of SNR are made coincidentally with the discriminant measurements. The discriminant noise variance and the discriminant slope are then determined from the measured SNR, and these quantities are utilized in the calculations of the filter gains. Thus, the filter is provided with data on discriminant used by the filter, thereby adapting the filter to the characteristics of each measurement sample.
SUMMARY OF THE INVENTION
In accordance with the present invention, a coherent radar tracking system is provided with separate range and velocity (doppler) tracking filters implemented in accordance with the iterative equation
X.sub.i.sub.+1 = .phi..sub.i X.sub.i + L.sub.i + K.sub.i [Y.sub.i -H.sub.i X.sub.i]
where X is the estimate of range or velocity, .phi. is a transition matrix, L is a vector of dynamical aiding terms to compensate for rotational rates and inertial acceleration of the radar antenna, K is a gain factor, Y is the measurement structure for the dynamical system, and H is a system scaling factor which accounts for gain in the measurement structure. A bar over a symbol indicates a matrix quantity or value used in the filter for the parameter represented by the symbol, and the subscript i indicates a value at a given time i. The subscript i+1 then indicates an estimate of X at the next iteration time. The states of the range filter are
R.sub.TPRX.sub.R = V.sub.TPR a.sub.TPR
where R.sub.TPR is the estimated (predicted) range of the target and the remaining states V.sub.TPR and a .sub.TPR are effectively the respective first and second derivatives of R.sub.TPR. The states of the velocity filter are
V.sub.TPVX.sub.V = a.sub.TPV
where V.sub.TPV is the estimated (predicted) velocity of the target and the remaining state is effectively the first derivative of V.sub.TPV. The velocity state V.sub.TPV is derived ambiguously from doppler shift of the signal return from radar pulses transmitted at a medium PRF, but the state V.sub.TPR is unambiguous once ambiguity in range, R.sub.TPR, is resolved at the time the target is acquired for tracking using conventional techniques. Ambiguity is then resolved in the state V.sub.TPV when uncertainty in range channel velocity estimate, V.sub.TPR, is less than .lambda.PRF/4, i.e., when the difference between the actual doppler shift, f.sub.DP, derived from the unambiguous velocity, V.sub.TPR, and the ambiguous doppler shift, f.sub.DAP, derived from the ambiguous velocity, V.sub.TPV, is less than PRF/2. At that time, a corrected velocity V.sub.TCORR is computed in accordance with the following equation
V.sub.TCORR = .lambda./2 PRF {[(f.sub.MLC +f.sub.DAP -f.sub.DP) PRF.sup..sup.-1 +1/2]*-(f.sub.DAP +f.sub.MLC)}
where the asterisk by the bracketed quantity indicates that the quotient (f.sub.MLC +f.sub.DAP -f.sub.DP) .div. PRF is to be truncated by dropping the fractional part after the quotient has been rounded out by adding 1/2 to the quotient. The truncated number N is the number of spectra from a reference frequency f.sub.o in which the doppler shift of the target return should be. The quantity f.sub.MLC is an offset of the reference introduced to avoid main lobe clutter in the center of the doppler shift spectrum where the target is most likely to be, and is predetermined as a function of ground speed of the intercepting aircraft and elevation angle of the radar antenna. The actual doppler shift velocity, V.sub.TCORR, is thus computed by multiplying PRF by N, subtracting the sum of f.sub.DAP and f.sub.MLC and converting the difference to feet per second by multiplying by half the wavelength, .lambda., of the radar frequency in feet per second (half because of the round trip path of the returned signal). V.sub.TCORR is then used to reinitialize the velocity filter during the next filter cycle by substituting V.sub.TCORR for V.sub.TPV that one time. Thereafter, the velocity filter tracks V.sub.TPV accurately and unambiguously.

BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram illustrating an airborne radar monopulse tracking system embodying the present invention.
FIG. 2 is a general block diagram of the general form of the filters for each of the four filter channels in an estimator for the elevation, azimuth, range and velocity tracking system of FIG. 1.
FIGS. 3a through 3d are block diagrams of the four filter channels for tracking in elevation, azimuth, range and velocity, wherein each filter represented by a block is of the form illustrated in FIG. 2.
FIGS. 4, 5 and 6 illustrate typical range discriminant characteristics.
FIG. 7 is a timing diagram of tracking filter functions.
FIGS. 8a-8d illustrate a functional flow diagram for a programmed tracking filter routine.
FIGS. 9a -9f illustrate a detailed flow diagram for the routine of FIGS. 8a-8d.
FIGS. 10-18 illustrate flow diagrams of programs for subroutines called out in detailed flow diagrams of FIGS. 9a-9f.
FIGS. 19 and 20a-20d illustrate flow diagrams for azimuth and elevation command computations.
FIGS. 21a and 21b illustrate the techinque employed for computing signal-to-noise ratios for use in the flow diagrams of FIGS. 9a-9f.
FIG. 22 is a block of a digital computer employed as a radar data processor (RDP) in the system of FIG. 1.
FIG. 23 illustrates the storage allocation assignments for the RDP of FIG. 22.
FIG. 24 illustrates schematically the working registers of the RDP of FIG. 22.
FIG. 25 illustrates instruction formats for the RDP of FIG. 22.
FIG. 26 is a diagram useful in understanding how velocity ambiguity is resolved.
FIG. 27 is a flow chart of a routine for resolving velocity ambiguity.

DESCRIPTION OF THE PREFERRED EMBODIMENT
Before proceeding with a detailed description of a preferred embodiment, a typical environment for the present invention will be described with reference to FIGS. 1 through 3.
In the most general terms for describing the environment, means are provided for iteratively computing a prediction Xt.sub.(i.sub.+1) of the next measurement sample Yt.sub.(i.sub.+1) from the difference (residual) between a current estimate Xt.sub.(i) and measurement Yt.sub.(i) of a tracking system state. The residual is multiplied by a gain factor Kt.sub.(i) and the product is improved by available external aiding signals Lt.sub.(i), such as for compensation of antenna motion and/or aircraft motion as they affect tracking. Means for extrapolating the next estimate Xt.sub.(i.sub.+1) from the current estimate Xt.sub.(i) and the measurement residual is provided as a minor loop in the residual loop. The two loops constitute a tracking filter.
In the foregoing, t.sub.(i.sub.+1) denotes the time of the updated measurement and t.sub.(i) denotes the time of the previous measurement. For convenience, the letter t will be omitted hereinafter and only the subscripts i and i+1 will be used to denote the times.
The extrapolation loop is a dynamic model, .phi..sub.i, of the system state aided by the available external aiding signals, L.sub.i. The general filter structure is then defined by equation (1) set forth hereinbefore in the summary of the invention. In operation, the estimates are generated by adding measurement corrections K.sub.i [Y.sub.i - H.sub.i X.sub.i ] to extropolated values .phi..sub.i X.sub.i of past estimates improved by an aiding term L.sub.i. Thus, in the absence or rejection of a measurement, extrapolation is automatically performed until the next measurement is obtained, thereby tracking through blind regions. Correlation between the measurement residuals and the errors in estimated states is important to the present invention. Such correlation can arise in one of two possible ways -- direct measurement correlation or indirect dynamical correlation.
Direct measurement correlation exists between a given measurement and a given state if the measurement is itself a measure of the particular state. For example, the azimuth and elevation measurement residuals of the radar are direct measurements of the angular pointing errors, and are, therefore, directly correlated with the computational estimates of angular pointing error. Dynamical correlation arises from dynamical coupling between quantities which are directly measured and quantities which are estimated. As an example, extrapolation of the angular position of the target is performed by integrating the estimate of the target's line-of-sight (LOS) rate. Thus, any errors in the estimated LOS rate will produce errors in the extrapolated angular position, thereby resulting in a correlation between the angular position error and the LOS rate error.
Means is provided for an estimated state to be updated by any measurement which is correlated -- either directly or dynamically -- with that state. Thus, in the preceding example, since the angle measurement residuals are directly correlated with angular position error, and since angular position error is dynamically correlated with LOS rate error, the angle measurement residuals are correlated with LOS rate errors and can therefore be used to reduce LOS rate errors. In that manner, a single measurement quantity may be employed to generate estimates of several system states. Each estimated state is updated by the measurement residual weighted by a particular gain factor associated with that state. To obtain the greatest accuracy, the value of each gain factor is continually made proportional to the statistical correlation between the measurement residual and the uncertainty in the particular estimate, and inversely proportional to the variance of the measurement error. This is the form of the optimal gain for a continuous-time computational means; a slight modification is necessary in the case of discrete-time computational means. The real-time calculations of the gain factors are performed as follows: The statistical (ensemble) cross-correlations between the measurement residual and the estimation uncertainties, or errors, are computed by appropriate means in terms of the measurement model and the covariance matrix of the estimation errors, which is recomputed by appropriate means in a recursive manner once each computational cycle. The covariance matrix takes into account cross-correlation between the system states due to dynamical interactions between the states.
The tracking system is divided into the following channels:
1. Azimuth angle channel
2. Elevation angle channel
3. Range channel
4. Velocity channel
These four channels are cross-coupled to obtain the benefits of cross-channel aiding. The azimuth and elevation angle channels have Kalman filter configurations and are identical in form, each estimating the following set of four state variables: (1) pointing error, (2) line-of-sight rate, (3) target acceleration normal to the line-of-sight, and (4) angular scintillation. Each of these states is referenced directly to antenna coordinates. Both of the angle channels use the same set of gain factors, which are computed and updated once each computational cycle. Measured values of signal-to-noise ratios are used in the calculation of the filter gain factors, thereby enabling the computational means to adapt to changing signal characteristics.
The range and velocity channels also have Kalman filter configurations, but employ semi-fixed instead of time-varying gains. Both of these channels employ three sets of gains, which are selected as a function of measured signal-to-noise ratio. Range signal-to-noise ratio (SNR.sub.RNG) is used to select the appropriate set of gains for the range channels, and velocity signal-to-noise ratio (SNR.sub.VEL) is used to select the appropriate set of gains for the velocity channels. In different PRF modes, the range channel processes the measurement residuals to form estimates of target range, range rate and radial acceleration. In a high PRF mode, where no range residuals are measured and where it is unnecessary to control range rate positions, the range channel consists of a single state, the target range state, and velocity aiding is provided by the velocity channel.
In high and medium PRF modes, the velocity channel processes velocity measurement residuals to form estimates of range rate and radial acceleration. The velocity channel is not employed in low PRF mode. The angular rate commands for the antenna are obtained by passing the pointing error estimate through a compensator and adding the line-of-sight rate estimate to the compensator output. The use of the accurate line-of-sight rate estimates in the antenna commands results in a substantial reduction of both dynamical and steady-state antenna pointing errors. The fact that the estimates are generated in antenna coordinates permits the antenna commands to be generated simply and directly from the estimates without any coordinate transformation.
Although each of the four channels could function independently of one another, better performance is obtained by cross coupling. The form of the channel filters permits this cross coupling to be implemented very easily. Thus, range and range rate estimates from the range and velocity channels, respectively, are used in the angle channels, and the line-of-sight rate estimates of the angle channels can be used in the range and velocity channels. In addition, roll cross coupling is provided between the two angle channels.
Each of the four tracking loops is aided by inertial navigator outputs to compensate for aircraft accelerations. However, the loops can also function in the absence of inertial navigator aiding. A unique form of aiding, utilizing gyro outputs in addition to gyro torque commands, is employed to compensate for antenna motion.
The system also employs special timing techniques which permit sufficient time to process the radar data while avoiding dynamical problems which might otherwise result from the delays between the time of measurement and the time of generating the commands required for closed-loop tracking. These techniques include pre-averaging of the radar measurements together with one-step extrapolation of the estimates in the angle channels, and two-step extrapolation in the range and velocity channels.
At the initiation of tracking, and until the tracking channels can acquire sufficient data with which to accurately track the motion of the target, the tracking loops are iterated at a fast rate in order to avoid losing the target. Thereafter, a slow rate of iteration may be employed. However, fast iteration cannot be performed if channel gain factors are to be computed due to time required for the computations. Therefore, in an initial tracking phase of predetermined duration (.about. 1.5 sec.) after initial lock-on, constant preprogrammed gain factors are used to permit the tracking loops to iterate at fast rates. Thereafter, the gain factors used are computed to provide adaptive tracking loops.
FIG. 1 illustrates an exemplary amplitude-comparison monopulse airborne radar tracking system embodying the present invention. Four antenna horns A, B, C and D are located symmetrically around the antenna axis 10, and are fed in phase by a conventional transmitter-receiver 11 to produce a narrow beam along the axis. Transmitted pulses are timed by a conventional controller 12. Between transmitted pulses, received energy is coupled to three channels of a receiver portion of the radar receiver-transmitter. An in-phase or sum channel (A+B+C+D) permits reception of fullamplitude echo signals for use in display, ranging, radial velocity tracking and as a reference signal for angle tracking. An azimuth error channel, (A+C)-(B+D), and an elevation error channel, (A+B)-(C+D) permit angle tracking. The coupling duplexers (not shown) are conventional.
The radar controller transmits range and velocity gates R.sub.G and V.sub.G to a signal processor 13. There the received sum channel is sampled to produce range and velocity discriminants .DELTA.R.sub.m and .DELTA.V.sub.m, while at the same time the difference channels are sampled to produce azimuth and elevation discriminants, .DELTA..eta..sub.m and .DELTA..epsilon..sub.m. For ranging, two samples are taken, one on each side of the predicted peak of a return pulse, to develop the range discriminant. For velocity tracking, two samples are also taken, one on each side of the predicted doppler shift to develop the velocity discriminant. The signal processor also provides measurements of signal and noise to a signal-to-noise ratio computer 13a which computes for range, velocity, elevation and azimuth the respective ratios SNR.sub.RNG, SNR.sub.VEL, SNR.sub.e and SNR.sub.d as required for use by an estimator 14.
The outputs of the signal processor 13 and SNR computer 13a are in digital form, and are used in an estimator 14 for developing an estimate of target range R.sub.TPR, an estimate of radial velocity (range rate of target) V.sub.TPV, azimuth and elevation line-of-sight rate estimates .omega..sub.LSPd and .omega..sub.LSPe, and azimuth and elevation tracking error estimates .epsilon..sub.P and .epsilon..sub.P . These angle estimates are used in an azimuth and elevation command computer 15 to produce control signals for an antenna servo 17, thus closing a servo loop through the dynamical system. The range and velocity estimates are used in a range and velocity command computer 16 to produce control signals for the radar controller 12 which produces range and velocity gates R.sub.G and V.sub.C, to close range and velocity tracking loops.
Timing for the sections 13, 13a, 14, 15 and 16, which collectively constitute a digital radar data processor, is provided by a clock pulse system that is based on a very stable high frequency clock pulse source in a conventional manner. The estimator 14 operates on a fixed cycle of a period selected for the mode of radar operation, namely high, medium or low PRF. In each mode, the cycle period is greater than the sampling period in the signal processor. In order to utilize the information contained in the intervening samples, a preaveraging system 18 implemented as part of the radar data processor, accumulates the intervening samples and divides by the number of samples taken to provide average discriminant inputs to the estimator. Assuming the discriminant values are in binary form, averaging may consist of simply adding 2.sup.N samples, where N is a whole integer, and dividing by 2.sup.N by effectively shifting down N places at the end of every 2.sup.N samples. The accumulator is reset after every 2.sup.N samples.
State vectors of the four Kalman filter channels in the estimator may be used for purposes other than tracking, such as in a display and fire control system 19. Each of the four tracking loops is aided by outputs from an aircraft inertial navigation system 20 which produces signals representing pitch angle .theta., aircraft roll angle .phi..sub.I, aircraft heading angle .psi. and north, east, and vertical components of interceptor velocity, V.sub.N, V.sub.E and V.sub.D. The antenna servo 17 also provides input signals representing antenna roll gimbal angle .phi..sub.G, antenna elevation gimbal angle .epsilon..sub.G and antenna azimuth gimbal angle .eta..sub.G. These signals are all either in digital form or immediately converted to digital form, preferably the former.
Although each of the four tracking filters could function completely and independently, better performance is obtained by cross coupling the filters in particular ways. The form of the filters permits cross coupling to be easily implemented. Range (R.sub.TPR) and range-rate (V.sub.TPR) estimates from the range and velocity filters, respectively, are used in the angle filters, and the line-of-sight rate estimates .omega..sub.LSPd and .omega..sub.LSPe are used in the range and velocity filters. In addition roll cross coupling is provided between the two angle-tracking filters.
A general block diagram applicable to each of the four tracking filters in the system will now be described with reference to FIG. 2. A block 21 represents the dynamical system of a tracking channel, such as for elevation tracking. The differential equation in the block indicates the form of the discrete tracking system. Pursuing the example of the elevation channel, the dynamical system can be more accurately defined by the following continuous state equations
.epsilon..sub.e = .omega..sub.LSe - .omega..sub.Ae + .omega..sub.Ar .epsilon..sub.d (2) ##EQU1## Where: .epsilon..sub.e is the pointing error in elevation.
.omega..sub.LSe is the angular rate in elevation of the line-of-sight to the target.
.omega..sub.Ae is the angular rate of the antenna axis in elevation.
.omega..sub.Ar is the angular (roll) rate about the antenna axis.
.epsilon..sub.d is the pointing error in azimuth.
R is the slant range to the target.
a.sub.T.sbsb.d is the acceleration of the target in azimuth.
a.sub.I.sbsb.d is the acceleration of the interceptor (radar platform) in azimuth.
.omega..sub.LSd is the angular rate in azimuth of the line-of-sight to the target.
.tau..sub.T is the correlation time of target acceleration model.
w.sub.T is white noise driving target acceleration model.
S.sub.e is scintillation of the target in elevation.
.tau..sub.s is the correlation time of the angular scintillation process.
w.sub.s is the white noise driving angular scintillation model.
These continuous state equations (2)-(5) may be more conveniently set forth in matrix form by the following substitutions in the dynamical system equation (block 21 in FIG. 2).
______________________________________ .epsilon..sub.e .omega..sub.LSeX = a.sub.T.sbsb.d (6) S.sub.e 0 1 0 0 2 R 1 0 - 0 R RA = (7) 1 0 0 - 0 .tau..sub.T 1 0 0 0 - .tau..sub.s - .omega..sub.Ae + .omega..sub.Ar .epsilon..sub.d (8) a.sub.I.sbsb.dL = - + .omega..sub.Ar .omega..sub.LSd R 0 0 0 0w = w.sub.T (9) w.sub.s______________________________________
The value of X from the differential equation in block 21 is the input to measurement structure represented by a dotted line block 22 in FIG. 2, where H is a measurement system parameter by which the input signal X is multiplied. The multiplier is represented by a block 23. Noise in the measurement system is added to the signal HX to provide a model of measurements
Y.sub.i = HX + v (10)
where v is the noise added, as represented by the circle 24 in the measurement structure. The subscript i indicates the value of the measurement during a particular cycle of the filter shown within a dotted line block 25 in FIG. 2. The filter produces an estimate of the measurement X.sub.i, from which a predicted measurement Y.sub.i is produced by multiplication of the estimate X.sub.i by H.sub.i in block 26, where H is the system measurement parameter. The subscript i indicates the value of H at time i, thus implying that H is not a constant. A bar over a symbol indicates a matrix quantity or value used in the filter as the filter's version of the parameter represented by the symbol.
The predicted measurement is subtracted from the actual measurement in a subtractor represented by a circle 27 to form a measurement residual. That residual is multiplied by a filter gain K.sub.i in block 28. Aiding signals L.sub.i are added to the product through an adder 29 to compensate for antenna motion as sensed at antenna gimbals and aircraft motion as sensed by the inertial navigation system (INS). The output of the adder 29 is fed back through a unit delay operator 30. The feedback signal X.sub.i is then used in an extrapolator 31 to form the product .PHI..sub.i X.sub.i which is added to the next measurement residual while forming the next estimate X.sub.i.sub.+1. In that manner the predicted measurement can be continually extrapolated. The extrapolator loop equation is;
X.sub.i.sub.+1 = .PHI..sub.i X.sub.i + L.sub.i (11)
where X, .PHI. and L are vectors. Observing that Y.sub.i = H.sub.i X.sub.i from the measurement structure, the filter state equation is;
X.sub.i.sub.+1 = .PHI..sub.i X.sub.i + L.sub.i + K.sub.i (Y.sub. i -H.sub.i X.sub.i) (12)
where the filter gain is given by the equations
K.sub.i = .PHI..sub.i M.sub.i H.sub.i.sup.T (H.sub.i M.sub.i H.sub.i.sup.T +R.sub.i).sup.-1 (13)
M.sub.i.sub.+1 = (.PHI..sub.i -K.sub.i H.sub.1) M.sub.i .PHI..sub.i.sup.T + Q.sub.i (14)
and Q.sub.i is the covariance matrix of the noise driving the systems dynamical model and R.sub.i is the covariance matrix of the measurement noise. The superscript T denotes the transpose of the associated matrix, and is not an exponent.
For the elevation and azimuth channels, .PHI..sub.i is given by the equation
.PHI..sub.a.sbsb.i = I + A.sub.a.sbsb.i T + A.sub.a.sbsb.i.sup.2 T.sup.2 /2 (15)
where I is the identifying matrix, T is the filter cycle period and ##EQU2## The elevation and azimuth filter parameters are given the equations
H.sub.a.sbsb.i = [k.sub.a.sbsb.i 0 0 k.sub.a.sbsb.i ] (17)
R.sub.a.sbsb.i = .sigma..sub.a.sbsb.i.sup.2 (18) ##EQU3## and .DELTA.V.sub.di is compensation for the acceleration a.sub.I.sbsb.d of the interceptor along the azimuth axis; .theta..sub.r is compensation for roll cross-coupling due to antenna roll motion and .intg. .omega..sub.A.sbsb.e dt is compensation for antenna motion about the elevation axis.
In equations (17) and (18), k.sub.a.sbsb.i is the angle discriminant slope and .sigma..sub.a.sup.2 is the angle discriminant noise variance determined from signal-to-noise ratio (SNR). An SNR is determined for both the range (SNR.sub.RNG) and radial velocity (SNR.sub.VEL) measurements of discriminants, as well as elevation (SNR.sub.e) and azimuth (SNR.sub.d) measurements of discriminants, and ideally each SNR would be used in the respective filters. However, as will be noted more fully hereinafter, the SNR is very nearly the same in both elevation and azimuth so that an average SNR can be used with sufficient accuracy in both angle filters. Another possibility is to compute the angle discriminant slope separately for the two angle filters from SNR.sub.e and SNR.sub.d and to use an average of those values in computing the gain factor K.sub.a.sbsb.i to be used in both angle channels. The average SNR of the angle filters is used to determine the discriminant noise variance to be used in both channels. This alternative is the one adopted for the specific exemplary embodiment to be described because of the desire to minimize computing time without significantly degrading performance. Thus, separate measurements of SNR.sub.e and SNR.sub.d are made by the signal processor 13 (FIG. 1) during each filter channel period while the discriminant measurements are being made. The angle discriminant noise variance, .sigma..sub.a.sbsb.i.sup.2, and the angle discriminant slope, k.sub.a.sbsb.i, are then computed as the average values for the elevation and azimuth channels. In the specific exemplary embodiment to be described, they are computed according to the following equations:
k.sub.a.sbsb.i = 1/2 (k.sub.e.sbsb.i + k.sub.d.sbsb.i) (23)
where k.sub.e and k.sub.d are predetermined functions of SNR.sub.e and SNR.sub.d, respectively.
.sigma..sub.a.sup.2 = C.sub.o for SNR.sub.a < 1 (24a) ##EQU4## where C.sub.o is a predetermined constant and SNR.sub.a = 1/2(SNR.sub.e +SNR.sub.d).
For the range and velocity filter channels, sets of predetermined constant gain factors, K.sub.r and K.sub.v, are selected based on SNR.sub.RNG and SNR.sub.VEL to reduce computation time in the specific exemplary embodiment to be described. However, for the present, it is assumed that each of the range and filter channels are fully implemented in a manner analogous to the implementation of each of the angle filter channels.
The value .DELTA.V.sub.di in Equations (21) and (22) is computed from INS velocities with transformation of those velocities to the antenna coordinate system. Assuming the transformation, .DELTA.V.sub.di is computed from the equation
.DELTA.V.sub.di = V.sub.di - V.sub.d(i.sub.-1) (25)
and the value .theta..sub.r is computed from the equation ##EQU5## where all symbols are as defined hereinbefore except .eta..sub.G = time derivative of azimuth gyro angle .eta..sub.G.
.omega..sub.a.sbsb.d = antenna inertial rate about azimuth, d, axis.
.epsilon..sub.G = elevation gyro angle.
.omega..sub.RG = angular rate of the aircraft roll gimbal.
The quantity in the curly brackets is a measurable expression for .omega..sub.A.sbsb.r, and .theta..sub.r is mechanized by measuring each of these quantities separately and combining as shown. Note that if a rate gyro were mounted on the r axis of the antenna, its output would directly measure .omega..sub.A.sbsb.r.
From the foregoing, it is evident that the full elevation channel equation is
X.sub.e(i.sub.+1) = .PHI..sub.ai X.sub.ei + L.sub.ei + K.sub.ai .DELTA.e (27a)
where the residual .DELTA.e = Y.sub.ei - H.sub.ai X.sub.ei - k.sub.a.sbsb.i r.sub.e.sbsb.i, and
.epsilon..sub.ei .omega..sub.LSeiX.sub.ei = , a.sub.Tdi S.sub.ei
The computed radome compensations r.sub.ei and r.sub.di are determined as a function of gimbal angle. The full azimuth (deflection) channel equation is
X.sub.d(i.sub.+1) = .PHI..sub.ai X.sub.d (i) + L.sub.di + K.sub.ai .DELTA.d (27b)
where the residual .DELTA.d = Y.sub.di -H.sub.ai X.sub.di - k.sub.ai r.sub.di, and
.epsilon..sub.di .omega..sub.LSdiX.sub.di = a.sub.Tei S.sub.di
In both angle channels, the filter input, Y.sub.i, is the average of discriminants over the ith measurement interval. The measurement residual is then the difference between the input Y.sub.i and the predicted measurement Y.sub.i = X.sub.i H.sub.i. Roll cross-coupling between channels is provided between the two angle filters.
In the range filter, the continuous system Equation (1) evolves into the following discrete equivalent
X.sub.r(i.sub.+1) = .PHI..sub.ri X.sub.ri + L.sub.ri + K.sub.ri [Y.sub.ri -H.sub.ri (X.sub.ri -X.sub.Gi)] (28)
where:
Y.sub.ri = .DELTA.R.sub.mi
X.sub.Gi = R.sub.Gi
R.sub.iX.sub.ri = V.sub.ri a.sub.Tri
.PHI..sub.ri = I + A.sub.ri T + A.sub.ri.sup.2 T.sup.2 /2 ##EQU6## where .DELTA.V.sub.ri is the change in interceptor (own ship) velocity along the radar boresight axis, and ##EQU7## where in practice .omega..sub.LSi.sup.2 may be substituted by a constant set to approximate the square of the line-of-sight rate.
By replacing X.sub.ri with V.sub.vi, Y.sub.ri with .DELTA.V.sub.mi, and X.sub.Gi with V.sub.Gi, the continuous system equation for the velocity filter evolves, where ##EQU8## The discriminant .DELTA.V.sub.mi is the average for the ith cycle of radial velocity determined by measuring doppler shift. The parameters used in .PHI..sub.ri, L.sub.ri and N.sub.ri are analogous to the parameters of the range filter. The parameter H.sub.ri = [k.sub.ri 0 0 k.sub.ri ] contains the discriminant slope for range. The corresponding parameter H.sub.vi = [k.sub.vi 0 0 k.sub.vi ] for the velocity filter contains the discriminant slope for velocity. The parameters k.sub.ri and k.sub.vi have the same form as the parameter k.sub.ai for the angle filters, as noted hereinbefore, and are stored in read only memories 48 and 49 for retreival as functions of SNR.sub.RNG and SNR.sub.VEL, respectively.
Referring to the general Equation (1), the last term is the measurement residual Y.sub.i - H.sub.i X.sub.i. The measurement residual is seen to be the actual measurement Y.sub.i minus the computed estimate or predicted measurement H X.sub.i. In the case of the angle filters, the measured discriminant Y.sub.i is the deviation of the antenna axis from the line-of-sight, i.e., the pointing error .epsilon. in elevation or azimuth. Consequently, the estimate computed as a filter output for control of the antenna is, after scaling, in a form to be subtracted directly from the measured value Y.sub.i, i.e., H.sub.i X.sub.i is an estimate of the measured value Y.sub.i. Therefore, the direct difference is the desired measurement residual. This residual is analogous to an error signal in a conventional servo control loop.
In the range and velocity filters, the measured discriminator outputs .DELTA.R.sub.m and .DELTA.V.sub.m are the difference between the respective slant range and radial velocity of the target and the anticipated range R.sub.G and velocity V.sub.G set by the radar controller from the estimates in range and velocity from the filters. It is therefore necessary to add R.sub.G -R and V.sub.G -V to the range and velocity discriminator outputs to form the measurement residuals. Consequently, in the range and velocity filters, the measurement residuals are given by the differences .DELTA.R.sub.mi - H.sub.ri (X.sub.ri - X.sub.rGi) and .DELTA.V.sub.mi - H.sub.vi (X.sub.vi - X.sub.vGi).
FIGS. 3a through 3d illustrate separately four filter channels 41, 42, 43 and 44 for the estimator 14 of FIG. 1 for elevation, azimuth, range and velocity, each with its separate controller, where the discriminants are
.DELTA..eta..sub.mi = Y.sub.di
.DELTA..epsilon..sub.mi = Y.sub.ei
.DELTA.R.sub.mi = Y.sub.ri
.DELTA.V.sub.mi = Y.sub.vi
The equations for the elevation and azimuth angle state vectors in an exemplary embodiment are ##EQU9## where all terms except .delta..sub.Re and .delta..sub.Rd are as defined hereinbefore. The constant C.sub.10 is a constant which appropriately scales the radar discriminant measurement. The terms .delta..sub.Re and .delta..sub.Rd are radome error corrections which can, for example, be computed or determined empirically for antenna gimbal angles and stored in a read-only memory 45 (FIG. 3a) for use in the elevation and azimuth angle filters to correct for refraction of electromagnetic energy by the radome for any position of the antenna during the ith iteration. These equations are used at all times for initial and final tracking at high, medium or low PRFs. However, for initial tracking some simplification may be achieved by omitting radome compensation.
The Kalman gain factor K.sub.ai is computed by iterating the following two equations, first the equation for M.sub.ai and then the equation for K.sub.ai.
M.sub.ai = [.PHI..sub.ai.sub.-1 - K.sub.ai.sub.-1 H.sub.ai.sub.-1 ] M.sub.ai.sub.-1 .PHI..sub.ai.sub.-1.sup.T + Q.sub.ai (31)
K.sub.ai = .PHI..sub.ai M.sub.ai H.sub.ai.sup. T . [H.sub.ai m.sub.ai H.sub.ai.sup. T + R.sub.ai ].sup..sup.-1 (32)
where all terms are as defined hereinbefore. The value H.sub.a is a matrix containing the angle discriminant slope k.sub.a, and R.sub.a is equal to the angle discriminant noise variance .sigma..sub.a.sup.2. The variables k.sub.a and .sigma..sub.a.sup.2 could be predetermined empirically as a function of SNR.sub..sub..SIGMA. = 1/2(SNR.sub.e + SNR.sub.d), and stored in a read-only memory for use in computing M.sub.ai and K.sub.ai. Computation of these equations is carried out by a block 46 (FIG. 3b) for both the elevation and the azimuth channels. This assumes the discriminant slopes k.sub.e for elevation and k.sub.d for azimuth are nearly the same to permit using an average k.sub.a = 1/2(k.sub.e + k.sub.d). In some systems, that may not be sufficiently true, in which case separate computations may be required for unique Kalman gain factors in each of the two angle filters.
As noted hereinbefore, there is cross-coupling between the angle filters in the aiding vectors L.sub.e and L.sub.d as reflected in Equation (8) for L.sub.e. The aiding vector L.sub.d is the exact symmetric version of the aiding vector L.sub.e. One need only substitute subscripts in Equation (8) to provide the equation for L.sub.d.
The system driving noise covariance matrix Q.sub.a set forth in Equation (19) can be simplified to the following form ##EQU10## where Q.sub.s and .alpha..sub.4 are single valued constants determined analytically or empirically, T is the filter iteration period, and the angular scintillation parameters .tau..sub.s and .tau..sub.s.sup.2 are updated when the Q.sub.a matrix is to be updated according to the following equations
.tau..sub.s = min {.alpha..sub.1, .alpha..sub.3 R.sub.TPR /.vertline.V.sub.TPV .vertline..sup.1/2 } (34a)
.tau..sub.s.sup.2 = .alpha..sub.2 / R.sub.TPR.sup.2 (35 b)
where .alpha..sub.1, .alpha..sub.2 and .alpha..sub.3 are single valued constants determined analytically or empirically. This matrix appears only in the angle filters and is the same for both azimuth and elevation. Its function is to reduce tracking error caused by angular scintillation, i.e., to estimate angular scintillation of the target.
The angle filter outputs to the azimuth and elevation command computers 15a,b are .omega..sub.LSP.sbsb.e .sbsb.d and .epsilon..sub.p.sbsb.e .sbsb.d as shown in FIGS. 3a,b. Note that for convenience, the subscripts i+1 have been omitted, it being understood that the outputs are for the time T.sub.i.sub.+1. The computers 15a,b calculate the antenna commands .omega..sub.c.sbsb.e and .omega..sub.c.sbsb.d as follows:
.omega..sub.c.sbsb.e (i.sub.+1) = .omega..sub.LSP.sbsb.e (i.sub.+1) + K.sub.2 . [l.sub.e (i.sub.+1) + a.sub.2 .epsilon..sub.P.sbsb.e (i.sub.+1) ] (36a)
.omega..sub.c.sbsb.d(i.sub.+1) = .omega..sub.LSP.sbsb.d (i.sub.+1) + K.sub.2 . [l.sub.d (i.sub.+1) + a.sub.2 .epsilon..sub.P.sbsb.d (i.sub.+1) ] (36b)
where K.sub.2 and a.sub.2 are single valued constants. Parameters l.sub.e and l.sub.d are intermediate antenna command variables computed in accordance with the following equations:
l.sub.e (i.sub.+1) = b.sub.2 l.sub.e (i) + c.sub.2 .epsilon..sub.P.sbsb.e .sbsb.i (37 a)
l.sub.d (i.sub.+1) = b.sub.2 l.sub.d(i) + c.sub.2 .epsilon..sub.P.sbsb.d .sbsb.i (37 b)
where b.sub.2 and c.sub.2 are single-valued constants. The l-parameters provide filtering (sloping) of the tracking errors .epsilon..sub.P.sbsb.e .sbsb.d. The computations provide for different selection of b.sub.2 and c.sub.2 during initial track and final track.
The computations of these Equations 36a and 36b consist of adding compensated elevation and azimuth LOS rate estimates to respective elevation and azimuth tracking errors to maintain angle tracking. The addition is represented in FIGS. 3a and 3b by an encircled summation symbol, .SIGMA.. The second term added to the tracking errors, the compensated LOS rate estimates, is formed by the indicated computation represented in FIGS. 3a and 3b by blocks becoming the legends COMP.sub.e and COMP.sub.d. As will be noted in an exemplary implementation (to be described hereinafter) of the present invention in the form of a digital radar data processor programmed to carry out the functions of at least sections 14, 15 and 16 of FIG. 1, the computation of Equations 37a and 37b is included in this angle tracking filter routine, rather than as part of an antenna control routine. That is done merely as a matter of convenience, to avoid having to store .epsilon..sub.P.sbsb.ei and .epsilon..sub.P.sbsb.di in a buffer during cycle i+1.
The equations for the range and velocity state vectors for blocks 43 and 44 of FIGS. 3c and 3d are ##EQU11## where R.sub.BIN is a scaling factor for converting .DELTA.R.sub.m into feet. ##EQU12## where f.sub.w is the filter band width for a radar frequency f=1/2 used to convert .DELTA.V.sub.m into feet per second. The superscripts and subscripts a in the range filter, and the superscripts and subscripts d in the velocity filter, indicate an initial track phase of a fixed time T.sub.j following acquisition of a target. In final track, which follows a fixed period of initial track, the superscripts and subscripts a and d are substituted by b and e, respectively. C.sub.g is a constant equal to 0 for initial track and to 1 for final track. The range and velocity gate command computations of the computer 16 are represented by blocks 16a and 16b in FIGS. 3c and 3d. In an exemplary embodiment, these computations (which will be described hereinafter) are carried out by a radar data processor, programmed as noted hereinbefore.
Referring first to just the range filter, computation of the transition matrix .PHI..sub.R.sbsb.a is as follows:
.PHI..sub.R.sbsb.a = I.sub.3 + IA.sub.Ra + 1/2T.sup.2 A.sub.Ra.sup.2 (40)
where I.sub.3 is a 3 .times. 3 identity matrix and A.sub.R.sbsb.a is the system dynamical matrix given by ##EQU13## C.sub.1 is a constant with one of two fixed values, depending upon target range at the time of entry into the initial track phase, and C.sub.2 is a single valued constant. These constants may be determined analytically or empirically.
For the initial phase, the operating filter period T is an integer multiple of the phase period T.sub.j, and the constant C.sub.9 is set equal to zero. That omits the dynamical aiding terms to simplify the range filter computations.
K.sub.1.sup.a, K.sub.2.sup.a and k.sub.3.sup.a are constants, each with one of three fixed values, depending upon one of three ranges (high, medium and low) of SNR.sub.RNG. At the time of entry into initial track, the middle Kalman gain K.sub.2.sup.a is used until the first valid SNR.sub.RNG measurement is made after entry.
A.sub.I.sbsb.r is the interceptor (own ship) acceleration about its r (roll) axis given by ##EQU14## where T.sub.1 denotes the time interval between the time of the updated motion compensation and the time of the last motion compensation, and .DELTA.V.sub.r is a velocity vector about the r axis computed from INS data in a manner to be described hereinafter.
In the final track phase, the constant C.sub.1 in the system dynamical matrix is replaced by a constant C.sub.3, a constant with one of two values depending upon target range. The resulting transition matrix .PHI..sub.R is then denoted .PHI..sub.R.sbsb.b. The time T is then the filter iteration period and the set of Kalman gain constants are replaced by K.sub.1.sup.b, K.sub.2.sup.b and K.sub.3.sup.b. The constant C.sub.9 is set equal to one to reinstate the dynamical aiding term.
Referring now to the velocity filter equation, the transition matrix .PHI..sub.R.sbsb.d is as fillows:
.PHI..sub.R.sbsb.d = I.sub.2 + TA.sub.R.sbsb.d + 1/2 T.sup.2 A.sub.R.sbsb.d (43)
where I.sub.2 is a 2 .times. 2 identity matrix and the system dynamical matrix A.sub.R.sbsb.d is given by ##EQU15## K.sub.2.sup.d and K.sub.3.sup.d are constants, each with one of three fixed values depending on SNR.sub.VEL as in the range filter. All other terms are as defined hereinbefore.
For final track in the velocity filter the constants K.sub.2.sup.d and K.sub.3.sup.d are replaced by constants K.sub.2.sup.e and K.sub.3.sup.e, each of which is again a set of three fixed values selected as a function of SNR.sub.VEL for every filter iteration. This provides a Kalman gain factor which is a function of SNR.sub.VEL, just as a Kalman gain factor is provided in the range filter as a function of SNR.sub.RNG.
The manner in which own-ship motion compensation calculations are made will now be described. Interceptor motion data including velocity components in the north (N), east (E) and down (D) coordinate system, and interceptor pitch (.theta.), roll (.phi..sub.I) and true heading (.psi.) are provided by the inertial navigation system (INS). A vector of first differences is then formed using the corresponding measurements taken approximately 0.2 second earlier: ##EQU16## where t.sub.i denotes the time of the updated measurement and t.sub.i.sub.-1 denotes the time of the previous velocity measurement used for motion compensation. Let T.sub.1 represent the time interval between these measurements, as noted hereinbefore. The INS and antenna angular motion data, (.theta., .phi..sub.1, .psi., .phi..sub.G, .epsilon., .eta.) measurements occur midway (.+-.5 m-sec) between the two times at which the above velocity first difference data are taken. The pitch, roll and true heading data from this intermediate measurement are used for motion compensation as shown below. The remaining data needed for this computation are: .epsilon. = antenna elevation gimbal angle; .eta. = antenna azimuth gimbal angle, and .phi..sub.G = antenna roll gimbal angle. Thus, all data for the tracking filter interceptor motion compensation will be available when the second velocity measurement is made. Coordinate transformation is used to obtain stabilized antenna coordinates .epsilon..sub.s, .eta..sub.s and .rho..sub.s from the above INS and antenna angular data. ##EQU17## Solving the above matrices will result in the following general equations.
.DELTA.V.sub.r = .DELTA.V.sub.N cos (.eta..sub.s + .psi.) cos .epsilon..sub.s + .DELTA. V.sub.E sin (.eta..sub.s + .psi.) cos .epsilon..sub.s - .DELTA.V.sub.D sin .epsilon..sub.s (50)
.DELTA.V.sub.e = .DELTA.V.sub.N [cos (.eta..sub.s + .psi.) sin .epsilon..sub.s sin .zeta..sub.s - sin .eta..sub.s cos .zeta..sub.s + .DELTA. V.sub.E cos (.eta..sub.s + .psi.) cos .zeta..sub.s + .DELTA.V.sub.D cos .eta..sub.s sin .zeta..sub.s (51)
.DELTA.V.sub.d = .DELTA.V.sub.N [cos(.eta..sub.s +.psi.) sin .epsilon..sub.s cos .zeta..sub.s + sin (.eta..sub.s +.psi.) sin .zeta. .sub.s ] - .DELTA.V.sub.E cos (.eta..sub.s +.psi.) sin .zeta..sub.s + .DELTA.V.sub.D cos .epsilon..sub.s cos .zeta..sub.s (52) The terms .DELTA.V.sub.e and .DELTA.V.sub.d are also used by the angle tracking filter channels.
To simplify other computations define: ##EQU18##
The manner in which SNR values are computed will be described, but first the following description will cover the manner in which they are used to determine the actual discriminant noise variances and actual discriminant slopes corresponding to each discriminant measurement utilized by the filters.
SNR data from the computer 13a are used to set the gains of the tracking filters. In both of the velocity and range filters, the gains available are quantized in initial track and final track, as just noted above. In the angle filters, the gains are continuous functions of SNR. Reasonably high SNRs are required for acceptable tracking. Initially the filters will be tracking (mostly extrapolating) at a relatively low SNR because the target will not be centered in the tracking gates. At low SNR levels, the current discriminant data is weighted by the filter gains lighter than under normal tracking because the return signal is weak relative to the noise in the signal.
Various techniques may be employed to compute the discriminants and the SNRs. By way of example, the range gate command, R.sub.GC, used to place the range gate at the predicted range bin of the target may be used to produce two adjacent range gates. The sign of a target signal from one gate is arbitrarily set negative, and the sign of a target signal from the other is set positive. The range discriminant is then essentially the algebraic sum of two range gated signals. The range tracking filter attempts to center the target between the adjacent gates. This type of tracker is referred to as the "split gate" type. To compute the SNRs, noise measurements are effectively made by averaging signal return in an equal number of range bins, or doppler filters, on each side of the gated range bins, or doppler filters, and subtracting that average from an average value of the two gated signal returns used to form the discriminants, taking into account noise present in the signal. The SNR's are then effectively computed as the ratio of the sum of the split gate signals used to compute the discriminants (less noise) and the noise thus measured. SNR measurements are averaged in the computer 13a over the same number of sampling cycles (typically four) as the preaveraging system 18 for the discriminants.
Split-gate tracking is used for all discriminants. For the velocity discriminants, the technique is directly analogous to that described for range. Two doppler filters are gated and the tracker attempts to maintain the target centered between the two filters. For the azimuth and elevation tracking, range-gated signals from the monopulse radar system are processed as the discriminants. The angle trackers attempt to maintain the target at the antenna axis by driving the antenna to a position such that (A+C)-(B+D) = 0 and (A+B)-(C+D) = 0. In that manner coherent subtraction of the left and right half of the antenna forms the azimuth discriminant, and the coherent subtraction of the upper and lower half of the antenna forms the elevation discriminant. Note that microwave plumbing on the back of the antenna does the coherent subtraction. Range and velocity discriminants are formed with only the sum channel signal (A+B+C+D).
In each case, the discriminant is a bipolar signal. In the noise free case, its magnitude is dependent on the tracking error as well as target signal magnitude which varies with range and size of target. To reduce the dependence on signal magnitude, the discriminants can be normalized by dividing by some function, f (M.sub.1, M.sub.2), of the target signal, where M.sub.1 and M.sub.2 are the signals used to form the discriminant. The present system uses the sum as follows: ##EQU19## Normalizing by dividing by the largest of M.sub.1 and M.sub.2 would give 50 percent better gain stability over SNR varying from 6 to 30 db, but that normalizing technique would only be possible in range and velocity tracking because in angle tracking M.sub.1 and M.sub.2 are not known separately, but their sum (M.sub.1 + M.sub.2) is known.
In the noise free case the normalized discriminant magnitude is dependent on the error, and its sign indicates the direction of the error. Receiver noise not only produces measurements with dispersion around where they would be in the noise free case, but actually causes the mean output to be lower. The mean suppression becomes greater with lower signal-to-noise ratio.
Typical range discriminant characteristics are shown in FIGS. 4, 5 and 6. FIG. 4 shows range discriminant means, i.e., the mean value of discriminants as a function of range error in bin widths for different SNR's of -5, 0, +7, +12 and +20 db. The standard deviations, .sigma., are shown in FIG. 5 for the same range errors and SNR's. FIG. 6 shows small signal discriminant slopes. These data can be determined analytically, but are preferably determined experimentally, for use in the selection of the gains in the filters. As noted hereinbefore, each filter can provide optimal tracking performance under instantaneous signal characteristics if provided data on the actual discriminant noise variances, .sigma..sub.i.sup.2, and actual discriminant slopes, k.sub.i, corresponding to each discriminant measurement, i.e., on a cycle by cycle basis. Once the data of FIGS. 4, 5 and 6 have been established, the noise variances and discriminant slopes can be determined during each filter cycle as a function of discriminants and SNR. The discriminant slope, k.sub.i, and the noise variance, .sigma..sub.i.sup.2, are used in the calculations of the Kalman gain, K.sub.i. This is, in theory, to be done in each filter during each cycle, but in practice it is fully done only in the angle tracking filters, and even in the angle filters an average discriminant slope k.sub.a.sbsb.i = 1/2 (K.sub.e.sbsb.i + K.sub.d.sbsb.i) and an average noise variance .sigma..sub.a.sbsb.i.sup.2 = 1/2 (.sigma..sub.e.sbsb.i.sup.2 + .sigma..sub.d.sbsb.i.sup.2) of the elevation (e) and azimuth (d) channels are used to calculate a Kalman gain, K.sub.a.sbsb.i, for use in both angle filters. That is done because the Kalman gain factor is an input to the calculations of the one step covariance matrix, M.sub.i, which is quite complex and would require too much time to compute separately for each channel. Instead an average covariance matrix, M.sub.a.sbsb.i, is computed for use in both filters using an average Kalman gain.
In the range and velocity filters, the computations are further simplified in the exemplary embodiment to be described hereinafter. That is done by simply providing three precalculated Kalman gain factors for selection based on SNR. The SNR used in each filter is ideally SNR.sub.RNG for range and SNR.sub.VEL for velocity, but in practice both SNR's may be assumed to be very nearly the same at all times, at least sufficiently so for the accuracy required in using just one SNR for precomputed Kalman gain factors in the range and velocity channels. Consequently, in the exemplary embodiment to be described, SNR.sub.RNG could be used to select the Kalman gains K.sub.r.sbsb.i and K.sub.v.sbsb.i for the range and velocity channels. The theory otherwise remains the same for all filters as described hereinbefore in general terms.
In an exemplary embodiment a digital radar data processor is programmed to implement all four filters. Consequently, the estimator 14 will now be described with reference to functional flow charts of a functional filter (FT) Routine in FIGS. 8a, 8b and 8c, and with reference to detailed flow charts of that routine in FIGS. 9a through 9f.
The FT Routine provides quantities necessary to maintain track. Specifically, the variables generated by FT and passed on to other routines to maintain track are listed below.
.epsilon..sub.p.sbsb.e -- Elevation tracking error estimate.
.omega..sub.LSP.sbsb.e -- Target elevation LOS rate estimate used to maintain elevation angle tracking.
.epsilon..sub.P.sbsb.d -- Azimuth tracking error estimate.
.omega..sub.LSP.sbsb.d -- Target azimuth LOS rate estimate used to maintain azimuth angle tracking.
R.sub.gc -- range gate command derived by radar controller from R.sub.TPR and used to generate the range gate R.sub.G.
V.sub.gc -- velocity gate command derived by radar controller from V.sub.TPV and used to generate the velocity gate V.sub.G.
To compute the quantities necessary to maintain angle tracking, FT implements a four-state Kalman filter for both the elevation and azimuth channels. The state vectors of the angle filters are:
.epsilon..sub.P.sbsb.eElevation tracking error estimate..omega..sub.LSP.sbsb.eTarget elevation LOS rate estimate.a.sub.TdTarget acceleration (inertial) estimate along antenna d-axis.S.sub.eElevation angular scintillation estimate..epsilon..sub.P.sbsb.dAzimuth tracking error estimate..omega..sub.LSP.sbsb.dTarget azimuth LOS rate estimate.a.sub.T.sub.-eTarget acceleration (inertial) estimate along antenna (-e) axis.S.sub.dAzimuth angular scintillation estimate.
To simplify the computational requirements, a single computation of Kalman gains is made for both channels by averaging the measurement characteristics of the two channels. (Note: The Kalman filter is implemented only in the Final Track Mode. In Initial Track Mode, the form of the filter is retained, but the gains are quasi-constants.)
To maintain range tracking, a three-state range filter is implemented. The state vector of the range filter is: ##EQU20##
To maintain velocity tracking, a two-state velocity filter is implemented. The state vector of the velocity filter is: ##EQU21##
The range and velocity filters are both implemented in the "Kalman form", but their gains are always selected on the basis of signal-to-noise ratios (SNR's). The measurement inputs to the angle filters are the respective angle discriminants. Because of electronic counter measures considerations, the range filter processes only the range discriminant; the velocity filter processes only the velocity discriminant. Thus, although the last two of the states in the range filter and the two states of the velocity filter mean the same thing, they are derived from different measurements and will, in general, be unequal.
The entries to the FT Routine are listed below:
Ft -- called by an executive routine (XT) provided that the discriminants associated with filter cycle (i) are completed before the FT call during filter cycle (+1) and FT must be completed before the AT call near the middle of filter cycle (i+1).
Ft1 -- called by XT to initialize non-zero value filter variables.
Fts1 -- called by FT for scintillation parameters.
Fts2 -- called by FT for the state transition matrix.
Fts3 -- called by FT for motion compensation.
Fts4 -- called by FT for radome compensation.
Fts5 -- called by FT for angle discriminant slopes and residuals.
Fts6 -- called by FT for Kalman gains and covariance update.
Fts7 -- called by FT for angle state vectors update.
Fts8 -- called by FT for own-ship acceleration in antenna coordinates.
The general nature of the track filtering process will be discussed first, with the aid of FIG. 7. The figure shows two adjacent filter cycles numbered, respectively, i and i+1, and portions of a third, i+2. The points i, i+1, etc., are to be considered the mid-points of their respective filter cycles. At the end of the FT computations for cycle i, the filter state vectors X.sub.e (i), X.sub.d (i), X.sub.R (i) and X.sub.V (i) (in the general case) have been computed with a time reference at the mid-point of cycle i. The FT variable for current filter cycle time, T, will equal T.sub.1. Assume that discriminant data .DELTA..epsilon..sub.m, .DELTA..eta..sub.m, .DELTA.V.sub.m and .DELTA.R.sub.m are being collected over cycle i.
If the period for filter cycle i+1 is different than that of cycle i, the Executive (XT) Routine will load the new filter period (T.sub.2 in the figure) in the FT variable T.sub.NEW before calling FT for cycle i+1. Also, output of the final discriminants must be completed before FT is called. Early in the FT computations for cycle i+1, the prediction interval from point i to i+1, 1/2(T+T.sub.NEW), is computed and stored in T. The new state vectors at i, using prediction equations with period T and augmented by the discriminant data gathered over i weighted by the filter gains. The range gate command, R.sub.GC (i+2), for cycle i+2, is the range estimate for point i+2 computed by pure prediction from the range state at i+1, only now using the prediction interval from i+1 to i+2, T.sub.NEW. The velocity gate command, V.sub.GC (i+2), is computed in a similar manner. At the end of FT, T.sub.NEW is stored in T as the current filter cycle period.
A special note should be added. If T.sub.1 .noteq. T.sub.2 (as shown in the figure), the gate commands for cycle i+1 will be incorrect because the prediction interval from i to i+1 was assumed by FT to be T, rather, 1/2(T+T.sub.NEW), since, during cycle i, FT had no a priori knowledge of T.sub.NEW. This gate inaccuracy is not a problem, however, because when the filter cycle period changes, discriminant data will not be gathered over the first filter cycle with the new period. Thus, in the figure, FT called during cycle i+2 would update the state vectors to point i+2 without benefit of discriminant data gathered over i+ 1.
The azimuth and elevation command computations use the tracking error and LOS rate estimates from the new angle state vectors X.sub.e (i+1) and X.sub.d (i+1), to compute and output new antenna drive near the middle of cycle i+1. That computation is controlled to be near the center of the filter cycle because that is the time reference point for X.sub.e i+ 1) and X.sub.d (i+1).
Near the end of filter cycle i+1, the radar controller (FIG. 1) computes new range and velocity gate positions R.sub.G and V.sub.G using R.sub.GC (i+2) and V.sub.GC (i+2), which are then effective throughout filter cycle i+2 and affect the range and velocity discriminants gathered over cycle i+2. From the above discussion it can be seen that the range and velocity gate computations are in the form of a two-step prediction process, while the antenna drive computations are in the form of a one-step prediction process.
A functional flow diagram for the tracking filter routine (FT) will now be described with reference to FIGS. 8a - 8c. Reference numerals in parenthesis identify blocks in the flow diagram. At the beginning of FT in FIG. 8a, the return link to the XT Routine is stored in a special FT variable (memory location) and an initial mode check is made (101). If the mode is Initial Track (I/T), the variable C.sub.INS is set to zero as a first time final track indicator (102). The averaging (111) of T and T.sub.NEW is bypassed in I/T, since the filter periods are all equal in I/T. T and T.sub.NEW are set to the I/T period for the current mode by XT before the start of track.
When not in I/T, which is to say while in the Final Track (F/T) Mode, the radar platform (own-ship) accelerations in antenna coordinates are required by the tracking filter. These accelerations are computed (103-110) by differencing inertial navigation system (INS) velocities V.sub.N, V.sub.E, and V.sub.D =-V.sub.D over a four-filter cycle period (where N, E and D designate the north, east and vertical axes of the INS), dividing by the time of the four-cycle period to produce own-ship accelerations in INS coordinates, then transforming to antenna coordinates using the sines and cosines of aircraft and antenna Euler angles sampled at approximately the center of the four-cycle period. The accelerations a.sub.I.sbsb.r, a.sub.I.sbsb.e and a.sub.I.sbsb.d produced by this process are used in the filter computations for the next four-filter cycles, after which they are refreshed by the above process.
The filter cycle counter is C.sub.INS and the duration of the four-cycle period is accumulated in T.sub.INS. On the first cycle of F/T (indicated by C.sub.INS = 0), the current set of INS velocities is saved in V.sub.N.sbsb.1, V.sub.E.sbsb.1 and V.sub.D.sub..noteq. ; C.sub.INS is set to 1 and T.sub.INS to 0 to initialize the acceleration computations. The covariance matrix M.sub.a.sbsb.i for the Kalman filter is also initialized at this point (110). The quantities .eta..sub.1, .eta..sub.2 and (T.sub.2 - T.sub.1), used in the motion compensation equations, are also initialized in this program branch.
On succeeding filter cycles, T.sub.INS is incremented by the previous filter period, T, and C.sub.INS is incremented by 1. When C.sub.INS = 3 the program is on cycle three of the four-cycle period. Since FT is called early in a filter cycle, the time point when C.sub.INS = 3 is shortly after the end of the cycle two or nearly the mid-point of the four-cycle period. At this time, the current sines and cosines of Euler angles necessary to transform from INS to antenna coordinates are saved in special FT buffer calls. (The sine and cosine of .psi. are computed by FT). When C.sub.INS reaches 5, the time point is just past the end of cycle four of the four-cycle period and T.sub.INS equals the sum of the four previous filter periods. At this point C.sub.INS is reset to 1 and subroutine 8 (FTS8) is called. This subroutine picks up the current INS velocities and, using these and V.sub.N.sbsb.1, V.sub.E.sbsb.1, V.sub.D.sbsb.1, and T.sub.INS, computes the average own ship acceleration in INS coordinates, over the last four filter cycles. It then transforms these accelerations to antenna coordinates using the buffer-stored Euler angles mentioned above. These new values of a.sub.I.sbsb.r, a.sub.I.sbsb.e and a.sub.I.sbsb.d are now available to the filter for the next four cycles. Subroutine 8 also stores the current INS velocities in V.sub.N.sbsb.1, V.sub.E.sbsb.1 and V.sub.D.sbsb.1, and sets T.sub.INS = 0 so that the next acceleration computation cycle is initialized. Finally, in Final Track Mode the old, T, and new, T.sub.NEW, filter periods are averaged (111) and stored in T as the prediction interval from cycle i to cycle i+ 1 (see FIG. 7). Note that if T.sub.NEW has not been changed by XT, then T will simply be the common period of cycles i and i+1.
The angle tracking filter is range and velocity dependent. In the next section (112) of FT, the range, R.sub.TPA, and velocity, V.sub.TPA, to be used in the angle filter are selected. The signal-to-noise ratio, SNR(D), used to determine if the angle filter should extrapolate, is also selected in this section. SNR(D) is selected as SNR.sub.RNG and R.sub.TPA is selected as R.sub.TPR (i). In the Final Track Mode, V.sub.TPV (i) is the best choice for V.sub.TPA ; however, in Initial Track, V.sub.TPV (i) is ambiguous and V.sub.TPR (i) is used in this case. Finally, R.sub.TPA is limited .gtoreq. 512 ft. to avoid overflows in the angle filter computations.
FT next computes in block 113 the angular scintillation parameters .sigma..sub.s.sup.2 and .tau..sub.s by means of subroutine 1 (FTS1), and in the last block 114 of FIG. 5a computes the angle filter state transition matrix, .PHI.(i+1, i), using subroutine 2 (FTS2). Only the non-zero and non-unity elements of .PHI..sub.a are computed. Block 113 also computes the l parameters (Eqs. 37 a,b).
Referring next to FIG. 8b, the FT routine calls a subroutine 3 (FTS3) in block 160 of the flow chart to compute the motion compensation terms L.sub.e.sbsb.1, L.sub.d.sbsb.1, L.sub.e.sbsb.2 and L.sub.d.sbsb.2. For initial track, only a portion of the terms are computed to reduce computation time.
If a `DATAVALID` flag is set (115) to indicate that discriminant data were collected over the previous filter cycle (cycle i) and are available for use on cycle i+1, which is the Yes condition for 115, and if the flag is not set which is the No condition for 115, or SNR(D) indicates too low an SNR (116), which is the No condition for 115, the `ANGLE XTRAP` flag is set (117) and k.sub.e, k.sub.d, .DELTA..sub.e and .DELTA..sub.d are set to zero (118). If discriminants are available and SNR(D) is greater than a threshold, the `ANGLE XTRAP` flag is reset (119). If not in I/T (120), random compensation is computed in block 121 using Subroutine 4 (FTS4), and angle discriminant slopes, k .sub.e and k.sub.d, and total angle residuals, .DELTA..sub.e and .DELTA..sub.d, are computed in block 122 using Subroutine 5 (FTS5). The radome compensation calculation is bypassed in initial track to reduce computation time and is needed in final track only if angle discriminant data are used.
The next section of FT computes the gains for the angle filters. If in initial track (123), one of three sets of gains is selected (124), based on R.sub.TPA. In final track, the angle gains are computed. Some logic is gone through before making these computations. If, in the previous filter cycle, it was determined that one or both of the first two co-variance matrix diagonal terms, m.sub.11 and m.sub.22, were becomming large relative to their full scale values, the `M.sub.a MATRIX LARGE` flag will have been set. If that is so (125) and the angle filter is extrapolating (126), this would drive the co-variance matrix even larger. This is clearly undesirable since the M.sub.a matrix must not overflow. Consequently, in this instance, the gain calculation is bypassed and the last Kalman gains computed with be used. If the last M.sub.a matrix were not too large or if the angle filter is not extrapolating, the MATRIX LARGE flag is reset (127) and the Kalman gains, K.sub.a (i), are computed (128) and the covariance matrix is updated to M.sub.a (i+1) by means of Subroutine 6 (FTS6). After this, calculations m.sub.11 (i+1) and m.sub.22 (i+1) are examined (129) to see if either one of them is getting to large. If so, the `M.sub.a MATRIX LARGE` flag is set (130) and m.sub.11 (i+1), m.sub.22 (i+1) and m.sub.12 (i+1) are all reduced by a factor C.sub.13.
After the gains have been determined, the angle state vectors are updated (131) to the point i+1 by means of Subroutine 7 (FTS7) using the states at point i, the .PHI. matrix, the motion compensation terms and the total angle residuals weighted by the gains. The program then proceeds in FIG. 8c to the range and velocity filter section of FT.
At the beginning of the range and velocity filter calculations, the `DATAVALID` flag is checked (132) to see if discriminant data were collected over the last filter cycle. If no discriminant data was collected, the program branches to set the extrapolation conditions, but if discriminant data are available, the program will select gains for the range and/or velocity filters provided that the appropriate SNR is not below a certain threshold (SNR1). If the SNR in question is too low (133), the filter will be put into an extrapolation mode. Furthermore, in Final Track Mode, the velocity filter will couple into the range filter under this condition (134 and 135).
For non-extrapolation conditions, and in Initial Track Mode (136) the program provides for the selection of one of two sets of gains in initial track (137) and one of two sets of gains in final track (138). Gain selection is based on SNR.sub.RNG.
After the gain constants have been selected and stored in variable cells (i.e., predetermined memory locations) the target acceleration model tme constnat, .tau..sub.a, is set (139) at a normal 3 seconds. The range discriminant slope and the total range residual, .DELTA.R.sub.M, is computed (140, 141) as shown on the detailed flow chart of FIGS. 9a-9f. The total velocity residual, .DELTA.V.sub.M, is also computed (142). Note that the measured discriminants .DELTA.R.sub.m = .DELTA.R.sub.DSCR and .DELTA.V.sub.m = .DELTA.V.sub.DSCR are here distinguished from the respective residuals by the capital M subscripts for the residuals.
For the extrapolate condition, .tau..sub.a, is set at 10 seconds and R.sub.M and V.sub.M are both set = 0 in block 143. If range is available from the range filter (144), the two branches of the program now merge to update the range filter state vectors (145). Similarly, if velocity is available from the velocity filter (146) the velocity filter state vectors are updated (147).
At the end of FT, T.sub.NEW is installed in T as the current filter period (148), range, R.sub.TPR (i+1), is limited to be greater than a positive lower limit, R.sub.L, to avoid negative ranges, and control is returned to the executive (XT) Routine, thus completing a tracking filter cycle.
Entering the tracking filter routine (FT) in FIG. 9a the boxes will be identified by the code identifier number. The routine of FIGS. 9a to 9f provide a detailed description of the routine of FIGS. 8a to 8d.
In box FT004 the return address to the executive (control) routine is stored in memory cell FTV0000.
In box FT005 a decision is made for initial track where XTF001 is the initial track flag and if it is not equal to 0 the system is in initial track. If there is not an initial track condition the system goes to box FT010 and C.sub.INS which is the counter for computing the own ship's acceleration and counts entries into this routine is checked to determine if it is equal to 0.
If C.sub.INS = 0 (YES) then the routine initializes the acceleration computations and also initializes the co-variance matrix of box FT018.10.
In box FT012, the present A/C velocities are stored and in box FT017, time T.sub.INS (the time between velocity samples in order to do the acceleration) are stored as well as C.sub.INS.
Then in box FT018.70 .eta..sub.1 and .eta..sub.2 which are two successive samples of antenna azimuth, are set. Also, two time tags are saved as the difference, which is an initializing computation for the antenna azimuth rate. In box FT042 the filter cycle time is computed.
If C.sub.INS is not equal to 0 in box FT010, the flow goes to box FT021 where T.sub.INS is updated and the counter is updated in box FT024.
In box FT026 a check is made to see if counter C.sub.INS, contains a value of 3 which is in the middle of the acceleration compute cycle.
In box FT028 the current aircraft heading is then fetched.
In box FT029, the sine and cosine of the aircraft heading is computed and the computed values are stored in box FT030.
In box FT032 the sines and cosines of the angles required to perform the inertial to antenna transformation are stored.
If in box FT026 a NO is detected and box FT037 a YES is detected then the routine is not yet at the end of the acceleration branch compute cycle and if a NO is detected it means that the routine is at the end of the cycle. When going to FT039 the operation is to reset the counter. In box FT040, the own ship acceleration is computed and stored. If the decision in box FT026 is YES, the flow skips its own ship acceleration computations.
Going from box FT007 to FIG. 9b, box FT005 fetches the range and the range rate and SNR(RNG).
Box FT061 makes an initial track determination and if it is a YES, box FT063 fetches a different value for range rate. If a NO is determined the operation goes directly to box FT083 where register one (R1) is examined and with box FT083.20 the range is limited to 512 feet so range has a minimum value for computation purposes.
In the next step, box FT083.30 stores range, velocity and SNR.
In box FT088 an initial track checkk is again made.
Box FT090 and FT093 function to select b and c for digital filtering.
In box FT095 a shaping parameter 1.sub.e for elevation filtering is computed and in box FT102 a shaping parameter 1.sub.d is computed for azimuth filtering.
Referring to FIG. 9b-1 and box FT117 the scintillation parameters are computed and stored (.sigma..sub.s.sup.2 is the variance of the target scintillation model and .tau..sub.s is the time constant).
Box FT122 is the state transition matrix and in box FT124, both for final and for initial track, part of the L vector is computed and if the system is in initial track, it exits. If the system is in final track, the operation goes to the following box and computes the remainder of the terms.
In box FT126, a flag is checked to see if there is valid discriminant data. If the data is valid, the SNR in box FT128 is checked to see if it is above a threshold. In box FT131, the flag angle extrapolate is reset meaning the system is not in an angle extrapolate (i.e. the data is valid and being received and there is a satisfactory SNR).
In box FT132 a check is made of initial track so that if the system is in initial track, the radome compensation is skipped to save computing time. If the routine goes to box FT134, the radome compensation is performed.
In box FT135, the residual (difference between the measured and computer determination of tracking error) is computed and stored. If the data is not valid in box FT126 or the SNR is below a threshold value, set angle extrapolate in box FT138 and set the discriminant slopes and residuals equal to zero in box FT139.
In FIG. 9c an initial track determination is made in box FT145 and if the result is YES, the filter gains are selected for initial track based on range or an SNR threshold (Kalman gains are not computed). This index operation includes box FT185. If the initial track is NO in box FT145, then the flag is examined in box FT147 to determine if the matrix is close to overflow. If the Ma matrix is close to overflow and the system is in the angle extrapolate mode, (FT149) then the gain and covariance update is skipped and the last set of gains constants are used. In box FT151 the flag is reset and in box FT152 the Kalman gain and the covariance update are computed and stored.
In boxes FT153 and FT156, a determination is made whether the Ma matrix is close to overflow, and if YES, the routine goes to box FT161 to set the flag. In box FT162 the covariance elements are decreased to minimize chances of overflow. In box FT191, the state vectors are updated based on state transition matrix .phi., the L vectors and the Kalman gains time the residuals.
Going now to FIG. 9d which selects gains for the range and velocity filters based on SNR, a data valid determination is made in box FT411 and if the data is not valid, continues on to FIG. 9e. If the data is valid, in box FT415 a check is made to see if SNR is below a minimum threshold (SNR.sub.1), and if below, box FT491 again performs a check if initial track, and if YES goes to FIG. 9e. If there is not initial track (NO) in box FT491, the velocity filter estimates are coupled into the range filter estimates in box FT493.
An initial track check is made in box FT418 and if the track is initial, two sets of gains are selected in boxes FT420, FT428 and FT424. If the system is in final track, one of two sets of gains are picked based on SNR in boxes FT430, FT434 and FT438.
Referring now to FIG. 9e, when data is not valid or a very low SNR is present in box FT495 T.sub.A (target acceleration model time constant) is set to 10 seconds. In box FT496, the range and velocity residuals are set to zero.
In box FT499, the selected gains are picked up and stored and in box FT508, the target acceleration model time constant .tau..sub.n is set to 3 seconds. In boxes FT511, FT513 and FT522 the range discriminant slope (k.sub.R.sbsb.f) is computed and in box FT530, the velocity residual is computed. In box FT533 the range and velocity residuals are stored and in box FT537 the filter cycle time and other parameters are computed.
Referring now to FIG. 9f, a range available determination is made in box FT545.10 and if the result is YES, the flow goes to box FT548 in which the update equations are calculated to update the range filter states. Also a new range gate R.sub.GC setting is computed. Box FT597.10 is entered, to make a velocity available determination, and if the determination is YES, the velocity filter state update computations are performed in box FT598. A new velocity gate V.sub.GC is also computed in this box. In box FT660, T.sub.NEW the new filter cycle time is stored as the current filter cycle time. In boxes FT662, FT663 and FT665 the range is limited so as to be not less than R.sub.L (an arbitrary minimum range). Then in box FT666, the operation returns to the track executive routine via the address shown in FTV0000 as stored in box FT004 of FIG. 9a.
The subroutines FTS1 through FTS8 and FT1 called by the FT routine will now be described in order. Following that antenna control routine, designated AT and its only subroutine ATS1 will be described.
Subroutine FTS1 illustrated in the flow diagram of FIG. 10 is the Angular Scintillation Parameters Subroutine. Its purpose is to compute the variance, .sigma..sub.s.sup.2, and the time constnat, .tau..sub.s, of the angular scintillation noise model for the Tracking Filter Routine (FT). It is called with a BALFTS1, 0 instruction. The subroutine stores .sigma..sub.s.sup.2 and .tau..sub.s in FT variable memory. The terms and their equations computed by FTS1 are as follows. ##EQU22## .alpha..sub.1, .alpha..sub.2 and .alpha..sub.3 are constants.
Subroutine FTS2 illustrated in the flow diagram of FIG. 11 is the Angle State Transition Matrix Subroutine. Its purpose is to compute the non-zero and non-unity elements of the angle state transition matrix, .PHI., for the Tracking Filter Routine (FT). It is called with a BAL FTS2, 0 instruction. The subroutine stores the computed .PHI. elements in FT variable memory.
The angle tracking filter state transition matrix is given by the equation:
.PHI.(i+1, i) = e.sup.A(i)T .apprch. I + A(i)T + A.sup.2 (i)(T.sup.2 /2) (59)
where
T = Filter prediction interval from point i to i +1
I = 4 .times. 4 unity (identity) matrix ##EQU23## R.sub.TPA (i) = Range used in angle filter V.sub.TPA (i) = Range rate used in angle filter
.tau..sub.T = Target normal acceleration model time constant (= const)
.tau..sub.s (i) = Angular scintillation model time constant (computed in FTS1)
Computing .PHI. from the three-term expansion gives ##EQU24## where .phi..sub.11 = 1
.phi..sub.12 = T - T.sup.2 V.sub.TPA /R.sub. TPA
.phi..sub.13 = -t.sup.2 /2 r.sub.tpa
.phi..sub.22 = 1 - 2t v.sub.tpa /r.sub. tpa + 2 [t v.sub.tpa /r.sub. tpa ].sup.2
.phi..sub.23 = -t/r.sub.tpa + t.sup.2 v.sub.tpa /r.sup. 2.sub.tpa + t.sup.2 /(2.tau..sub.t r.sub.tpa)
.phi..sub.33 = 1 - t/.tau..sub.t + 1/2 (t/.tau..sub.t).sup.2
.phi..sub.44 = 1 - t/.tau..sub.s + 1/2 (T/.tau..sub.s).sup.2
The computational steps executed by FTS2 to compute the .PHI. elements are listed below:
x = .alpha..sub.T.sup.T where .alpha..sub.T = 1/.tau..sub.T = const (62)
.phi..sub.33 = 1 - x+x.sup.2 /2 (63)
Y = T/.tau..sub.s (64)
.phi..sub.44 = 1 - Y+Y.sup.2 /2 (65)
z = t .sup.. v.sub.tpa /r.sub.tpa (66)
.phi..sub.12 = t(1 - z) (67)
.phi..sub.22 = 1 - 2z(1 - z) (68)
.phi..sub.13 = (t.sup.2 /2)/r.sub.tpa (69)
.phi..sub.23 = - .phi..sub.12 /r.sub.tpa - .alpha..sub.t .sup.. .phi..sub.13 (70)
the six .PHI. elements are stored in FT variable memory for later use. The zero elements and .phi..sub.11 are not allocated memory locations.
Subroutine FTS3 illustrated in the flow diagram of FIGS. 12a-12c is the Motion Compensation Subroutine. Its purpose is to compute the non-zero elements of the motion compensation vectors, L.sub.e and L.sub.d, used in the angle tracking filter. It is called with a BAL FTS3, 0 instruction. The subroutine stores the computed elements in FT variable memory.
The motion compensation vectors, L.sub.e and L.sub.d, are given by ##EQU25## For Initial Track ##EQU26##
L.sub.e.sbsb.2 = 0 (73)
L.sub.d.sbsb.2 = 0 (75) where
.omega..sub.e = Antenna inertial rate about e over i to i+1
.omega..sub.d = Antenna inertial rate about d over i to i+1
.omega..sub.A.sbsb.r = Measured antenna inertial rate about r at one point in the interval i to i+1
.theta..sub.r = .omega..sub.A.sbsb.r .sup.. T
Other terms have been defined hnereinbefore. The simplification in initial track is to reduce computational load only.
The integrals of antenna angular rates over t.sub.i to t.sub.i.sub.+1 are provided by an antenna rate integrating gyro which provides a measured gyro output ##EQU27## if .omega..sub.A is assumed constant over the interval T = t.sub.i.sub.+1 -t.sub.i.
Since the .theta.s must be sampled as close as possible to t.sub.i and t.sub.i.sub.+1, FTS3 computes only the -T.omega..sub.A term of the integral, and the second term, involving the .theta.s, is added later by an antenna control (AT) Routine which adds this term directly to .epsilon..sub.p (i+1), rather than L.sub.1, since FT furnishes .epsilon..sub.p (i+1) to AT complete, except for the second term of the above integral. The AT routine will be discussed hereinafter.
In the first part of FTS3, the last values of A105 and A104 input by the XT Routine are picked up and converted to radians/second using stored scale factors. The terms -T.omega..sub.A.sbsb.e and -T.omega..sub.A.sbsb.d are formed and stored as L.sub.e.sbsb.1 and L.sub.d.sbsb.1, respectively. If the mode is Initial Track, FTS3 exists. (L.sub.e.sbsb.2 and L.sub.d.sbsb.2 will be zero by virtue of initialization prior to entering track.)
In the Final Track Mode, L.sub.e.sbsb.1 and L.sub.d.sbsb.1 must be augmented by additional terms and L.sub.e.sbsb.2 and L.sub.d.sbsb.2 must be computed. After storing the return address, FTS3 computes the antenna rate about the antenna, r, axis, .omega..sub.A.sbsb.r , given by ##EQU28## .omega..sub.OG is the outer (roll) gimbal rate of the antenna given by the last value of A112 converted to radians/second using a stored scale factor. The term .eta. is computed by differencing two samples of .eta., .eta..sub.2, and .eta..sub.1, saved by XT in FT variable memory, then divided by the time difference, (T.sub.2 - T.sub.1), between the two samples, also saved by XT in an FT dedicated location.
After .omega..sub.A.sbsb.r is computed, the term .theta..sub.r = T.omega..sub.A.sbsb.r is computed and the term .theta..sub.r .epsilon..sub.P.sbsb.d added to L.sub.e.sbsb.1 and the term (-.theta..sub.r .epsilon..sub.P.sbsb.e) added to L.sub.d.sbsb.1.
The term ##EQU29## is computed and added to L.sub.e.sbsb.1 to complete L.sub.e.sbsb.1.
The term ##EQU30## is computed and stored as L.sub.e.sbsb.2.
A similar procedure is used to complete L.sub.d.sbsb.1 and to compute L.sub.d.sbsb.2. FTS3 exits by execution of an indirect branch to the location containing the saved return address.
Subroutine FTS4 illustrated in the flow diagram of FIGS. 13a and 13b is the Radome Compensation Subroutine. Its purpose is to compute compensation terms to counteract tracking error measurement perturbations due to radome diffraction of target return signals. Two terms, .sigma..sub.R.sbsb.e and .sigma..sub.R.sbsb.d are computed for the angle tracking filter and represent estimates of elevation and azimuth tracking error indications, respectively, due to radome diffraction effects.
FTS4 is entered only in Final Track Mode and only if the tracking error measurements (angle discriminants) are available. The subroutine stores .sigma..sub.R.sbsb.e and .sigma..sub.R.sbsb.d in FT variable memory for later use. It is called with a BAL FTS4, 0 instruction.
To better understand the nature of the randome compensation computations, an explanation of several definitions is in order.
i.sub.R, j.sub.R, k.sub.R -- radome axes
i.sub.R is the radome boresight axis
j.sub.R is along the A/C j axis
k.sub.R completes the right hand set
i.sub.R and k.sub.R form the radome elevation principal plane
i.sub.R and j.sub.R form the radome azimuth principal plane
.sigma..sup.1 -- radome tilt down angle from A/C FLR; i.e., i.sub.R, j.sub.R, k.sub.R are obtained by rotating i, j, k through -.sigma..sup.1 about the j (or j.sub.R) axis.
.DELTA. -- angle between radome boresight and antenna boresight; i.e., .DELTA. = cos.sup.-.sup.1 (i.sub.R .sup.. l.sub.r)
.sigma..sub.EL -- beam deflection when .DELTA. is in elevation principal plane of radome, supplied by radome manufacturer as a three-line segment function of .DELTA..
.sigma..sub.AZ -- beam deflection when .DELTA. is in azimuth principal plane of radome, supplied by radome manufacturer as a three-line segment function of .DELTA..
.alpha. .DELTA., .gamma. -- special Euler angle sequence to transform from randome axes to antenna axes.
The angle .DELTA. (actually, sin .DELTA. is used) is required to select .sigma..sub.EL and .sigma..sub.AZ from the supplied curves. .alpha. is used to interpolate between the curves to determine the total deflection, .sigma.. The angle .gamma. is used to resolve .sigma. into .sigma..sub.Re and .sigma..sub.Rd.
The first computations are of the cosine and sine of .DELTA. as given by the following equations.
cos .DELTA. = i.sub.R .sup.. 1.sub.r = cos .sigma..sup.1 cos .epsilon. cos .eta. + sin .sigma..sup.1 [sin.phi..sub.G sin .eta. - cos .phi..sub.G sin .epsilon. cos .eta.] (83)
sin .DELTA. = 1 - cos.sup.2 .DELTA. (assumed to be always positive) (84)
Next, sin .alpha., cos .lambda. and sin .lambda. are computed as follows. ##EQU31##
The quantities .delta..sub.EL and .delta..sub.AZ are computed as a function of sin .DELTA.. Sin .DELTA. is used rather than .DELTA. to avoid a lengthy sin.sup.-.sup.1 procedure and because most of the variations in .delta..sub.EL and .delta..sub.AZ occur at relatively small .DELTA.s. One of three linear equations is used for each of .delta..sub.EL and .delta.AZ, depending on the size of sin .DELTA.. The break points for sin .DELTA. are the same for both principal planes.
In general, the angle .DELTA. will not lie in either of the principal planes of the radome. The total beam deflection, .delta., is assumed, however, to be always in the .DELTA. plane and toward the radome boresight axis. Since .alpha. is the angle between the .DELTA. plane and the radome elevation principal plane, .delta. can be obtained by interpolating the .delta..sub.EL , and .delta..sub.AZ values according to the formula: .sub. ##EQU32## Quadratic functions are used where the j.sub.R, k.sub.R cross-section of the radome is elliptical in shape and sin.sup.2 .alpha. gives a better interpolation than .vertline. sin .alpha. .vertline..
Finally, .delta..sub.R.sbsb.d and .delta..sub.R.sbsb.e are obtained by resolving .delta. through .lambda.. The compensation terms are stored, and FTS4 exits.
Subroutine FTS5 illustrated in the flow diagram of FIG. 14 is the Angle Discriminant Slopes and Total Residuals Subroutine. Its purpose is to compute the elevation and azimuth angle discriminant slopes, k.sub.e and k.sub.d, respectively, and the elevation and azimuth total angle residuals, .DELTA..sub.e and .DELTA..sub.d, respectively. The subroutine is entered whenever angle discriminants are available. The computed terms are stored in FT variable memory for later use. It is called with a BAL FTS5, 0 instruction.
The quantities computed by FTS5 have the following definitions. ##EQU33##
The curve of discriminant output versus the measured tracking error is a function of SNR and is not truly linear. A linear relationship is assumed, however, as required by Kalman filter theory and should hold for small tracking errors. The total angle residual is a measure of the noise in the tracking error measurement and the error between the true tracking error and the filter predicted tracking error. The term "tracking error" in the above discussion is meant to include all off boresite effects "seen" by the radar. Thus, tracking error in the above sense includes target off boresite, angular scintillation, and radome diffraction effects.
The BIT calibration variable, D.sub.CAL, is loaded into R2 and R4. If SNR.sub.e = SNR(EL) is greater than a threshold, then k.sub.e = D.sub.CAL. If SNR(EL) is small, then k.sub.e is computed as a linear function of D.sub.CAL and SNR(EL).
After k.sub.e has been calculated, the elevation total angle residual, .DELTA..sub.e, is computed: ##EQU34## The constant C.sub.10 converts the non-dimensional discriminant, .DELTA..epsilon..sub.DSCR, from the DS Routine, to radians. The term .vertline..epsilon..sub.P.sbsb.e + S.sub.P.sbsb.e +.delta..sub.R.sbsb.e .vertline. represents the filter's estimate of what the radar should measure as a "tracking", or, more properly, an off boresite error.
FTS5 follows a similar procedure to the above discription to compute k.sub.d and .DELTA..sub.d, and then exits.
Subroutine FTS6 illustrated in the flow diagram of FIGS. 15a through 15d is the Kalman Gains and Covariance Matrix Update Subroutine. Its purpose is to compute Kalman gains for the angle tracking filter and update the angle state vectors covariance matrix to the point i+1. Kalman gains are computed only in final track, and the same gains are used for both angle channels by using the average of the measurement characteristics (discriminant slopes) of the two channels in the gain computation. A single covariance matrix is also used for both angle channels, and the lower (symmetric) off diagonal terms are not carried.
FTS6 is entered only in final track. The Kalman gain matrix, K.sub.a (i), used to weight the angle residuals is computed and stored in FT variable memory. The diagonal and upper off-diagonal terms of M.sub.a (i+1), the angle covariance matrix for point i+1, are also computed and stored in FT variable memory. It is called with a BAL FTS6, 0 instruction.
The equations for the gain, K.sub.a (i), and the updated covariance matrix, M.sub.a (i+1), for a one-step Kalman predictor are given below.
K.sub.a (i) = .PHI.(i) M.sub.a (i) H.sub.a.sup.T (i) [H.sub.a (i) M.sub.a (i) H.sub.a.sup.T (i) + R.sub.a (i)] .sup.-.sup.1 (90)
M.sub.a (i+1) = [.PHI.(i) - K.sub.a (i) H.sub.a (i)] M.sub.a (i) .PHI..sup.T (i) + Q.sub.a (i) (91)
where
H.sub.a (i) = measurement or observation matrix. To avoid separate gain calculations for each angle channel, H.sub.a (i) is taken to be the average measurement matrix for the elevation and azimuth channels, i.e.
H.sub.a (i) = [k.sub.2 (i) 0 0 k.sub.a (i)]
where
k.sub.a (i) = 1/2 [k.sub.e (i) + k.sub.d (i)]
R.sub.a (i) = measurement noise covariance matrix = .sigma..sub.a.sup.2 (a scalar in this case
Q.sub.a (i) = system noise covariance matrix
M.sub.a (i) = angle state vectors' covariance matrix for point i
.PHI.(i) = angle state transition matrix from point i to point i+1
Define the auxiliary matrix D.sub.a (i) = .PHI.(i) M.sub.a (i): ##EQU35## where m.sub.jl = m.sub. lj for j .noteq. l The equation for K.sub.a (i) can now be expanded to yield ##EQU36## Now define the auxiliary variables ZM1 = m.sub.11 + m.sub.14
Zm2 = m.sub.12 + m.sub.24
Zm3 = m.sub.13 + m.sub.34
Zm4 = m.sub.14 + m.sub.44 (94)
From the equation there results the following (remembering that M.sub.a (i) is symmetric and .phi..sub.11 = 1)
Z.sub.a.sbsb.1.sbsb.1 = d.sub.11 + d.sub.14 = ZM1 + .phi..sub.12 ZM2 + .phi..sub.13 ZM3
z.sub.a.sbsb.2.sbsb.1 = d.sub.21 + d.sub.24 = .phi..sub.22 ZM2 + .phi..sub.23 ZM3 (95)
z.sub.a.sbsb.3.sbsb.1 = d.sub.31 + d.sub.34 = .phi..sub.33 ZM3
z.sub.a.sbsb.4.sbsb.1 = d.sub.41 + d.sub.44 = .phi..sub.44 ZM4
Finally, the gain matrix can be written ##EQU37##
The equation for M.sub.a (i+1) can be written in the form below.
M.sub.a (i) .PHI..sup.T (i) = D.sub.a.sup.T (i)
Note that since M.sub.a (i) is symmetric, ##EQU38## where Q.sub.s and .alpha..sub.4 are constants in the Q.sub.a matrix.
The return address in RO is saved in FTV2400. A non-zero value is stored in R6 to avoid a possible 0/0 division in case k.sub.a should be 0. The measurement parameter, k.sub.a, is formed as the average of the elevation and azimuth angle discriminant slopes. If k.sub.a = 0 (extrapolate condition), then the gains should be 0 according to Equation (96). In this case the Z.sub.a terms need not be computed and FTS6 branches directly to the computation of the K.sub.a terms which will result in 0 values by virtue of k.sub.a = 0, and a non-zero value for the denominator term in R6.
If k.sub.a is non-zero, FTS6 computes the ZM1 through ZM4 terms (auxiliary variables) and the Z.sub.a.sbsb.1.sbsb.1 through Z.sub.a.sbsb.4.sbsb.1 terms of Equation (95). The k.sub.a.sup.2 [ZM1 + ZM4] portion of the denominator is computed in R6. The system measurement noise variance, .sigma..sub.a.sup.2, is computed as follows.
SNR.sub.a = SNR (angle) = 1/2[SNR(AZ) + SNR(EL)]= 1/2 [SNR.sub.d +SNR.sub.e ]
.sigma..sub.a.sup.2 = R.sub.a.sbsb.0 (a constant) for SNR (angle) < 1 ##EQU39## The noise variance is added to R6 to form the complete denominator term for the gain computation.
The four gain terms are computed according to Equation (96) in an index loop. R2 is used as the loop controller (four iterations) and also selects the proper Z.sub.a from temporary storage and routes the computed gain to the proper cell. The terms k.sub.a Z.sub.a.sbsb.i.sbsb.1 are also saved in the four FT temporary storage cells as they are needed in the covariance update computations to follow. R1 contains a shift count to adjust the k.sub.a Z.sub.a.sbsb.i.sbsb.1 product to obtain the proper scaling for each K.sub.a. Fortunately, there was a simple relationship between the shift count required and the loop counter. After the gains have been computed and stored, FTS6 proceeds to the covariance update computations.
Equation (97) will be used to derive the equations for the covariance matrix update. As a preliminary step to updating the m terms, the program computes the following auxiliary variables in the registers RO through R3 indicated.
d.sub.12 = m.sub.12 + .phi..sub.12 m.sub.22 + .phi..sub.13 m.sub.23 .fwdarw. RO
d.sub.13 = m.sub.13 + .phi..sub.12 m.sub.23 + .phi..sub.13 m.sub.33 .fwdarw. R1 .phi..sub.22 m.sub.23 .fwdarw. R2 (98)
d.sub.23 = .phi..sub.22 m.sub.23 + .phi..sub.23 m.sub.33 .fwdarw. R3
The diagonal elements of M.sub.a (i+1) are computed first. From Equation (97),
m.sub.11 (i+1) = d.sub.11 + .phi..sub.12 d.sub.12 + .phi..sub.13 d.sub.13 - k.sub.a k.sub.a (d.sub.11 +d.sub.14) +Q.sub.s (99)
and using Equations (94) and (95), this expression reduces to
m.sub.11 (i+1) = (m.sub.11 +Q.sub.s) - K.sub.a.sbsb.1 (K.sub.a Z.sub.a.sbsb.1.sbsb.1) + .phi..sub.12 [m.sub.12 +d.sub.12 ] + .phi..sub.13 [m.sub.13 + d.sub.13 ] (100)
Again, from Equations (97), (92) and (95) there results
m.sub.22 (i+1) = .phi..sub.22 d.sub.22 + .phi..sub.23 d.sub.23 - K.sub.a K.sub.a2 (d.sub.21 +d.sub.24) = .phi..sub.22 .sup.2 m.sub.22 - K.sub.a2 (k.sub.a Z.sub.a.sbsb.2.sbsb.1) + .phi..sub.23 [.phi..sub.22 m.sub.23 + d.sub.23 ] (101)
m.sub.33 (i+1) = .phi..sub.33 d.sub.33 + K.sub.a K.sub.a.sbsb.3 (d.sub.31 +d.sub.34) + .alpha..sub.4 T = .phi..sub.33 .sup.2 m.sub.33 - K.sub.a.sbsb.3 (K.sub.a Z.sub.a.sbsb.3.sbsb.1) + .alpha..sub.4 T (102) ##EQU40## Note that the terms (K.sub.a Z.sub.a.sbsb.i.sbsb.1) were saved in FT temporary storage from the gain computations.
To obtain the update equations for the upper offdiagonal terms, it is sometimes simpler to use the expansion for the corresponding (equal) lower diagonal term. Thus,
m.sub.12 (i+1) = m.sub.21 (i+1) = .phi..sub.22 d.sub.12 + .phi..sub.23 d.sub.13 - K.sub.a K.sub.a.sbsb.2 (d.sub.11 +d.sub.14) = .phi..sub.22 d.sub.12 + .phi..sub.23 d.sub.13 + K.sub.a.sbsb.1 (K.sub.a Z.sub.a.sbsb.2.sbsb.1 ) (104)
since
K.sub.a.sbsb.2 Z.sub.a.sbsb.1.sbsb.1 = K.sub.a.sbsb.1 Z.sub.a.sbsb.2.sbsb.1 (105)
Also
m.sub.13 (i+1) = m.sub.31 (i+1) = .phi..sub.33 d.sub.13 - k.sub.a K.sub.a.sbsb.3 (d.sub.11 +d.sub.14) = .phi..sub.33 d.sub.13 - K.sub.a.sbsb.1 (k.sub.a Z.sub.a.sbsb.3.sbsb.1 ) (106)
Before continuing with the off-diagonal updates, the following auxiliary variables are computed in the registers shown.
d.sub.43 = .phi..sub.44 m.sub.34 .fwdarw. R0
d.sub.42 = .phi..sub.44 m.sub.24 .fwdarw. R1 (107) (d.sub.23 is still in R3)
The remaining upper off-diagonal m terms are obtained as follows.
m.sub.14 (i+1) = d.sub.41 +.phi..sub.12 d.sub.42 + .phi..sub.13 d.sub.43 - k.sub.a K.sub.a.sbsb.1 (d.sub.41 +d.sub.44) = .phi..sub.44 m.sub.14 + .phi..sub.12 d.sub.42 + .phi..sub.13 d.sub.43 - K.sub.a.sbsb.1 (k.sub.a Z.sub.a.sbsb.4.sbsb.1 ) (108)
m.sub.23 (+1) = m.sub.32 (i+1) = .phi..sub.33 d.sub.23 - k.sub.a K.sub.a.sbsb.3 (d.sub.21 +d.sub.24) = .phi..sub.33 d.sub.23 - K.sub.a.sbsb.2 (k.sub.a Z.sub.a.sbsb.3.sbsb.1 ) (109)
m.sub.24 (i+1) = .phi..sub.22 d.sub.42 + .phi..sub.23 d.sub.43 - k.sub.a K.sub.a.sbsb.2 (d.sub.41 + d.sub.44) = .phi..sub.22 d.sub.42 + .phi..sub.23 d.sub.43 - K.sub.a.sbsb.2 (K.sub.a Z.sub.a.sbsb.4.sbsb.1 ) (110)
m.sub.34 (i+1) = .phi..sub.33 d.sub.43 - k.sub.a K.sub.a.sbsb.3 (d.sub.41 + d.sub.44) = .phi..sub.33 d.sub.43 - K.sub.a.sbsb.3 (k.sub.a Z.sub.a.sbsb.4.sbsb.1) (111)
At the end of the covariance update, FTS6 exits via the return address stored in location FTV2400.
Subroutine FTS7 illustrated in the flow diagram of FIG. 16 is the Angle State Vectors Update Subroutine. Its purpose is to update the angle state vectors, X.sub.e and X.sub.d, to the point i+1 using the state vectors at point i and the previously computed state transition matrix, .PHI., the motion compensation vectors L.sub.e and L.sub.d, the angle filter gain matrix, K.sub.a, and the total angle residuals .DELTA..sub.e and .DELTA..sub.d. It is called with a BAL FTS, 0 instruction. The new angle state vectors, X.sub.e (i+1) and X.sub.d (i+1) are stored in FT variable memory.
The vector-matrix equations to update the angle state vectors are shown below.
X.sub.e (i+1) = .PHI.(i+1, i) X.sub.e (i) + L.sub.e (i) + K.sub.a (i) .DELTA..sub.e (112)
X.sub.d (i+1) = .PHI.(i+1, i) X.sub.d (i) + L.sub.d (i) + K.sub.a (i) .DELTA..sub.d (113)
These equations can be expanded in scalar form to yield the following set of equations computed by FTS7.
.epsilon..sub.P.sbsb.e (i+1) = .epsilon..sub.P.sbsb.e (i) + .phi..sub.12 .omega..sub.LSP.sbsb.e (i) + .phi..sub.13 a.sub. TP.sbsb.d (i) + L.sub.e.sbsb.1 (i) + K.sub.a.sbsb.1 (i) .DELTA..sub.e (i) (114)
.omega..sub.LSP.sbsb.e (i+1) = .phi..sub.22 .omega..sub.LSP.sbsb.e (i) + .phi..sub.23 a.sub.TP.sbsb.d (i) + L.sub.e.sbsb.2 (i) + K.sub.a.sbsb.2 (i) .DELTA..sub.e (i) (115)
A.sub.TP.sbsb.d (+1) = .phi..sub.33 a.sub.TP.sbsb.d (i) + K.sub.a.sbsb.3 (i) .DELTA..sub.e (i) (116)
S.sub.P.sbsb.d (i+1) = .phi..sub.44 S.sub.P.sbsb.e (i) + K.sub.a.sbsb.4 (i) .DELTA..sub.e (i) (117)
.epsilon..sub.P.spsp.1 (i+1) = .epsilon..sub.P.sbsb.d (i) + .phi..sub.12 .omega..sub.LSP.sbsb.d (i) + .phi..sub.13 a.sub.TP .sbsb.e (i) + L.sub.d.sbsb.1 (i) + K.sub.a.sbsb.1 (i) .DELTA..sub.d (i) (118)
.omega..sub.LSP.sbsb.d (i+1) = .phi..sub.22 .omega..sub.LSP.sbsb.d (i) + .phi..sub.23 a.sub.TP .sbsb.e (i) + L.sub.d.sbsb.2 (i) + K.sub.a.sbsb.2 (i) .DELTA..sub.d (i) (119)
a.sub.TP .sbsb.e (i+1) = .phi..sub.33 a.sub.TP .sbsb.e (i) + K.sub.a.sbsb.3 (i) .DELTA..sub.d (i) (120)
S.sub.P.sbsb.d (i+1) = .phi..sub.44 S.sub.P.sbsb.d (i) + K.sub.a.sbsb.4 (i) .DELTA..sub.d (i) (121)
Note that the .phi. matrix elements and the gains are the same for both channels. velocity
The return address in R0 is saved in FTV2400. Equation sets (118) to (121) and (114) to (118) are computed with the same code, with index registers set to select the proper variables. R1 is used as an iteration counter and also selects the proper angle residual. R2 is used to select the proper L terms and R3 selects the proper state variables. The initial value of 2 for R1 will cause the required two iterations of the code and also select .DELTA..sub.d as the angle residual for the first iteration. The inital value of 4 for R2 will select L.sub.d.sbsb.1 and L.sub.d.sbsb.2 for the equations on the first iteration, and the initial value of 8 for R3 will cause selection of the azimuth states on the first iteration. Equations (118) to (121) are computed first and the updated azimuth states stored in memory.
At the end of the azimuth channel state vector update, R2 and R3 are set to 0. This will cause selection of L.sub.e.sbsb.1 and L.sub.e.sbsb.2 and the elevation states, respectively, in the equations on the second iteration. A Branch and Count (BCT) instruction is executed reducing R1 to 0, which will now select .DELTA..sub.e for the equations, and the program branches to execute Equations (114) to (118) on the second iteration.
At the end of the elevation channel state vector update, the second execution of the BCT instruction, with R1 now equal to 0, leads to the exit instruction, an indirect branch to location FTV2400.
Subroutine FTS8 illustrated in the flow diagram of FIG. 17 is the Ownship Acceleration in Antenna Coordinates Subroutine. Its purpose is to compute the components of own ship acceleration in antenna coordinates for use as aiding terms in the angle, range, and velocity tracking filters. These components are computed every four tracking filter cycles in final track using own ship velocities in N, E, D to r, e, d Euler transformation angles sampled near the mid-point of the four-cycle period. Note that the direction D is the same as the vertical direction V, but opposite in sign.
FTS8, called with a BAL FTS8, 0 instruction, is entered every four-tracking filter cycles in Final Track Mode. Before calling FTS8, the following quantities must be stored in FT variable memory
1. V.sub.N.sbsb.1, V.sub.E.sbsb.1, V.sub.V.sbsb.1 -- own ship velocity components in N, E, V near beginning of the four-cycle period.
2. T.sub.INS -- time in seconds of the four-cycle period.
3. Sines and cosines of .phi..sub.i, .theta..sub.i, (.phi.+.phi..sub.G).sub. i, .epsilon..sub.i, .eta..sub.i -- Euler angles sampled near mid-point of the four-cycle period.
The computed own ship accelerations in antenna coordinates, a.sub.1.sbsb.r, a.sub.1.sbsb.e, a.sub.1.sbsb.d, are stored by the subroutine in FT variable memory.
The fundamental equations used by FTS8 to compute the components of own ship acceleration in antenna coordinates are: ##EQU41## where
V.sub.n.sbsb.2, v.sub.e.sbsb.2, v.sub.v.sbsb.2 = own ship velocity components in N,E,V near the end of the four-cycle period
and the other terms have been defined above.
The Single Axis Rotation Subroutine (SR) can be conveniently used to perform the successive 3 .times. 3 times 3 .times. 1 matrix multiplications required in the computations. Thus, to compute vector components in frame 2 which is rotated by an angle, .alpha., from frame 1, load sin .alpha. in R4, cos .alpha. in R6, and the two vector components in frame 1 in R1 and R2. Sr then computes:
R4 = r1 (cos .alpha.) + R2 (sin .alpha.) (126)
R5 = r1 (sin .alpha.) + R2 (cos .alpha.) (127)
Which frame 1 components are input in R1 and R2 and which frame 2 components are output in R4 and R5 can be determined from the matrix equations.
The return address in R0 is stored in FTV2400. The current own ship velocities from the I/o memory area are loaded into R4, R5, and R6 as V.sub.N.sbsb.2, V.sub.E.sbsb.2, and V.sub.V.sbsb.2, respectively. The velocities V.sub.N.sbsb.1, V.sub.E.sbsb.1, and V.sub.V.sbsb.1, valid four filter cycles ago, are loaded into R1, R2, and R3, respectively. Then, the current velocities V.sub.N.sbsb.2, V.sub.E.sbsb.2, and V.sub.V.sbsb.2 are stored in FT buffer cells as V.sub.N.sbsb.1, V.sub.E.sbsb.1, and V.sub.V.sbsb.1 to be used on the next call of FTS8. The velcoity differences are formed in R4, R5, and R6 with rescaling of the vertical difference to B12 and sign changing to make the down direction positive. The average own ship N, E, D acceleration components over the last four filter cycles are computed by dividing the velocity differences by the four-filter cycle time, T.sub.INS. T.sub.INS is cleared to initialize for the following cycle.
A series of five single axis rotation transformations are performed according to Equation (125) using SR as described above. The sines and cosines of the Euler angles transforming N,E,D to r,e,d, saved by FT near the middle of the four-cycle period, are used in this process. The final results, a.sub.I.sbsb.r, a.sub.I.sbsb.e and a.sub.I.sbsb.d, are stored in FT variable memory for use by the tracking filter over the next four filter cycles. The subroutine exits via the return address stored in location FTV2400.
Subroutine FTI illustrated in the flow diagram of FIG. 18 is the Filter Initialization Subroutine. Its purpose is to initialize those FT variables having non-zero values before the start of track. A common entrance is provided for all modes, with mode logic in FTI directing the program to the proper initialization computations. Results are stored in FT variable memory. It is called with a BAL FTI, 0 instruction.
Before the start of track, the Executive Routine (XT) clears the track data base. Thus, all FT variables and flags requiring zero initial values will be initialized by this process. FTI is called by XT to initialize those FT variables requiring non-zero values.
The range bin number, R.sub.T, and the filter hit number, F.sub.T, from acquisition, are loaded into R1 and R2, respectively. The initial track period, T, determined by XT, is loaded into R3, and the negative of the last computed own-ship ground velocity, V.sub.G, is formed in R6.
The range filter states and the velocity filter states are initialized according to the following equations.
R.sub.TPR = R.sub.BIN .sup.. [R.sub.T + 0.5]
V.sub.TPR = -V.sub.G
(a.sub.TPR = 0 by track data base clearing) (128) ##EQU42##
(a.sub.TPV = 0 by track data base clearing)
The initial gate commands are:
R.sub.GC = R.sub.TPR + T .sup.. V.sub.TPR
V.sub.GC = V.sub.TPV (129)
A set of a priori SNR's must be stored for use by the FT Routine during the first tracking period equal to a final track filter period for the operating PRF, since SNR' s from the SN Routine will not be available during this time.
The variable, N, is initialized at one and the flag used to select a gain of one for the first MPRF burst ranging is set. FTI exits via the return address stored in R0.
The Antenna Control Routine, AT, illustrated in the flow diagrams of FIGS. 19 and 20a--20d computes the desired antenna drive commands for roll, elevation and azimuth and outputs these commands to the antenna servo through the appropriate analog output signals. The entries to the AT Routine are listed below.
At called by XT near the middle of the current track filter cycle.
Ats1 called by XT to output analog values.
The flag, with its associated symbolic name, is listed below.
Atfo1 roll
the variables defined and used in the AT Routine are listed below.
Atv01
atv02
atv03
atv04
atv05
ftv2011
ftv2012
ftv2021
ftv2022
fig. 19 is a functional flow diagram of the routine AT shown in more detail in the flow diagrams of FIGS. 20a-20d. AT performs two analog inputs in the direct mode to obtain analog input word 10 (.theta..sub.d, azimuth error angle) and analog input word 11 (.theta..sub.e, elevation error angle) from a phase sensitive detector.
The current roll angle, .phi., input from the INS is used to determine whether to establish a stablized roll aspect angle at 0.degree. or 180.degree. in the following manner.
.cndot. The stabilized roll aspect angle is 0.degree. if,
.vertline..phi..vertline. .ltoreq. 70.degree. or
70.degree. < .vertline..phi..vertline. .ltoreq. 109.degree. and the previously established roll aspect angle is 0.degree. .
.cndot. The stabilized roll aspect angle is 180 degrees if,
.vertline..phi..vertline. > 109.degree. or
70.degree. < .vertline..phi..vertline. .ltoreq. 109.degree. and the previously established roll aspect angle is 180.degree. .
The shortest angular rotation to maintain the stabilized roll aspect angle (0.degree. or 180.degree. as determined above) is computed. This value is converted to a full scale of .+-.110.degree. and is output to the antenna servo (LVPS) as analog output word 5.
The analog input, .theta..sub.e (t+1), is used to compute the difference in elevation:
.DELTA..theta..sub.e (t+1) = .theta..sub.e (t+1) - .theta..sub.e (t) (130)
and the estimated elevation angle point error:
.epsilon..sub.P.sbsb.e (t+1) = K.sub.G .sup.. .DELTA..theta..sub.e (t+1) + .theta..sub.P.sbsb.e (t) (131)
where
K.sub.G = a constant
The desired elevation rate is computed:
.omega..sub.C.sbsb.e = .omega..sub.LSP.sbsb.e (t+1) + 15 [l.sub.e (t+1) + .epsilon..sub.P.sbsb.e (t+1)] (132)
where
.omega..sub.LSP.sbsb.e = the LOS elevation rate from the FT Routine
l.sub.e = an intermediate variable from the FT Routine
.omega..sub.C.sbsb.e = scaled to .+-.40 degrees/second at BO and is output to the antenna servo as analog output word 4.
The computation for the desired azimuth command rate proceeds in a similar manner, where the analog input, .theta..sub.d (t+1), is used to compute the difference in azimuth:
.DELTA..theta..sub.d (t+1) = .theta..sub.d (t+1 ) - .theta..sub.d (t); (133)
and the estimated azimuth angle pointing error:
.epsilon..sub.P.sbsb.d (t+1) = K.sub.G .sup.. .DELTA..theta..sub.d (t+1) + .epsilon..sub.P.sbsb.d (t). (134)
The desired azimuth rate is then
.omega..sub.C.sbsb.d = .omega..sub.LSP.sbsb.d (t+1) + 15 [l.sub.d (t+1) + .epsilon..sub.P.sbsb.d (t+1)] (135)
where
.omega..sub.LSP.sbsb.d = the LOS azimuth rate from the FT Routine
l.sub.d = an intermediate variable from the FT Routine
.omega..sub.C.sbsb.d = scaled to .+-.40.degree. /second at BO and is output to the LVPS as analog output word 3.
As indicated hereinbefore, the tracking system employing the present invention will have an initial and a final tracking phase, i.e., after a target has been acquired, the system utilizes two different track modes. The initial track mode is used to keep a target between the split gates used for range and velocity tracking while the Kalman filter gain inputs are being generated. A final track mode, which uses variable Kalman gains, produces improved tracking with parameter estimates accurate enough to satisfy mission requirements. The same type of discriminate data used by the initial track mode is averaged to produce the discriminate data for the final track mode. Thereafter, average of discriminate data in the final track mode produces measurements with less effective noise. The averaging period is selected to be compatable with the expected variations in target parameters. SNR data produced by averaging signal and noise measurements over a period compatable with their expected variation are used to set track filter gains. A technique for computing the SNR data will now be described in greater detail.
The magnitude of the target signal, S, is essentially measured by measuring the magnitude of whatever is present in the split-gated range bins or doppler filters as shown in FIGS. 21a and 21b, respectively. Since the signal measured in each range bin or doppler filter consists of both signal and noise, some adjustment to the measurement may need to be made to produce the best measure of signal. The magnitude of noise, N, would best be measured in each case after removing the target signal from the split-gated signals. However, this is impossible without removing some clutter which is one component of the noise present. Consequently, to obtain a measure of the noise, return signals are sampled in range bins or doppler filters on each side of the split-gated bins or filters and averaged. Wherever possible, these noise measurements are made by looking in range bins rather than doppler filters because jet engine modulation sidebands may put unwanted signals in the gated noise samples, thereby degrading the noise measurement. Therefore, when range gating is available, range bins are used for the noise measurement in computing the SNR for range, velocity, azimuth and elevation. For example, five cells on each side of the split-gated range bins may be sampled, added and then divided by 10 to form an average noise measurement, N.
Since a ratio, S/N, is required, an average signal measurement, S, must be obtained for the numerator in the case of each SNR. That is accomplished in the case of SNR.sub.RNG by obtaining the return signals sampled in the split-gated range bins, forming the sum S+2N, and then subtracting out the averaged noise component present. In other words, recognizing that the target will be in one of the two range bins, if the signal returns from the split-gated range bins are added, their sum wull be S+2N. If five range cells on either side of the split-gated cells are sampled and added to obtain a noise measurement, the average noise 10N/10 can be formed directly. To remove the component 2N from the signal to be used in the numerator, it is then a simple matter of subtracting two times the average noise signal. The new values of S+2N and N are obtained every 8.6 msec. At the end of a 34.4 msec. period, a smoothed estimate of the signal-to-noise ratio is formed from the four samples of S+ 2N and N by the computer 13a. The signal and noise samples are obtained from the channel of the radar receiver 11 which receives the sum (a+b+c+d) from the antenna.
The azimuth and elevation signal-to-noise ratios SNR.sub.d and SNR.sub.e are similarly computed by the computer 13a using as the numerator the signal S developed from the split-gated range bins because, while tracking on target, the azimuth signal (a+b) -(b+d) and the elevation signal (a+b) -(c+d) are being driven to zero. The develop an average noise signal, N, in the two azimuth and elevation channels, the computer 13a updates a running average of the signal amplitudes in the azimuth and elevation channels as sampled every 8.6 msec. At the end of a 34.4 msec. period, the azimuth and elevation signal-to-noise ratios are formed by dividing the signal, S, obtained from the range channel by the respective average azimuth and elevation noise signals developed from samples of the azimuth and elevation channels.
While the computer 13a is shown as receiving its inputs from the signal processor 13, it is recognized that the signal-to-noise ratio computation may actually be performed within the signal processor 13, or within the estimator 14 using the new raw data obtained from the signal processor 13 and processing the raw data with a stored subroutine. Alternatively, the various signal-to-noise ratios may be computed using analog techniques from the output signals of the radar receiver. Analog SNR signals could be sampled and converted to digital form at the end of every 34.4 msec. data accumulation period. Still other techniques will occur to those skilled in the art, particularly in a monopulse tracking radar system employing only two receiver channels, one for the range signal and the other time-shared for the azimuth and elevation signals. Consequently, it is to be understood that the present invention is not directed to techniques for computing the required signal-to-noise ratios, but rather is directed to using the signal-to-noise ratios however computed from signal measurements to adapt the tracking filters in the estimator for the noise environment of the return target signal.
To implement the foregoing routines, the radar data processor which carries out the functions of the estimator 14, i.e., of the tracking filters, and the controllers 15, 16 includes a digital computer which will now be described. That computer may also be used to carry out other system functions, such as the functions of the signal processor 13 and the radar controller 12. Consequently, the full capability of the computer will be set forth in sufficient detail to enable a programmer to not only provide the routines described but also provide other system function, i.e., to enable a programmer to adopt the present invention to a system having a particular environment and operating requirements.
The particular computer chosen for radar data processor is a Model HCM-231 Advanced Aerospace Computer designed and manufactured by Hughes Aircraft Company. It is called, simply, the "RDP" hereinafter. Basically a simplex (uni-processor) machine, the RDP possesses a number of advanced architectural features. These include the use of general purpose processor registers, half-word and full-word instruction types, a central address/data and control bus, system-wide addressing, a modular input-output system, and provisions for growth into a multiprocessor system.
The objective of the following is to describe those features of the RDP with programming significance and to present its instruction set. The description is intended to serve as a detailed reference document for both the application programmer and the computer requirements analyst.
The appendices include a summary of the instruction set in functional "arrow" notation, instruction listings ordered alphabetically and by opcode, a discussion of data transfers over the system main bus, and an explanation of the Read-Only Memory (ROM) subroutines.
The RDP is composed of standard and special purpose functional modules interconnected by a central address/data and control bus to provide maximum flexibility. It uses a modular structure that is capable of being modified and expanded readily if the necessity should arise. It provides considerable programming flexibility via an extensive instruction set that employs both full- and half-word instructions which operate on eight general-purpose processor registers (GPRs). Other aerospace features provided are a real-time clock register, an interrupt indicator register with priority decoding, and a fast-access processor local store. Data can be manipulated as 12-bit, 24-bit, 48-bit, or parallel 12-bit binary numbers in fractional two's complement form. Main memory is configured as one module with a capacity of 16K full-words, although the system could be modified to add other memory modules. The system inputoutput is completely modular to provide the greatest flexibility possible. It is assembled from standard input-output (I/O) building block modules.
The configuration of a chosen RDP is given in FIG. 22. It consists of the following major elements. A Processor Unit 200 that: fetches instructions, controls instruction execution, and fetches and stores information in a control section 201, performs arithmetic and logical operations in an arithmetic section 202, and provides fast access non-destructive readout (NDRO) storage for frequently used routines in an area called the local store or the Read-only Memory (ROM)203. A Main Memory 210 that consists of one 16K core module. A Central Communication Bus 211 and Bus Allocation Logic 212 that interconnects all RDP system units. An Input-Output (I/O) System 220 that consists of standard building block modules and special I/O units designed for the application. The special independent units are an interface unit 221 referred to as an "041 Special" a central control computer (CCC) multiplex terminal 222 referred to as a "CMUX", and a peripheral multiplex terminal 223 referred to as a "PMUX". Dependent units are a channel controller 224 and three supervised units; a discrete input unit 225, a discrete output unit 226 and an analog-digitalanalog converter 227 for analog input (AI) and analog converter 227 for analog input (AI) and analog output (AO).
I/O operations are accomplished in either of two modes: direct mode or buffered mode. Direct mode I/O, which is under complete program control, involves the transmission of data items directly between the I/O system and one of eight general purpose processor registers. Generally, one program instruction is required for each data item transfer.
Buffered mode I/O is accomplished by one of the I/O special units 221, 222 and 223 independently of the processor unit operation once and I/O transaction has been initiated. I/O transactions can be accomplished either by the execution of te PCW instruction or by an externally generated start command. Each transaction may involve a variable number of data items. The status of a transaction can be determined by the execution of an LCW Instruction that addresses the I/O control unit in charge of the transaction, except in the case of specially designed control units whose status cannot be sampled.
Each RDP module is categorized as either an independent or dependent unit in the drawings. Only independent units may initiate data transfer requests. All such requests are arbitrated by the bus allocation unit logic that assigns bus cycles to a unique (priority-selected) independent unit request. Requests may be addressed, in general, to other independent units or, more often, to one of the system dependent units, which respond to the request appropriately.
The operational structure of the RDP enables it to perform efficiently a variety of real-time general-purpose aerospace computational tasks:
a. Main Core Memory of 16K full-words, each full word containing 24 bits.
b. Half-word oriented addressing scheme to provide flexibility in half-word operations.
c. Word-oriented system-wide data transfer (24-bit word) for maximum hardware efficiency. (Memory and I/O locations are addressable and alterable by half-word, word, or double-word quantities.)
D. machine cycle time of 0.25 .mu.s for rapid execution.
e. Selective memory write protection for program instruction and constant security.
f. Eight 24-bit general purpose registers or GPRs (replacing specialized registers such as index registers, accumulators, M/Q registers, and data registers) to reduce program size and increase processor speed. Three GPRs are used as index registers, in addition to their general functions.
g. Four 24-bit working registers (WRs) to contain the following registers in program-addressable locations.
Program location counter register
Interval timer register
Priority-Decoder Interrupt indicator register
Interrupt mask bit register
h. Dual-addressing of GPRs and WRs so that all memory-addressing instructions (with or without address modification) can perform register-to-register operations for added programming power.
i. Fast access local store containing frequently used mathematical subroutines.
j. Direct addressing of 2048, 24-bit words (ranging over entire read/write scratchpad memory) without the need for indexing or indirect addressing to facilitate operations involving constants and data stored in memory.
k. Instruction address modification via indexing alone, multilevel indirect addressing alone, or multilevel indirect addressing with pre-and/or post-indexing at each level.
1. Immediate data-storing instructions for greater storage efficiency and increased speed.
m. Automatic error condition checking for arithmetic and shift overflows, division by zero, and illegal write addresses. Detection of any of these conditions triggers an interrupt that passes control to a user-written recovery routine. At the user's option, error conditions may be ignored by masking off selected interrupts.
n. Three-state condition code (less than, equal to, greater than zero) for complete six-condition branching flexibility; set by most load, arithmetic, logical, and shift instructions.
o. Power transient sensing and program shut-down capability via hardware interrupt.
p. Program monitoring via watchdog timing logic and interrupt to provide program error detection and recovery capability.
q. I/O interrupts to indicate status of I/O operations and to provide I/O system control.
r. Complete, powerful instruction set, including
Half-word and full-word instructions
Half-word, parallel half-word, word, and double-word arithmetic operations
Multiple register transfer instructions
Complete set of logical operations (And, Exclusive and Inclusive Or, One's and Two's Complement)
Comparison operations
Shift operations: right, left, and circular-single or double word -- arithmetic or logical; single word normalize
Branch addressing ranging over main memory directly without need for address modification
Extensive register-to-register instruction subset
Programming the RDP involves some understanding of its data structures and storage allocation, the basic processing elements, its instruction types and address computation techniques, and the operation of its interrupt system. The details of organization and operations that are commonly required to program most efficiently may be grouped into four major areas: data formats and storage allocation; processor; instruction formats and instruction address formation; and interrupt system.
Referring first to data formats, data in the RDP system can be represented as full-word, half-word, or double-word elements. The appropriate formats are presented below, followed by a discussion of data information boundaries.
Full-Word -- The basic data element in the RDP is a 24-bit word. Bit positions within a word are numbered 0 through 23 as follows, and bit position 0 is reserved for the sign (S).
Half-Word -- An RDP 24-bit word can be divided into 12-bit half-words. Bit positions are numbered 0 through 11 for both half-words; the left half-word has an even systemaddress, and the right half-word has the next higher odd system-address. Again, bit positions numbered 0 are reserved for the sign (S).
The left and right half-words may be unrelated; however, together they may form a parallel half-word operand, and two arithmetic operations may be performed concurrently using two pairs of parallel operands.
Double-Word -- Two RDP words can be combined to form a 47-bit double word. Bit positions are numbered 0-23 for the most significant half plus sign in bit position 0, and 24-46 for the least significant half. Bit position 47, the least significant bit of the second word (normally numbered 23) is not used, i.e., in double-word operations, the contents of Bit 47 are unpredictable.
Data in any length format can be either arithmetic or non-arithmetic. Whenever arithmetic data are stored in the RDP, the fractional two's complement number system is used with the sign bit appearing in the positions numbered 0 in each data format. In a fractional data representation scheme, data values can range only from -1 to +1. The binary point is understood to be located immediately after the sign bit.
The system has certain restrictions to the positioning of data items relative to the full-word storage location boundaries. Basically, data item boundaries must align with full-word boundaries. The restriction reflects the full-word data fetching by the processor; whenever a half-word quantity is required, the full-word containing it is accessed and the processor retains the required half-word. These restrictions are not a serious inconvenience since data types are usually grouped together for maximum storage allocation efficiency.
The RDP system-wide address structure facilitates modularity, flexibility, and instruction set effectiveness by providing each storage location with an address on a common address continuum. Basically, all storage locations have a system address, whether they are physically in the processor, main memory or input/output system. Further, storage locations external to the computer system can be assigned and referenced by system addresses, requiring only that these locations are provided with an interface connection to the main bus. Up to 8,389,000 full-words (16.8 M half-words) locations can be referenced. Access to this wide range of storage locations is accomplished through the use of a 24-bit system address, which is transmitted over the 24-bit bus also used for parallel data transmission.
FIG. 23 contains the RDP storage allocation assignments. Because of the half-word instruction and data word capabilities, RDP addresses are expressed in half-words. The first 256 addresses (octal locations 0-377) reference the general purpose registers, working registers, and local store locations. Although the processor registers also have short, three-bit addresses normally used in instruction words the auxiliary system address allows instructions which nominally utilize an operand in memory to also specify one in a processor register; this capability enhances the power of the instruction set since, for example, an exchange of two registers can be accomplished by the same instruction used to exchange the contents of a register with those of a memory cell.
The RDP processor can, however, be operated in a mode where the first 256 addresses reference main memory locations instead of processor locations; in this case read or write requests with addresses in this range are sent out over the main bus rather than satisfied within the processor. In FIG. 23, the first 256 main memory half-word locations can (only) be referenced in this mode. Special control instructions (SCP and SCM) are used to change processor addressing modes and thereby lock or unlock this block of privileged memory cells.
The rest of the main memory locations in FIG. 23 are addressable in either processing mode. They are partitioned into read/write scratch pad and read only parts, by the memory interface logic; an attempted write into the read only portion is denied and an interrupt transmitted to the processor. Note that part of the scratch pad has been dedicated to the storage of interrupt information.
The I/O system addresses in FIG. 23 are disjointed from, and numerically higher than, those of the processor and main memory. Many of the potential I/O addresses are spares.
The RDP contains certain basic storage elements whose contents or state are directly affected by the program instructions. These elements are discussed below and are depicted in FIG. 24.
The control section 201 is composed of four working registers, control bits used for enabling the tactical interrupts and controlling low-order memory address references, and the instruction execution register -- plus other logic necessary to fetch instructions and operands as well as sequence the processor unit.
Each working register is dedicated to a specific function:
Program Instruction Register (Working Register O) that is functionally 18 bits in length. It is used to hold the address of the instruction currently being executed.
Interval Timer Counter (Working Register 1) that contains a 24-bit count of clock timing pulses. Both the timing pulse frequency and effective count size (within 24 bits) have wire-wrap options.
Interrupt Indicator Register (Working Register 2) that contains the set of priority-ordered interrupt indicators. Bit position 0 corresponds to the highest priority indicator; lower priority indicators are assigned to increasing higher numbered bit positions.
Interrupt Indicator Mask Register (Working Register 3) that contains the mask bit corresponding to the interrupt indicator register in the same relative bit position.
The instruction execution register contains either the left-most half of full-word instructions or entire half-word instructions. Normally, it receives instructions from the processor look-ahead unit (not shown) and not directly from storage.
The arithmetic section 202 consists of eight 24-bit general purpose registers, a 2-bit condition code register, a 24-bit instruction address/operand register -- as well as an adder, auxiliary processor register, and the necessary gating and logic to execute instructions and perform address modifications.
A subset of the general purpose registers, registers 1 through 3, may be used as index registers. Otherwise, they are used exactly as the others; i.e., as accumulators, temporary data storage locations, fast-access storage for short instruction sequences, etc. Address indexing is accomplished by adding the index register contents to the instruction immediate address, that is obtained from the instruction address/operand register.
The 2-bit condition code register CC.sub.2 indicates the magnitude relative to zero (less than, equal, or greater than) of a particular data item; complete conditional branching is achieved through interrogation of this register. Thus if a branch on non-equality is desired, it will be allowed if the condition code register is in either the less than or greater than state. The allowed states of the condition code register are defined below.
In addition to the foregoing storage elements, there is a special 112-word block of fast access read-only memory designed to hold ROM subroutines.
As in most digital data processing systems, the RDP consists of a set of hardware units that can operate concurrently and that time-share a central communication bus. This organization provides a modular structure that allows the RDP to be tailored to application requirements to be easily augmented if the system needs upgrading during its life span. The modular organization also provides executional speed advantages. For example, operations such as an analog-to-digital conversion, a multiplexed digital output, an arithmetic instruction, and a fetch to memory of the next instruction can all be in progress concurrently.
As a result of this organization, however, the execution time for each individual instruction as well as for entire program segments is affected by several factors that are as follows. The value of each address (computed from the instruction address field, index register contents, and indirect address words) determines which unit contains the desired operand. Each unit in general has a unique access time. Since each unit possesses a fixed priority for bus cycles, the time required to secure the bus depends upon the concurrent requests from the other units. Once bus usage is secured, the time required to process the request depends on the requested unit's status; if concurrently busy, the request must be repeated when the unit is again idle. The previous program instructions and the corresponding system events affect the status of the next instruction look-ahead process. This process determines the actual instruction fetch time delays and also makes memory cycle requests concurrent with normal instruction execution. To aid in the preparation of RDP programs, typical execution time ranges for each instruction are given in Appendix A which sets forth a table of the RDP instruction set.
The RDP interval timer (working register 1 also known as "real-time clock") consists of a 24-bit binary counter that is automatically incremented by unity at the selected rate. The interval timer can be consulted and also set to any desired value by the program. Whenever the interval timer register overflows, an interrupt indicator is set. This device is primarily a means for imposing accurately determined time limits without requiring programmed clock watching.
Associated with the interval timer is some special logic known as the "watchdog timer." This logic monitors the time elapsing since the occurrence of the last interval, the logic generates an overriding (catastrophic) interrupt to indicate that a program error has occurred.
The interval timer is implemented as one of the RDP working registers, since it possesses both a 3-bit working register address and a syste-wide address. Thus, the register count can be "read" via any Load instruction and altered with a Store, Add-to-Memory (ATM), Exchange (X), Selective clear-to-working registers (CSW), or Or-to-Working Register (OW) instruction. The preferred technique for resetting the timer to overflow periodically is to execute an ATM instruction whose system "memory" address is that of the timer register. The two's complement of the period to be timed, measured in counter timing pulses, is the quantity to be added. The number of pulses elapsing since the last overflow is already contained by the timer; therefore, when the period complement is added a clock overflow will occur as desired. Resetting in this manner is error proof; if a timing pulse occurs during the ATM instruction execution, its increment is automatically delayed until the completion of the instruction execution.
The occurrence of an interval timer overflow enables the watchdog logic. This logic is disabled (turned off) by any program alteration of the timer contents. If no such "timer maintenance" is performed before 2.sup.12 clock pulses are generated, the timer register will overflow into bit position 11. When this occurs, the "watchdog interval" has elapsed and a watchdog interrupt is triggered (i.e., the watchdog timer interrupt indicator bit in WR2 is set). The watchdog interval is approximately 33 milliseconds (2.sup.12 pulses .times. 8 microseconds per pulse). Note that the execution of an ATM instruction, primarily to reset the interval timer, will also reset the watchdog logic.
There are 92 different RDP instructions. The instructions utilize 13 format types; these are presented in FIG. 25. Here, R is used to denote a general purpose register via a 2 or 3-bit processor address; superscripts are used to indicate the usage by the instruction of the register. An asterisk (*) is used to denote the indirect addressing flag, indicated by a 1 in bit position zero whenever this option is desired. The letter m is used to denote an instruction immediate address field; if neither indexing nor indirect address modification is utilized, this address becomes the instruction's final effective or global effective address. The letters y and I denote 12-bit or 3-bit immediate data operands, respectively; they are treated as signed, two's complement numbers where the sign bit occupies the most significant (leftmost) bit position within the operand field. Additional instruction format notation is explained in the figure.
The RDP instruction formats are of two basic types -- half-word and full-word -- that differ in their memory storage requirements. Most half-word format instructions (except the AGE instruction) involve operations that affect registers or control bits located within the Processor and utilize the short processor addresses for these purposes. Full-word format instructions typically affect a general purpose register and can also form system-wide addresses for operands as well. The specific formats are discussed briefly below.
Half-word instructions are used whenever possible since they require half the storage and execute more quickly than an equivalent full-word instruction. The RDP employs four half-word instruction formats: (1) RR (Register-to-Register) used by half-word instructions involving two general purpose registers, (2) RO (Register Operation) used by half-word instructions involving one general purpose register, (3) CO (Control Operation) used by half-word instructions that alter control bit states, (4) AGE (Aerospace Ground Equipment) used exclusively by the AGE instruction.
Full-word instructions provide system-wide addressing capability and maximum operation versatility. Though usually employed to reference memory or I/O system operands, they can also be used to advantage as powerful general purpose register instructions, referencing the registers via their system addresses. Nine full-word formats are used as follows:
1. RM (Register Memory) -- Used by instructions involving a general purpose register and an operand stored anywhere within the system.
2. LA (Long Address) -- Used by three branching instructions to directly address the total memory system.
3. BC (Branch Conditionally) -- Used by six conditional branch instructions to directly address the total memory system.
4. MM (Multiple Memory) -- Used by multiple-word data transfer instructions.
5. IA (Immediate Operand) -- Used by 3-bit immediate-operand storage instructions.
6. IY (Immediate Operand) -- Used by 12-bit immediate-operand storage instructions.
7. SH (Shift) -- Used by most shifting instructions.
8. BIT (Built-in Test) -- Used exclusively by the BIT instruction.
9. LCW (Load Control Word) -- Used exclusively by the LCW instruction.
The address modification facilities of the RDP are extremely powerful; direct addressing, indexed addressing, multilevel indirect addressing, and multilevel indirect addressing with indexing are all available. The complete range of system-wide addresses (8.4 million words) can be formed by any indexed address; indirect addresses include, without indexing, over 131,072 words. Each form of address modification is discussed below. All addresses extend to the half-word level.
Three terms are used in connection with RDP instruction address formation: (1) immediate address -- the address contained within an instruction or indirect address operand address field; (2) local effective address -- the address formed, at any addressing level, by the sum of an immediate address and the contents of an index register, if specified; and (3) effective or global effective address -- the final address determined by the instruction address modification process. In the case of direct addressing, the immediate address becomes both the instruction's local and global effective address. This address has a range of 2048 full words for most memory addressing instructions; branch instructions directly range over 16,384 full words.
Most memory-addressing instructions may specify an index register, designated as R.sup.x, whose contents will be added to its immediate address to form the instruction's global effective address. Such an address is 24 bits in length and can range over 8.4 million words. General purpose registers 1, 2 or 3 may be designated as an index register via the corresponding 2-bit binary address. (An address value of 00 indicates that indexing is not desired; thus, general purpose register 0 cannot be used as an index register.)
Indirect address formation is specified by setting the indirect address flag bit (bit position 0 denoted in an instruction format by an asterisk) to one. In this case, the instruction's local effective address locates or points to an indirect address operand word stored within the appropriate addressing range. The contents of this word appear in the following format:*R.sup.x E CC m0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Here, the fields of bit positions 1, 2 and bit positions 6-23 for R.sup.x and m respectively have the same meaning as in instruction formats. The CC and E fields (bit positions 4, 5 and bit position 3, respectively) are used during system interrupts to store the processor condition code and tactical interrupt enable status. In indirect addressing, the CC and E fields are not interpreted, unless the instruction is a B, BCT, or BAL instruction. In this case, the CC field is examined and if it contains zeros, no CC or E change is made. If the CC field is non-zero, then the CC register is set to the state corresponding to the CC field value and the Tactical Interrupt (TI) flipflop set to the value of the E field.
The interpretation of the local effective address depends upon the state of the indirect address word flag bit; it is set to 1, the indirect address operand's local effective address points to a second indirect addressing level. Succeeding indirect address levels are processed until an operand whose flag bit is set to 0 has been fetched. The local effective address of this final operand becomes the instruction's global effective address.
Indexing can be employed at any level of indirect addressing -- either in forming the indirect operand's address (pre-indexing) or in forming that operand's local effective address (post-indexing). When post indexing is used, an addressing range of 8.4 million words results; if not, the addressing range becomes 131,072 words.
Subroutines normally are entered by executing a Branch and Link (BAL) instruction, which places the calling program's return address in one of the first four general purpose registers (0 through 3). If registers 1 through 3 are used, a return from the subroutine can be accomplished through either indexing or indirect addressing techniques; if register 0 is specified, indirect addressing must be used. See the BAL instruction description in for specific calling sequences.
The RDP allows for a maximum of 24 interrupts, with hardware priority decoding and nesting. Interrupt signals set individual bits (called interrupt indicators) that are subsequently cleared by the programmer. Each interrupt signal consists of either a DC level or a pulse of at least 1 .mu.s duration. Interrupt indicator bits may also be set directly by the program, a capability useful in executive control routines and system test modes. The indicator bits are retained in the Interrupt Indicator Register (Working Register 2). The highest priority indicator is located in the register's sign bit position, and the others are located in succeeding bit positions in order of decreasing priority. Each interrupt, with the sole exception of the watchdog timer interrupt, can be selectively masked or unmasked via a mask bit in the associated interrupt mask register (Working Register 3). The mask bits in Working Register 3 correspond, bit position by bit position, to the interrupt indicator bits in Working Register 2.
The RDP interrupts are divided into two classes: catastrophic and tactical. Catastrophic interrupts have inherently higher priority than tactical interrupts, though each system interrupt possesses a unique priority level. The following table illustrates the current RDP interrupt system configuration. Three standard catastrophic interrupts are indicated. In order of decreasing priority, these are watchdog timer (unmaskable), power on, and power transient detection. In addition, a spare catastrophic interrupt indicator is available if needed later.
__________________________________________________________________________INTERRUPT BITPRIORITY POSITIONS FUNCTION CLASS__________________________________________________________________________0 0 Watchdog Timer CatastrophicSpare- 1 Catastrophic2 2 Power On Catastrophic3 3 Power Transient Catastrophic4 4 Arithmetic Anomaly Tactical5 5 Illegal Write Request Tactical6 6 Interval Timer Overflow TacticalSpare- 7 Tactical8 8 MRM Launch Command Tactical9 9 Processing Pulse TacticalSpare- 10 TacticalSpare- 11 Tactical12 12 RSP (039) Crowbar Fired Tactical13 13 RSP (041) Crowbar Fired Tactical14 14 A/D/A Conversion Complete Tactical15 15 RSP Data Transmission Tactical Complete16 16 RDP Multiplexer Transmission Complete Tactical17 17 CCC MUX Transmission Complete TacticalSpare- 18 Tactical19 19 RDP MUX Data Error TacticalSpare- 20 TacticalSpare- 21 TacticalSpare- 22 TacticalSpare- 23 Tactical__________________________________________________________________________
Priority Interrupt Assignments
Each interrupt level has a unique priority assignment and two dedicated full-word memory locations.
All other system interrupts (up to 20) are classified as tactical interrupts. Three are standard: arithmetic anomaly, illegal write request, and interval timer overflow. Interrupts required by the tactical application are added to these. As illustrated in the figure they include interrupts from I/O system modules indicating the completion of I/O data transmission tasks and interrupts originating externally in other avionic subsystems or computer system control panel.
The program exerts control over the interrupt system in three basic ways:
1. At each interrupt level, the interrupt mask bit can be set or reset, thereby affecting the system response to a set indicator.
2. All interrupts are temporarily disarmed for the two instruction execution times following a DSIM (Disable Interrupts Momentarily) instruction. These interrupts are also disarmed temporarily following the alteration of any working register contents by the system.
3. The tactical interrupts as a class can, at any time, be enabled or disabled via the ENT (Enable Tacticals) and DST (Disable Tacticals) instructions. These instructions set and reset a processor control bit. Upon interrupt recognition, the status of this bit is saved (to be restored following the interrupt subroutine execution) and is automatically set to the disable position.
Two memory cells, the interrupt's A and B words, are associated with each interrupt level. An interrupt's A word contains the 18-bit address (right justified in the 24-bit memory word) of the first instruction in the subroutine servicing that interrupt. It's B word provides storage space for an indirect address operand word, which is packed by the control unit at the time of interrupt recognition. It retains the interrupted program's resume location in the operand's address field, and the condition code register and tactical interrupt flip-flop status before the interrupt in the operand's CC and E fields, respectively. The A and B words are located sequentially in memory, and the A word has the lower numerical address.
RDP interrupt recognition is contingent upon various factors that are functions of external signals, program-set control bits, and the processor status. Catastrophic interrupt recognition differs only in that the tactical enabled condition is not required.
An interrupt level becomes set upon receipt of (1) an external interrupt sign or (2) an equivalent program initiated action. While the first such action results in setting the interrupt indicator bit, subsequent interrupts cannot be retained until the bit has been reset. When the tactical interrupts are disabled, none will be recognized even if all other conditions have been met. However, interrupt signals can be accepted and remembered in the disabled state. In the tactical interrupt enabled state, recognition becomes a function of individual interrupt level indicator and mask bits, and the processor state. Interrupt signals are accepted and remembered.
When an interrupt level is masked, a set indicator, if present, is not permitted to cause an interrupt. As before, interrupt signals are accepted and remembered. In the unmasked state (assuming also the enabled state) an interrupt level is effectively in a waiting state. Whenever an interrupt signal at this level is received, it will immediately be considered for recognition by the processor.
A set interrupt indicator, currently unmasked and enabled, is recognized by the processor when: (1) the interrupt system is armed, (2) the processor is between program instruction sequences, and (3) the interrupt has the highest priority among all interrupts with the same status. The processor then executes an interrupt control sequence, described in the next topic, and branches to the interrupt servicing subroutine. The interrupted program location, together with the status of the processor's condition code and tactical enable bit, are stored in the dedicated memory word. If use of general purpose or working registers is required by the interrupt subroutine, their current contents should first be saved and subsequently restored as required by the subroutine. An interrupt indicator bit, once set, is reset by the program; usually by the interrupt-servicing subroutine.
During the execution of an interrupt routine, the tactical enable control bit may be set by an ENT instruction. This action permits the interrupt-servicing subroutine itself to be interrupted by another tactical interrupt, if one is present that meets the other criteria. Thus the urgent portions of an interrupt can be processed first without delay and the remaining portions completed only when other interrupts (selectable through masking) have been recognized.
Programmed interrupt indicator setting can be used to advantage in certain forms of executive program control. For example, tactical interrupt levels can be assigned to each of the avionic program iteration rates, with the higher rate routines given higher priorities. An executive routine, controlled by a periodic interrupt, sets program interrupt indicators as the appropriate iteration rate; following its completion, control is passed to avionic programs in order of their relative urgency.
During the execution of tactical programs, errors may occur that either result in the generation of an unrepresentable operand (as with an arithmetic overflow) or in a program "hang-up". Since such occurrences can be a function of variables obtained from the I/O system, or of a spurious noise signal, they may not be detectable before their actual appearances in real time. The RDP system provides hardward detection of several such executional errors and subsequently sets an appropriate interrupt indicator bit.
If the RDP program enters an infinite loop or halts unexpectedly, control is regained via a catastrophic watchdog interrupt. This (unmaskable) interrupt is generated by special logic associated with an interval timer clock; see "Use of the Interval Timer" for further details on its operation. The exact interval elapsing between the occurrence of the error and the generation of the watchdog interrupt is subject to variation, though in most cases it will be less than the interval timer capacity.
Several arithmetic anomalies may occur that result in the setting of a tactical interrupt indicator. These anomalies occur when an operation result cannot be represented correctly as a fractional two's complement number, i.e., in the range (-1) through (+1 - 2.sup.-.sup.23), inclusively. Three specific anomalies are detected by the RDP processor; (1) overflows resulting from an addition or subtraction instructions, (2) saturated quotients resulting from any division instruction involving a dividend whose absolute value exceeds that of the divisor, or equals the divisor if the dividend and divisor are likesigned, and (3) overflows resulting from a left-shift operation in which the operand's sign bit value was changed during the shift. In all cases, the condition code register value after the anomaly is interpreted as follows.CC1 CC2 MEANING______________________________________0 1 Result after overflow is negative1 0 Result after overflow is zero1 1 Result after overflow is positive______________________________________
Note that overflow singularities resulting from two's complement absolute value, or multiply instructions are not detected. These result when (-1) is used as the operand or operands.
If a write request (resulting from a store, exchange, or add to memory instruction) is generated that addresses a read-only memory cell, it is detected by the memory addressing circuits that in turn set an interrupt indicator. The write request is not allowed.
If the processor attempts to execute a non-existent instruction (i.e., one with a non-used op code combination), an effective no-operation is performed. This condition is not formally detected, and the next program instruction is then executed.
The RDP input-output system interfaces directly or indirectly within the processor via the main bus system of the computer as noted hereinbefore with reference to FIG. 21.
RDP I/O operations are accomplished in either of two modes: direct mode or buffered mode. Direct mode I/O, which is under complete program control, involves the transmission of data items directly between the I/O system and one of the eight general purpose processor registers. Generally, one program instruction is required for each data item transfer.
Buffered mode I/O is accomplished by one of the I/O special units 221-223 in FIG. 22 independently of the processor unit operation once an I/O transaction has been initiated. I/O transactions can be accomplished either by the execution of the PCW instruction or by an externally generated start command. Each transaction may involve a variable number of data items. The status of a transaction can be determined by the execution of an LCW instruction that addresses the I/O control unit in charge of the transaction, except in the case of specially designed control units whose status cannot be sampled. The functioning of the I/O units are described in detail, but first the I/O system address formats and the definitions of various control parameters appearing in thse formats are presented.
Input-output operations, either direct or buffered modes, involve the transmittal of address words to I/O units. In addition, a controlled word is usually required by the special units during buffered mode operation. The two I/O system address formats that apply to both I/O modes are given here. The formal definition of all I/O system control parameters as used in address words or control words is also included.
The RDP system addressing philosophy is to provide unique addresses for all I/O registers and memory locations. As such, an "I" bit (number 6) in the address structure separates I/O addresses from memory addresses. (I=0 for all memory addresses and I=I for all non-memory addresses including the control words).
The two basic I/O address formats and the main memory address format for reference are given in Appendix A. One address is used for dependent I/O units (such as channel controllers) and the other for independent units 221-223. The positions and required states of various control parameters are shown. Control bit state combinations other than those given are undefined and thus result in illegal system addresses. In all addresses the first 4 bits (numbers 0-3) are reserved for system-wide addressing whenever more than one computer system is connected. These bits will be 0000 for all local addresses in the RDP application.
The control bit C (number 4) is set to 1 for all control word addresses and to 0 for non-control word addresses such as the memory and other dependent unit addresses.
Various I/O control parameters are required to designate the proper response to an I/O request. The values of the particular control parameters required in a data transmission are specified in the address or control word transmitted to the I/O unit over the address/data bus. Those I/O control parameters that are used in one or more of the standard RDP I/O formats are defined in Appendix A. Most control parameters are used either in address words or control words (not both) and apply to only those formats in which they are specified.
There are three I/O address word formats -- the main memory address format, the dependent unit address format, and the independent unit address format.
Because of the system-wide nature of addressing in the RDP architecture, all instructions that can form an effective address specifying 18 or more of the 24-bit full system address can reference locations in the I/O system. Fully 38 of the 92 instructions in the RDP instruction set have this capability. Specifically, they are the instructions that utilize the RM, MM, LA, and IA instruction formats. Thus, no special I/O instructions are required to perform direct mode I/O operations. The instructions that can reference an operand in the I/O system are as follows.
__________________________________________________________________________MEMORY-REFERENCING INSTRUCTIONS__________________________________________________________________________Instruction Name Instruction Name__________________________________________________________________________(Input) (Arithmetic)L Load A AddLH Load Half AH Add HalfLE Load Right AD Add DoubleLD Load Double AP Add ParallelLM Load Multiple AIM Add Immediate to Memory(output) S SubtractST Store SH Subtract HalfSTH Store Half SD Subtract DoubleSTR Store Right SP Subtract ParallelSTD Store Double M MultiplySTM Store Multiple MH Multiply HalfSTI Store Immediate MT Multiply TruncatedSTHI Store Half D Divide Immediate(Logic) (Miscellaneous)N ANDO OR B Branch UnconditionalE Exclusive OR BAL Branch and LinkC Compare BCT Branch on CountCB Compare Bits X ExchangeCH Compare Half PCW Place Control Word__________________________________________________________________________
Most of the direct mode I/O operations probably will be accomplished by those data transfer instructions listed under input and output. These instructions are executed exactly as when a memory location is specified; the I/O system location involved is selected by the instruction effective address. The condition code register is also set or not set just as before.
To perform input and output data operations directly between the RDP arithmetic and control unit and the I/O system, the effective address must be generated and transmitted on the address/data bus in the format (1) given below:
S.A. C T I P Channel Con-0 0 0 0 X 0 1 1 troller No.______________________________________0 1 2 3 4 5 6 7 8 9 10 11controlbitsSubchannel S M Word No. HNo. 0______________________________________12 13 14 15 16 17 18 19 20 21 22 23______________________________________
where
S.a. = a "global" system address. Always 0 for RDP.
C = control Bit
C=1 for control word addresses
C=0 for non-control word addresses such as the memory.
T = terminate bit. Not used in RDP.
I=1 indicates an address outside main memory
I=0 for all memory addresses.
P=1 indicates a Channel Controller and not a special dependent unit (none in RDP) address.
Cc no. = Channel Controller number. Since there is only one in the RDP, it is always 0.
S/c no. = Subchannel number. For the A/D/A converter,
S/c = 0 and for both the DI and DO modules
S/c = 1.
s = spare. Always 0.
M = ai mode bit. Always 0 for AO's, DI's and DO's.
Word No. = Word Number.
H = least significant address bit
H = 0 ai's and AO's
H = 1 for DI's and DO's.
The address in format (1) can be formed in one of three ways: indexing, indirect addressing, or both. In indexing, one of three general purpose registers (No. 1, 2 or 3) would be loaded with an address operand directly in format (1 ) before execution of the actual I/O instruction. The effective address computed for the I/O instruction would be the sum of the index register contents and the instructions 12-bit immediate address field (right adjusted). The immediate address ranges over the I/O subchannel address, subchannel word number, and half-word address bit.
If an indirect addressing chain is used to form the effective I/O address, each indirect address operand obeys the standard format. As usual, indexing may be employed at any intermediate level if desired.
If a combination of indirect addressing and indexing is used, the indirect address operand is defined. Note that if an instruction uses (UNK3) as an indirect address operand, the final effective I/O address is the arithmetic sum of bits 6-23 of (UNK3) concatenated with six leading zeros, and the 24-bit contents of the specified index register (non-zero, 2-bit address in the X-field of the following format (2).
______________________________________0 1 2 3 4 5 6 7 8 . . . 23X.sub.(UNK3) = 0 0 0 0 1 1 0 . . . 0 10______________________________________
where R.sup.X is specified as a post index. Thus, if R.sup.X is loaded via an LI instruction, where the immediate field is the desired S/C No., M, Word No., and H bits, an indirect operation using (UNK3) will result in the correct address generation. Note that indexing is mandatory when using (UNK3). No restrictions need be placed on the index register or indirect address operand contents (any control bit or address field can be altered), but care should be exercised to insure that a legal I/O address results with all possible values of the parameters used.
The Channel Controller 224 of FIG. 22 is one of two dependent units in the RDP system, the other being the main memory. The Channel Controller services three subchannel (S/C) units 225, 226 and 227. The processor can communicate directly with the Channel Controller with any instruction that can specify indirect addressing. The input and output data associated with the Channel Controller can be thought of as existing in a "virtual" memory, with each word of data having a unique (system) address. To obtain input data (DI or AI), the processor would typically execute a load type instruction with an effective address outside of main memory and equal to the address of the particular input word desired. To set output data (DO or AO), the processor would typically execute a store type instruction with again the proper effective address. The general format of the 24-bit address required to address the Channel Controller in the RDP is shown in format (1) above; it can be formed using either indirect addressing, indexing or both.
The AI's and AO's exist in "virtual" (I/O) memory as left half-words, each with sign and 11 bits of significance. An AI can be requested with any instruction for which the processor issues a read request (except ATM and AIM). Similarly, an AO can be set with any instruction for which the processor issues a write request. As indicated in the first paragraphs of this discussion, AI's and AOs will be addressed by first loading R.sup.2 and then executing the appropriate instruction with indirect addressing to (UNK3), i.e.,LI, 2 Y(operation) (UNK3) The value of Y required for the various situations is shown below.
__________________________________________________________________________ 12 13 14 15 16 17 18 19 20 21 22 23 S/C Number S M Word Number H__________________________________________________________________________Indirect AI (No Wait) .fwdarw.0 0 0 0 0 0 X X X X X 0Direct AI (.about.50.mu.s Wait) .fwdarw.0 0 0 0 0 1 X X X X X 0AO .fwdarw.0 0 0 0 0 0 X X X X X 0__________________________________________________________________________
The S/C and Word Number addresses for AI's and AO's are not mutually exclusive; the decision to do an input or output is determined by the Channel Controller from the message type lines (read request or write request, respectively) which are set by the processor from the instruction type. The logic permits expansion to 31 AI's and 32 AO's, but currently there are about 20 AI's and 9 AO's. AL 00000 is specifically reserved for 0 volts (ground) for internal use. Full-word load instruction AI requests will result in zeros in the right half of the destination GPR. For full-word stores AO transmittals, the output data must be in the left half of the source GPR.
AI requests may be in one of two forms: Indirect or Direct conversions, depending on the state of bit 17 in the address. If bit 17 is 0, the AI data returned to the main bus and the processor are the result from the prior conversion request, after which a new conversion is initiated for the AI addressed. The purpose for the Indirect capability is to eliminate the loss of processor time resulting from the AI conversion time. To request a specific AI, therefore, requires two "Indirect" type of load instructions. The first AI instruction requests the desired AI when the returned data are ignored. After an ADA completion, a second AI instruction retrieves the desired data. If a "round robin" sequence of AI requests were to be executed, i.e., if each AI request addresses the next AI desired, only one instruction per AI (after the first) would be required.
The other AI option is the "direct" conversion for which bit 17= 1. The data returned for a direct request are for the AI addressed by the instruction; however, the processor is stopped until the conversion is completed. The direct instruction requires .about.50 microseconds. On indirect AI sequences, the program should normally wait for an ADA interrupt before issuing another AI instruction. It is strongly recommended that programmers do not "stack" I/O and that, before every AI or AO transactions, they check the ADA completion indicator (w2, bit 14) or otherwise ascertain that a known adequate time period has elapsed since the last transaction.
Important statistics for AI's and AO's are summarized below.
______________________________________Conversion Word VoltageTime Size Range Resolution______________________________________AI's .about.50.mu.s 11 bits + sign .+-. 10 V 5 mvAO's .about.66.mu.s 11 bits + sign .+-. 10 V 5 mv______________________________________
The DI's and DO's exist in virtual (I/O) memory as right half-words. They can be addressed by any of the memory-referencing instructions listed above (except ATM, AIM, and those under "Miscellaneous"), especially those listed under Input (for DI's) and those listed under Output (for DO's). The addressing will be accomplished by first loading R.sup.2 and then by using (UNK3) as described earlier. The virtual memory picture for the DI's and DO's, and the value of Y required for each word, is shown in the following table.
__________________________________________________________________________"Virtual" Memory Value of Y Subchannel S Word No. H0 11 12 23 12 13 14 15 16 17 18 19 20 21 22 23__________________________________________________________________________0 0 0 0 WDO 0 0 0 1 0 0 0 0 0 0 0 10 0 0 0 WD1 0 0 0 1 0 0 0 0 0 0 1 10 0 0 0 WD2 0 0 0 1 0 0 0 0 0 1 0 10 0 0 0 WD3 0 0 0 1 0 0 0 0 0 1 1 10 0 0 0 WD4 0 0 0 1 0 0 0 0 1 0 0 10 0 0 0 WD5 0 0 0 1 0 0 0 0 1 0 1 10 0 0 0 WD6 0 0 0 1 0 0 0 0 1 1 0 10 0 0 0 WD7 0 0 0 1 0 0 0 0 1 1 1 1__________________________________________________________________________
Note that the addresses for DI's and DO's are identical for a given word number because the processor interprets, and informs the Channel Controller, that loads and other memory read type instructions are DI requests and that store type instructions are DO transmittals.
Full-word load instruction DI requests will result in zeros in the left-half of the destination GPR, and for full-word store DO transmittals, the desired bit pattern must be in the right half of the source GPR.
The three independent I/O units 221, 222 and 223 of FIG. 21 are assigned numbers as shown below. The numbers listed correspond to B in PCW, LCW instruction descriptions.
______________________________________Unit Number Code Name______________________________________222 1 CMUX223 2 PMUX221 3 041 Special______________________________________
The program control capabilities are as follows:
Code LCW LCWName PCW Initiate Command Status Terminate______________________________________CMUX No Yes NoPMUX Yes Yes No041 Special No No No______________________________________
Thus, the CMUX and 041 Special are self-starting by signals received external to the RDP. The program has no terminate capabilities over the three units and no status monitoring capabilities over the 041 Special.
All the special units operate in the full-word transmission mode only, although some of the data have only 16 bits of significance. All three units provide interrupt signals to the RDP as follows.
______________________________________Code Message Completion Message ErrorName Interrupt Interrupt______________________________________CMUX Interrupt 17 Interrupt 18 (Not wired)PMUX Interrupt 16 Interrupt 19041 Special Interrupt 15 No______________________________________
The CCC Multiplex Terminal 222 operates as the interface between the CCC data bus and the RDP Main Bus. It is slaved to the Central Control Computer (CCC) as regards message initiation but acts as an independent unit on the RDP Main Bus. The CCC is not to be confused with the processor unit 200. The CCC is an independent ship board computer. The terminal will receive or transmit data in blocks. Every message is preceded by a specified select word from the foregoing table, issued from the CCC over one of two redundant party line busses.
______________________________________data/ Controlcommand Field T/R Word Count Parity4 8 9 10 11 12 13 14 15 16______________________________________1 0 0 0 1 0 0 0 1 00 0 0 1 1 1 0 1 1 00 0 1 0 1 0 0 1 1 10 0 1 1 1 0 1 0 0 10 1 0 0 0 1 0 0 0 00 1 0 1 0 0 0 0 1 0______________________________________
The unit address in bit positions 0-3 is 1010 in all cases as there is only one multiplexer, and the first 3-bit position of the control field is always zero. The maximum length of message is 15 words, each word containing 16 bits plus a parity bit. In the RDP memory, the 16 bits will be MSB aligned (bit zero) and will always contain trailing zeros (bits 16 to 23). The parity bit is used only by the terminal and does not appear in the RDP memory.
Once the unit begins to receive or send a data word or a select word, that word is carried to completion (all 17 bits). After a select word is received and recognized, the terminal is committed to the message length prescribed, except under the following conditions:
1. Loss of clock on the bus in use
2. Inability to perform a data transfer with the RDP memory within five microseconds
3. In receive mode, the absence of the first bit of an expected data word.
An invalid select word (invalid or data drop-out) is ignored by the terminal. An invalid received data word, with the exception of a data drop-out in the first bit, is noted as being bad and not stored in the RDP memory. In other words, if any word of a message is invalid, that word will not be updated, but all other words that were valid will be.
With this scheme the CCC has the capability of updating any contiguous group of data in any message by providing the proper starting address (not necessarily the full message count) and sending any number (up to that count) of data words.
The word address for data in memory is composed of a fixed and a variable part, the variable part being the message code contained in the select-word and the word-counter value. The word counter decrements from the original select-word count to obtain memory addresses. Consequently, data words are stored or read in decreasing address fashion, proceeding from the first (largest address) sequentially to the last (word address one).
Messages are limited to 15 words maximum and addresses are allocated in 16-word blocks to permit the 16th word (address zero) to be used as a validity tag. In this address scheme there will be unused addresses in some block since all messages will not necessarily contain 15 words. The fixed parts of the word addresses are set by jumpering at the base plate.
The message code in the instruction tells which message is currently active, or was most recently active. The word count is the current word "pointer". At the termination of a message, the last LCW word is stored in address zero of the message block as the "validity tag." It also remains available as an LCW word until the next select word arrives. If the message was terminated properly, the word count in the tag word and final LCW word will be zero. If the message was improperly terminated (i.e., loss of clock on bus in use, inability to access RDP main bus, or absence of first bit of received data), then the word count in the tag word and final LCW word is the value at message termination. If input data have bad parities or data drop outs (except in first bit), then the invalid bit is set to 1 and remains at 1 for the remainder of the message, including the tag word. In this case the data are not stored, but the message transaction continues. An interrupt indicator (W2, bit 17) is set = 1 whenever a message terminates.
The RSP Special receives data from the RSP's interface data assembler (IDA). The RSP Special receives the data as 30 half-words which it packs into 15 full-words and transmits to main memory locations 767-753 (full-word 752 is a spare). At the completion of the transaction the RSP Special sets its completion interrupt indicator (W2, bit 15) = 1.
The program has no PCW or LCW capabilities with this unit. The BIT instruction is the only control function available to software over the operation of this unit. Details of the message structure can be found in other documents.
The RSP multiplexer performs two major functions in the tactical mode: (1) receives a fixed block length message from the INS and stores it in main memory, and (2) fetches message blocks from main memory and transmits them to the RSP Special unit. Once a transaction is initiated by the program, the PMUX performs its tasks independently of the processor. The program cannot terminate a transaction once it is initiated.
A fixed block of main memory has been assigned for PMUX messages. The block can be thought of as consisting of eight sub-blocks of 16 full-words each, for a total of 128 full-words. Each sub-block is associated with a possible PMUX transaction.
Having described the manner in which the range and velocity tracking loops operate in cooperation with the angle tracking loop, the technique for resolving the ambiguity inherent in the velocity estimate, V.sub.TPV, will now be described. As noted hereinbefore, the ambiguity is resolved by using the unambiguous velocity estimate V.sub.TPR from the range channel when .vertline.V.sub.TPV - V.sub.TPR .vertline. < .lambda. PRF/4, which is when the difference between the ambiguous doppler frequency (f.sub.DAP = 2V.sub.TPV /.lambda.) and the unambiguous doppler frequency (f.sub.DP = 2V.sub.TPR /.lambda.) is less than PRF/2. A simple test could be quickly made to determine when that point in time has been reached, but it has been determined that a period of 1.5 seconds of tracking in initial track will be ample at all times to successfully resolve ambiguity. Consequently, a subroutine UV is called by the executive routine after a real time lapse of 1.5 seconds following acquisition of the target.
Before describing the UV routine with reference to FIG. 27, the problem at hand will be diagrammatically described with reference to FIG. 26 which shows a frequency spectra from a reference 0 to an indefinite number of times the radar PRF. An actual target return is shown at the actual doppler frequency f.sub.D, but additional target images will appear above and below the frequency f.sub.D at regular intervals of PRF above and below the frequency f.sub.D. The problem of resolving ambiguity is to track the target velocity in the range filter until V.sub.TPR, converted to frequency, is within PRF/2 and to then compute a corrected velocity V.sub.TCORR by determining the whole number N of PRF intervals between the target image at frequency f.sub.DAP and computing a corrected doppler frequency f.sub.DC equal to that number times the PRF less the frequency f.sub.DAP.
The reference 0 is not shown at frequency f.sub.o but at some frequency f.sub.MLC predetermined to shift the reference sufficiently for main lobe blanking on each side of the spectral lines without blanking the target return in the area of each spectrum where it is expected to appear. Consequently, the frequency f.sub.MLC must be taken into account in computing V.sub.TCORR which is in feet per second, and is correct only when referenced back to absolute zero (f.sub.o) in doppler frequency shift. To accomplish that, computation of V.sub.TCORR in an exemplary embodiment is in accordance with the following equation:
V.sub.TCORR = .lambda./2{PRF[(f.sub.MLC +f.sub.DAP -f.sub.DP)PRF.sup.-.sup.1 +1/2]*}-(f.sub.DAP +f.sub.MLC) (136)
where PRF is the medium PRF of the radar being used at the time, .lambda. is the wavelength of the radar frequency being used at the time, and the asterisk indicates the quantity in brackets is to be truncated by dropping the fractional part.
A flow chart of the subroutine UV shown in FIG. 27 will carry out the computation of Equation (136). A listing of instructions for implementation of the UV routine is set forth in Appendix D. It uses the more precise but ambiguous measurement of target doppler shift f.sub.DAP to compute an equally precise and unambiguous target doppler shift f.sub.DC in the manner generally described with reference to FIG. 26. The first step in block UV006 is to compute -f.sub.DP by multiplying V.sub.TPR in memory location FTV1002 by 2/.lambda. with binary point scaling at B18, i.e., at 18 bit positions to the right of the sign in bit position 0, where bit positions are numbered 1-23 with the least significant bit in position 23. The result is stored in register R4, one of eight working registers. That operation takes 11.75 .mu.s. The next operation in block UV009 is to compute f.sub.DAP by multiplying V.sub.TPV by 2/.lambda. with the same scaling B18. That takes 5.25 .mu.s.
Having formed f.sub.DP and f.sub.DAP, the next step in block UV010 is to form -f.sub.DC by forming the sum f.sub.MLC +f.sub.DAP -f.sub.DP, multiplying that sum by PRF.sup.-.sup.1, rounding of the product by adding 1/2, truncating the rounded product by dropping the fractional part to obtain a whole integer N, multiplying the integer N by PRF and then subtracting f.sub.DAP. That provides a corrected doppler shift frequency referenced to 0 in the diagram of FIG. 26. To reference it to a zero doppler shift frequency, f.sub.O, f.sub.MLC is subtracted. That has the effect of shifting the entire spectra back to f.sub.O away from which it was shifted for doppler tracking in order to blank the main lobe clutter, as noted hereinbefore.
The desired velocity V.sub.TCORR is then computed in block UV028 by simply multiplying -f.sub.DC by .lambda./2, scaling to B13 and storing the results in register R4. During the next iteration only, the velocity filter will take the value of V.sub.TCORR and use it as V.sub.TPV, thereby resolving velocity ambiguity. That is used by other systems, such as display and fire control systems so that it is important that ambiguity be resolved and that velocity thereafter be tracked unambiguously by the velocity channel.
The range and velocity command computer 16 also uses V.sub.TPV to calculate the velocity gate V.sub.GC in response to which the velocity gate V.sub.G is produced, thereby closing the velocity tracking loop. But now in final track, the value of V.sub.TPV may be greater by several multiples of PRF and referenced to f.sub.0, instead of f.sub.MLC. Therefore, during the final track, the computer 16 literally undoes what the routine UV has done, to reconstruct the ambiguous V.sub.TPV for continued smooth tracking.
The ambiguous velocity V.sub.TPV could be retained in the filter, and that would leave the computer 16 operating the same in final track as in initial track. In that case, each time V.sub.TPV would be called up for transmittal to the display and fire control 19, it would be resolved using the routine of FIG. 27.
From the foregoing description of the present invention and an exemplary digital computer (RDP), it is evident how the flow diagrams can be implemented by programming the RDP using instructions from the repertoire of Appendix A. An exemplary list of instructions for such an implementation is set forth in Appendix B. The values of constraints employed are listed in Appendix C.
APPENDIX A
Instruction Set
The Instruction Set consists of 92 instructions. Each instruction is described individually. The instruction descriptions make use of a common notation to describe the various instruction format fields and the hardware registers. This notation is summarized in the following table.
A -- normally designates a 12-bit immediate address (certain branch instructions do provide a 15-bit address)
B -- i/o control Unit
I -- immediate Data (3 bits; signed 2-bit integer)
K -- count (3 bits or 6 bits)
O -- mnemonic op code
R.sup.a -- General purpose register used as a destination register (0 .ltoreq. a .ltoreq. 7)
R.sup.c -- General purpose register used as a source register (0 .ltoreq. x .ltoreq. 3)
R.sup.x -- General purpose register used as an index register (1 .ltoreq. x .ltoreq. 3)
R.sub.age -- designates the AGE control register
R.sub.bit -- designates the set of distributed BIT flip-flops
W.sup.a -- Working register used as a destination register (0 .ltoreq. a .ltoreq. 3)
Y -- immediate data (12 bits; signed 11-bit integer)
* -- Indirect address flag
The instruction descriptions themselves are grouped by function for convenient reference. The seven functional groups are listed below.
______________________________________Functional Group Number Instructions______________________________________Data Transfer 17Arithmetic 28Logic 19Shift 9Branch 9Processor Control 8Input/Output (I/O) Control 2 92______________________________________
RDP instruction is described in terms of 11 items in a systematic format; this format and the notation used to define it are as follows:
MNEMONIC.sup.(1) INSTRUCTION NAME.sup.(2) SYMBOLIC INSTRUCTIONSYNTAX.sup.(3)INSTRUCTION FORMAT .sup.(4)0 1 2 3 . . . nUSAGE.sup.(5)OPERATION.sup.(6)EFFECTIVE IMMEDIATE OPERAND.sup.(7)INDICATORS.sup.(8)EFFECTIVE ADDRESS.sup.(9)TIMING.sup.(10)EXAMPLE.sup.(11) 1. MNEMONIC is the symbolic op code name. 2. INSTRUCTION NAME is the instruction's descriptive title.
Where:
1. MNEMONIC is the symbolic op code name.
2. INSTRUCTION NAME is the instruction's descriptive title.
3. SYMBOLIC INSTRUCTION SYNTAX is the form of the instruction's symbolic representation. The notation defined for expressing three symbolic representations is given in the foregoing table. Required syntax items are underlined, whereas optional items are not. The meaning of the symbolic in-instruction syntax is illustrated below.
______________________________________SYNTAX: O,R.sup.a *A,R.sup.xSYMBOLIC INSTRUCTION: A,1 TEMP,2______________________________________
In the above symbolic instruction example: A is a mnemonic op code meaning add memory to register; 1 specifies R.sup.1 as the register to be incremented; TEMP is a symbolic address; 2 specifies R.sup.2 as the index register whose contents are needed to TEMP to give the effective address.
4. INSTRUCTION FORMAT illustrates the particular format used by the instruction. Additional notation used to designate in-instruction format fields is given in the foregoing table.
5. USAGE is a functional description of the instruction actions, oriented to convey an intuitive feeling for its utilization.
6. OPERATION is a specific description of the detailed sequence of actions that the instruction initiates.
7. EFFECTIVE IMMEDIATE OPERAND describes the formation of immediate operands from immediate data instruction fields. (This item is defined for immediate instruction only.)
8. INDICATORS describes the setting of any indicators as a result of the execution of the instruction. Usually the indicators thus affected will be either the condition code register or one of the interrupt indicator register bits.
9. EFFECTIVE ADDRESS describes the options (if any) that may be used in forming the instruction's final operand address.
10. TIMING provides a range of nominal execution times (in microseconds) to be expected. The range limits are given, corresponding to the cases of no instruction look-ahead benefit (the longer time) and of complete look-ahead benefit (the shorter time). In general, the actual execution time may be between these limits at increments of 0.25 .mu.s. For those instructions capable of indirect addressing, the nominal timing penalty per addressing level is also given. In determining the timing values, the following assumptions were made:
a. No bus cycle conflicts occur; add 0.25 .mu.s per conflict
b. No memory cycle conflicts occur; add 0.75 to 1.5 .mu.s per conflict
c. Operands and instructions are located in the main memory; for local processor locations, subtract 0.5 .mu.s
d. The memory cycle time is 1.5 .mu.s
11. EXAMPLE: For some instructions, one or more examples are given to illustrate the instruction's operation. Where included, they are intended to help explain the action of the instruction and not necessarily to demonstrate their full capability.
DATA TRANSFER INSTRUCTIONS
Data transfer instructions operate on double-word (48-bit), full-word (24-bit), or half-word (12-bit) data fields. Load instructions load information into a data field of one or more of the eight general purpose registers. These instructions do not alter the information source location contents; however, all load instructions set the condition code register, thereby providing the following information about the information loaded into the affected general purpose register.
______________________________________Condition Code Setting, bit1 2 Data Field Value______________________________________0 1 Negative1 0 Zero1 1 Positive______________________________________
Store instructions alter only that portion of the storage location contents that correspond in length and position to the information field specified by the store instruction. These instructions do not set the condition code register and do not affect the contents of the data item source location -- unless this location happens also to be referenced by the instruction effective address.
The exchange instruction performs both a load and store operation, setting the condition code register by the data word loaded from the storage location specified by the effective address.
______________________________________L -- Load O,R.sup.a *A,R.sup.X*R.sup.x 00 R.sup.a Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Load register loads one of the eight general purpose registers with the contents of the effective address. The effective address is not restricted to the main memory, and may be used to load from an I/O address, another general purpose register, or any other valid system address.
OPERATION
The contents of the computed effective address are loaded into general purpose register R.sup.a. The contents of the source of the data are not disturbed.
INDICATORS
The condition code register is set by the data loaded into general purpose register R.sup.a.
EFFECTIVE ADDRESS
Indirect addressing and indexing may be specified. A full 24-bit word is accessed. The least significant bit of effective address is not decoded.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 2.0 3.5LG -- Load from Register O,R.sup.a R.sup.c R.sup.c 01 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Load from Register is used to transfer the contents of one general purpose register to another.
OPERATION
The contents of a general purpose register R.sup.c are read nondestructively and stored in R.sup.a.
INDICATORS
The condition code register is set to reflect the "condition" of the transferred data. Note that R.sup.a and R.sup.c may be the same register.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ 0.50 1.50LH -- Load Half O,R.sup.a *A,R.sup.x*R.sup.x 02 R.sup.a Address (4096 half-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Load Half is used the same as Load, with the exception that a 12-bit half-word operand is loaded into the left half of the designated general purpose register. As in Load, the operand may come from core memory, another general purpose register, an I/O unit, or any other addressable data storage locations.
OPERATION
The half-word specified by the computed effective address is transferred to the left half of the register, R.sub.l.sup.a. The right half of the register, R.sub.r.sup.a, is cleared to all zero's. The source of the data is unaltered.
INDICATORS
The data loaded into R.sub.l.sup.a set the condition code register.
EFFECTIVE ADDRESS
Indexing or multiple level indirect addressing with indexing at any level may be utilized to access the half-word operand. The least significant bit of the computed effective address can be thought of as "pointing" to the left (0) or right (1) half of a full word.
TIMING, .mu.s
Look-Ahead StatusIndirect Address.mu.s/level Complete None______________________________________1.5 2.0 3.5LHG -- Load Half from Register O,R.sup.a R.sup.cR.sup.c 03 R.sup.a0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Load Half from Register is a short instruction used to transfer only the left half (most significant 12 bits) of one general purpose register to another. The right half of the destination register is cleared to all zero's.
OPERATION
The contents of R.sub.l.sup.c are loaded into R.sub.l.sup.a. R.sub.t.sup.a is set to zero. R.sup.c is unchanged.
INDICATORS
The transferred data set the condition code register. Note that R.sup.a and R.sup.c may be the same GPR, thus clearing its right half while setting the condition code.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ 0.5 1.5LR -- Load Right O,R.sup.a *A,R.sup.x*R.sup.x 05 R.sup.a Address (4096 half-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Load Right is used to load a 12-bit left or right half-word operand into the right half of the designated general purpose register. The half-word operand may come from main memory, a general purpose register, or any other addressable location.
OPERATOR
The half-word specified by the computed effective address is transferred to the right half of the register, R.sub.r.sup.a. The left half of the register, R.sub.l.sup.a, is cleared to all zero's.
INDICATORS
The data loaded into R.sub.r.sup.a sets the condition code register.
EFFECTIVE ADDRESS
Indexing or indirect addressing may be utilized to access the half-word operand. The least significant bit of the computed effective address (which is not decoded for instructions referencing full-word operands) indicates either the left (0) or right (1) half of a full-word memory location.
TIMING, .mu.s
Look-Ahead StatusIndirect Address.mu.s/level Complete None______________________________________1.5 2.0 3.5LD -- Load Double O,R.sup.a *A,R.sup.x*R.sup.x 06 R.sup.a Address (2048 double-word pair)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Load Double places two successive full-words into two successive general purpose registers and is particularly useful for double precision arithmetic. It is not redundant with the Load Multiple instruction, since the complete operand address modification capabilities are available.
OPERATION
The full-word contents of the effective address and the full-word contents of the succeeding locations are loaded into R.sup.a and R.sup.(a.sup.+1) mod 8, respectively.
INDICATORS
The arithmetic condition of the word transferred into R.sup.a sets the condition code register.
EFFECTIVE ADDRESS
Indexing and indirect addressing are allowed and two 24-bit words are fetched. The least significant bit of the computed effective address is not decoded.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 4.5 6.0EXAMPLE 1: LD,3 ABCBefore Execution After Execution______________________________________(ABC) '00000000' '00000000'(ABC+2) '01234567' '01234567'(R.sup.3) XXXXXXXX '00000000'(R.sup.4) XXXXXXXX '01234567'(CC) XX 10______________________________________EXAMPLE 2: LD,7 DEFBefore Execution After Execution______________________________________(DEF) '01234567' '01234567'(DEF+2) '00000000' '00000000'(R.sup.7) XXXXXXXX '01234567'(R.sup.0) XXXXXXXX '00000000'(CC) XX 11LM -- Load Multiple O,R.sup.a,K *A______________________________________K 04 R.sup.a Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Load Multiple causes a sequential set of full data words to be loaded into a sequential set of general purpose registers. The set of data words need not come only from main memory.
OPERATION
General purpose register R.sup.a is loaded with the contents of the location specified by the effective address. R.sup.(A.sup.+1) mod 8 is loaded from the effective address +2 (half-words). This process continues sequentially, until K general purpose registers have been loaded. (Should K = 0, all eight general purpose registers will be loaded as described above.)
INDICATORS
The condition code register is set by the word loaded into R.sup.(a.sup.+1) mod 8.
EFFECTIVE ADDRESS
Indirect addressing is unconditional and is always used to compute the effective address. Indexing may be specified at any level, except the first, of multilevel indirect address operations.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 (2.0)K (2.0)K+1.5LI -- Load Immediate O,R.sup.a Y0 24 R.sup.a Immediate Operand0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
The Load Immediate instruction can be used to rapidly load certain constants into a general purpose register without the need for a separate operand location, since the operand is stored in the instruction itself. For example, a full register can be loaded with an index value in the range of integers -2048 .ltoreq. integer value .ltoreq. 2047, or a fractional value in the range -2.sup.-.sup.12 .ltoreq. fractional value .ltoreq. 2.sup.-.sup.12 -2.sup.-.sup.23. If the intent of the programmer is to load a constant into the right-hand half-word, the integer range remains the same and the fractional range is -1 .ltoreq. fractional value .ltoreq. 1 -2.sup.-.sup.12. Note that in the latter case, the left-hand word is set to either all zero's or all ones.
OPERATION
The effective immediate operand is loaded into register R.sup.a.
INDICATORS
The data loaded into R.sup.a set the condition code register.
EFFECTIVE IMMEDIATE OPERAND
Bits 12 through 23 of the effective immediate operand are taken directly from the IMMEDIATE OPERAND field of the LI instruction. Bits 0 through 11 of the effective immediate operand are set equal to bit 12 of the IMMEDIATE OPERAND (i.e., the sign bit of the IMMEDIATE OPERAND half-word is extended).
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ 0.5 1.5LHI -- Load Half Immediate O,R.sup.a Y2 24 R.sup.a Immediate Operand0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Load Half Immediate is used to load a constant into the left-hand half-word of a general purpose register. The right-hand half-word is set to all zero's.
OPERATION
The 12-bit IMMEDIATE OPERAND field of the instruction is transferred to R.sub.l.sup.a. R.sub.r.sup.a is set to zero.
INDICATORS
The condition code register is set according to the constant loaded into R.sub.l.sup.a.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ 0.5 1.5ST -- Store O,R.sup.a *A,R.sup.x* R.sup.x 10 R.sup.a Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
The Store instruction stores the contents of one of the eight general purpose registers into the effective address. While typically used to store a general purpose register into main memory, this instruction may be used to transfer a general purpose register to any addressable location in the system. Similarly to Load, Store may be used to index or indirectly address the destination of a register-to-register transfer. However, as opposed to Load, the condition code register is not set.
OPERATION
The contents of general purpose register R.sup.a are stored in the location specified by the computed effective address. The contents of R.sup.a are not disturbed by the transfer.
INDICATORS
None
EFFECTIVE ADDRESS
Indirect addressing and indexing may be specified to compute the effective address. A full 24-bit word is transferred. The least significant bit (half-word pointer) of the computed effective address is not decoded.
TIMING, .mu.s
Indirect Address, Look-Ahead Status.mu.s/level Complete None______________________________________1.5 1.5 3.25STH -- Store Half O,R.sup.a *A,R.sup.x* R.sup.x 12 R.sup.a Address (4096 half-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Store Half is used as Store, except that a 12-bit half-word operand from the left half of the designated general purpose register is stored into the effective address location. As in Store, the destination of the operand is not restricted to main memory.
OPERATION
The data in the left half of the register, R.sub.l.sup.a, are stored in the half-word specified by the computed effective address. The other half of the corresponding full-word is not changed. The contents of R.sub.l.sup.a and R.sub.r.sup.a remain the same. (Exception: When the effective half-word is in a working register, the contents of R.sub.r.sup.a will also be stored in the WR's remaining half-word, i.e., the half-word which was not addressed by the instruction.)
INDICATORS
None.
EFFECTIVE ADDRESS
Indexing or multiple level indirect addressing with indexing at any level may be utilized to reference the half-word storage location. The least significant bit of the effective address specifies the left (0) or right (1) half of the full-word storage location.
TIMING, .mu.s
Indirect Address, Look-Ahead Status.mu.s/level Complete None______________________________________1.5 1.5 3.25STR -- Store Right O,R.sup.a *A,R.sup.x* R.sup.x 15 R.sup.a Address (4096 half-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Store Right is used to store the right half of a designated general purpose register into a 12-bit half-word storage location. The storage location may be in main memory, another general purpose register, or any other addressable location.
OPERATION
The contents of R.sub.r.sup.a are stored into the half-word storage location specified by the computed effective address. The contents of R.sup.a and of the half-word adjacent to the selected storage location remain unchanged. (Exception: When the effective half-word is in a working register, the contents of R.sub.l.sup.a will also be stored in the WR's remaining half-word, i.e., the half-word which was not addressed by the instruction.)
INDICATORS
None.
EFFECTIVE ADDRESS
Indexing or indirect addressing may be utilized in forming the effective address. The least significant bit of the computed effective address indicates either the left (0) or right (1) half of a full-word storage location.
TIMING, .mu.s
Indirect Address, Look-Ahead Status.mu.s/level Complete None______________________________________1.5 1.5 3.25STD -- Store Double O,R.sup.a *A,R.sup.x* R.sup.x 16 R.sup.a Address (2048 double-word pair)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Store Double takes the contents of two successive general purpose registers and places them in two successive full-word storage locations. It is particularly useful for double precision arithmetic.
OPERATION
The full word contents of R.sup.a and R.sup.(a.sup.+1) mod 8 are stored in effective address and the effective address +2, respectively.
INDICATORS
None
EFFECTIVE ADDRESS
Indexing and indirect addressing are allowed and two 24-bit words are stored. The least significant bit of the instruction computed effective address is ignored.
TIMING, .mu.s
Indirect Address, Look-Ahead Status.mu.s/level Complete None______________________________________1.5 3.5 5.25STM -- Store Multiple O,R.sup.a,K *AK 14 R.sup.a Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Store Multiple causes a sequence of full data words to be transferred from a sequential subset of general purpose registers to a sequence of storage locations. The sequence of storage locations need not be in main memory.
OPERATION
The location specified by the computer effective address is loaded with the contents of R.sup.a. The succeeding full-word storage location is loaded with the contents of R.sup.(a.sup.+1) mod 8. This process continues, sequentially, until K general purpose registers have been stored into K successive storage locations. (Should K = 0, all eight general purpose registers will be stored.)
INDICATORS
None.
EFFECTIVE ADDRESS
Indirect addressing in unconditional and is always used to compute the STM effective address. Indexing may be specified at any level of multilevel indirect address operations, except the first.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 (1.5) K (1.5) K+1.0 K=8; Use 14.5.mu.sSTI -- Store Immediate Q,I *A,R.sup.x*R.sup.x 11 I Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
The Store Immediate instruction can be used to store one of eight constants (including zero) into a full-word storage location without the need for a separate data source, since the data are stored in the instruction itself. For example, a full-word storage location can be loaded with an index value in the range of integers -4 .ltoreq. integer value .ltoreq. 3. STI serves as a generalized "store zero" instruction for full-word data cells.
OPERATION
The effective immediate operand is stored in the effective address full-word.
EFFECTIVE IMMEDIATE OPERAND
Bits 22 and 23 of the effective immediate operand are copies from bits 10 and 11, respectively, of the IMMEDIATE OPERAND field of the STI instruction. Bits 0 through 21 are duplicates of bit 9 of the IMMEDIATE OPERAND (i.e., the sign bit of the IMMEDIATE OPERAND field is extended).
INDICATORS
None.
EFFECTIVE ADDRESS
Indexing and indirect addressing may be specified. A full-word storage location is specified. The least significant bit of the instruction computed effective address is ignored.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ 1.5 3.25STHI -- Store Halfword Immediate O,I *A,R.sup.x*R.sup.x 13 I Address (4096 half-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Store Halfword Immediate is used to load one of eight constants (including zero) into a right or left hand half of a full-word storage location without disturbing the other half. A half-word can be loaded with an index value in the range of integers -4 .ltoreq. integer value .ltoreq. 3. STHI serves as a generalized "store zero" instruction for halfword data cells.
OPERATION
The effective immediate operand is stored in the effective address half-word. The other half of the corresponding full word is not affected. (Exception: When the effective half-word is in a working register, the contents of the other half of the WR are affected in an unpredictable manner.)
EFFECTIVE IMMEDIATE OPERAND
The least significant 2 bits are copied directly from bits 10 and 11 of the immediate operand. The most significant 10 bits (including the sign bit) are duplicates of bit 9 of the immediate operand field (i.e., the sign bit is extended).
INDICATORS
None.
EFFECTIVE ADDRESS
Indexing and indirect addressing may be utilized to compute the half-word storage effective address.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ 1.5 3.25X -- Exchange Register and Memory O,R.sup.a *A,R.sup.x*R.sup.x 07 R.sup.a Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
The Exchange Register and Memory instruction can exchange the contents of a specified general purpose register with those of a full-word storage location in main memory.
OPERATION
The contents of the computed effective address location are read into a full-word buffer register; the contents of general purpose register R.sup.a and then stored in the location specified by the effective address, followed by loading R.sup.a from the buffer register.
INDICATORS
The condition code register is set by the data load into R.sup.a.
EFFECTIVE ADDRESS
Indexing and indirect addressing are allowed. The least significant bit of the instruction address field and any indirect address operand address fields are ignored.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 3.5 5.50______________________________________
This arithmetic instruction set performs fixed-point arithmetic in the fractional two's complement number system. The first operand with the exception of the Add Immediate Memory is located in one of the eight general purpose registers, while the second operand may be located in main memory, local store, the instruction immediate operand field, another (or the same) general purpose register, or generally in any valid system addressable storage location. All arithmetic instructions set the condition code register with the results of the operation, thus the following information is provided.
______________________________________Condition CodeSetting, bits1 2 Result Value______________________________________0 1 Negative1 0 Zero1 1 Positive______________________________________
In addition, if an arithmetic overflow occurs or a division by zero is attempted, bit 4 of the interrupt indicator register (working register 2) is set to signify that an arithmetic anomaly has occurred. This interrupt indicator is maskable under program control.
______________________________________A -- Add O,R.sup.a *A,R.sup.x*R.sup.x 40 R.sup.a Address (2096 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Add is used to form the two's complement sum (standard binary arithmetic) of a storage location and a general purpose register and store the sum in that same register.
OPERATION
The contents of R.sup.a are replaced by the sum of the full-word contents of the global effective address and the previous contents of R.sup.a. Thus, while the addend in memory is preserved, the general purpose register augend is replaced by the sum.
INDICATORS
An overflow condition sets the arithmetic anomalies indicator in the interrupt indicator register to a logical 1. The condition code register is set by the sum.
EFFECTIVE ADDRESS
Indexing and multilevel indirect addressing are allowed. A full 24-bit operand is accessed and the least significant bit (bit 23) of the global effective address is not decoded.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 2.0 3.5AG -- Add Register O,R.sup.a R.sup.c R.sup.c 41 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Add Register is used to rapidly add the contents of two general purpose registers.
OPERATION
The augend in R.sup.a is replaced by the sum of itself and the addend in R.sup.c. R.sup.c is left unchanged.
INDICATORS
The arithmetic anomalies indicator is set if an overflow occurs. The sum, which appears in R.sup.a, sets the condition code registers.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ 0.5 1.5AH -- Add Half O,R.sup.a *A,R.sup.x*R.sup.x 42 R.sup.a Address (4096 half-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
The Add Half instruction is used to perform half-word arithmetic on the left half of a general purpose register. The contents of a half-word storage location are added to the left half of the designated general purpose register.
OPERATION
The half-word contents of the global effective address are added to the contents of R.sub.l.sup.a, and the sum is subsequently stored in R.sub.l.sup.a. The storage location and R.sub.r.sup.a pointed to by the global effective address are left unchanged.
INDICATORS
The halfword sum sets the condition code register, and an overflow result sets the arithmetic anomalies indicator in the interrupt indicator register to a logical 1.
EFFECTIVE ADDRESS
The global effective address refers to a 12-bit half-word operand and may be formed through indexing and multilevel indirect addressing.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 2.0 3.5AHG -- Add Half Register O,R.sup.a R.sup.c R.sup.c 43 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Add Half Register is a short instruction used to rapidly add the left halves of two general purpose registers.
OPERATION
The half-word contents of R.sub.l.sup.a and R.sub.l.sup.c are added, and the sum is stored in R.sub.l.sup.a. The full-word contents of R.sup.c are unchanged, and the contents of R.sub.r.sup.a also remain unchanged.
INDICATORS
The arithmetic anomalies indicator in the interrupt register is set upon an overflow in the half-word sum. The condition code register is also set by the algebraic condition of the sum.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ 0.5 1.5AD -- Add Double O,R.sup.a *A,R.sup.x*R.sup.x 46 R.sup.a Address (2048 double-word pair)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Add Double is useful for double precision arithmetic and is used to add a double-word length addend in storage to a double precision augend in two general purpose registers.
OPERATION
The contents of the full-word storage location specified by the computed effective address together with those of the next higher address, full-word are treated as a double-length (46-bit + sign) operand. This operand is added to the contents of general purpose registers R.sup.a and R.sup.(a.sup.+1) mod 8. Double-length operands possess a single sign bit that is stored in bit position 0 of the most significant operand word. The least significant 23 bits of a double-length operand are stored left-justified in the least significant word; bit 23 of this word is always zero.
INDICATORS
IF the computer sum overflows, the arithmetic anomalies indicator in the interrupt indicator register will be set. The condition code register is set by the most significant word; i.e., the final contents of R.sup.a.
EFFECTIVE ADDRESS
The global effective address, which may be formed by indexing and multilevel indirect addressing, points to the first or most significant full-word of a double word operand.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 4.5 6.0AP -- Add Parallel O,R.sup.a *A,R.sup.x*R.sup.x 44 R.sup.a Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
The Add Parallel instruction is used to simultaneously add two adjacent half-words in storage to two half-words in a general purpose register. The two half-words in storage must be in the left and right halves of a full-word and cannot cross over a full-word boundary.
OPERATION
The right half-word of the contents of the global address is added to R.sub.r.sup.a and the sum stored in R.sub.r.sup.a. The left half-word is added to R.sub.l.sup.a and the sum stored in R.sub.l.sup.a.
INDICATORS
An overflow in the left-half sum will cause the arithmetic anomaly indicator in the interrupt indicator register to be set. The condition code register is set by the left-half sum.
EFFECTIVE ADDRESS
The global effective address refers to a full-word and the least significant bit of the computed effective address is not decoded. Indexing and indirect addressing are allowed.
TIMING, .mu.s
Look-Ahead Status Indirect Address, .mu.s/level Complete None______________________________________ 1.5 2.0 3.5EXAMPLE 1: AP,2 ABC Before Execution After Execution(ABC) `3333 5555` `3333 5555`(R.sup.2) `2222 4444` `5555 2221`(CC) XX 01APG -- Add Parallel (G) Register O,R.sup.a R.sup.c R.sup.c 45 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Add Parallel Register is a short instruction used to simultaneously add two half-words in one general purpose register to two half-words in another general purpose register.
OPERATION
The contents of R.sub.l.sup.a are added to the contents of R.sub.l.sup.c and the sum stored in R.sub.l.sup.a. The contents of R.sub.r.sup.a are added to the contents of R.sub.r.sup.c and the sum stored in R.sub.r.sup.a. R.sup.c is left unchanged.
INDICATORS
The condition code register is set according to the left half sum. The arithmetic anomaly in the interrupt indicator register is set if the left-half sum overflows.
TIMING, .mu.s
Look-Ahead StatusComplete None______________________________________0.5 1.5AI -- Add Immediate O,R.sup.a Y1 24 R.sup.a Immediate Operand0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Add Immediate can be used to add certain constants to a full-word general purpose register without the operand storage space that would be required if Add were used. For integer constants, the entire range -2048 .ltoreq. integer value .ltoreq. + 2047 is covered. For fractional constants, the range -2.sup.-.sup.12 .ltoreq. fractional value .ltoreq. 2.sup.-.sup.12 -2.sup..sup.-23 is covered. Therefore, a complementary Subtract Immediate instruction is not needed.
OPERATION
The effective immediate operand is added to R.sup.a and the sum stored in R.sup.a.
INDICATORS
The sum sets the condition code register. An overflow condition is not sensed.
EFFECTIVE IMMEDIATE OPERAND
Bits 12 through 23 of the effective immediate operand are copied identically from bits 12 through 23 of the immediate operand field. Bits 0 through 11 of the effective immediate operand are all identical to bit 12 of the immediate operand field (sign bit extension).
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ 0.5 1.5AHI -- Add Half Immediate O,R.sup.a Y3 24 R.sup.a Immediate Operand0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Add Half Immediate can be used to rapidly add any half-word constant to the left half of a general purpose register without the half-word operand storage space and extra time required for Add Half. Note that a Substract Half Immediate instruction would be redundant since both positive and negative constants are accommodated by the immediate operand field.
OPERATION
The immediate operand is treated as a half-word two's complement addend and added to R.sub.l.sup.a. The sum is stored in R.sub.l.sup.a. R.sub.r.sup.a is unchanged.
INDICATORS
The condition code register is set according to the algebraic condition of the sum. An overflow condition is not sensed.
TIMING, .mu.s
Look-Ahead StatusComplete None______________________________________0.5 1.5AIM -- Add Immediate to Memory O,I *A,R.sup.x*R.sup.x 47 I Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
The Add Immediate to Memory instruction can be used to add one of eight constants to any addressable storage location (with the exception of the eight GPRs) without the need for a separate data source, as the operand is stored in the instruction itself. Typical applications are the incrementing or decrementing of an integer count value with -4 .ltoreq. integer value .ltoreq. +3.
OPERATION
The effective immediate operand is added to the contents of the global effective address, and the sum is subsequently stored in the global effective address.
EFFECTIVE IMMEDIATE OPERAND
Bits 22 and 23 of the effective immediate operand are copied from bits 10 and 11, respectively, of the immediate operand field. Bits 0 through 21 are duplicated from bit 9 (i.e., the sign bit of the immediate operand field is extended).
INDICATORS
The condition code register is set by the computed sum. An overflow condition sets the arithmetic anomalies indicator in the interrupt indicator register.
EFFECTIVE ADDRESS
Indexing and indirect addressing may be specified. Since a full-word is accessed, the least significant bit of the computed effective address is not decoded. A GPR cannot be referenced by the global effective address.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 4.0 6.0ATM -- Add to Memory O,R.sup.a *A,R.sup.x*R.sup.x 57 R.sup.a Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Add to Memory is used to add a general purpose register to a storage location (which cannot be a GPR).
OPERATION
The contents of R.sup.a are added to the full-word contents of the global effective address and the sum subsequently stored in the global effective address. R.sup.a is left unchanged.
INDICATORS
The computed sum sets the arithmetic anomalies indicator in the interrupt indicator register if an overflow occurs. The condition code is set by the sum.
EFFECTIVE ADDRESS
Indexing and indirect addressing are allowed. The least significant bit (half-word pointer) of the computed effective address is not decoded. A GPR cannot be referenced by the global effective address.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 3.0 5.5S -- Subtract O,R.sup.a *A,R.sup.x*R.sup.x 50 R.sup.a Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Subtract is used to form the two's complement difference (standard binary arithmetic) of a storage location and a general purpose register. The difference is stored in the general purpose register.
OPERATION
The contents of R.sup.a are replaced by the difference of the full-word subtrahend in the global effective address and the full-word minuend in R.sup.a. The subtrahend is not changed.
INDICATORS
An overflow condition sets the arithmetic anomalies in the interrupt indicator register to a logical 1. The condition code register is set by the difference.
EFFECTIVE ADDRESS
Indexing and multilevel indirect addressing are allowed. A full 24-bit operand is accessed and the least significant bit of the global effective address is not decoded.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 2.0 3.5SG -- Subtract (G) Register O,R.sup.a R.sup.c R.sup.c 51 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Subtract Register is used to rapidly subtract one general purpose register from another; SG can thus be used to clear a GPR to all zero's.
OPERATION
The minuend in R.sup.a is replaced by the difference of itself and the subtrahend in R.sup.c. R.sup.c is left unchanged.
INDICATORS
The arithmetic anomalies indicator is set if an overflow occurs. The difference, which appears in R.sup.a, sets the condition code register.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ 0.5 1.5SH -- Subtract Half O,R.sup.a *A,R.sup.x*R.sup.x 52 R.sup.a Address (4096 half-Words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
The Subtract Half instruction is used to perform half-word arithmetic on the left half of a general purpose register. The contents of a half-word storage location are subtracted from the left half of a general purpose register.
OPERATION
The half-word subtrahend in the global effective address is subtracted from the half-word minuend in R.sub.l.sup.a, and the difference is stored in R.sub.l.sup.a. The storage location point to by the global effective address is left unchanged. R.sub.r.sup.a is left unchanged.
INDICATORS
The difference sets the condition code register, and an overflow result sets the arithmetic anomalies indicator in the interrupt indicator register to a logical 1.
EFFECTIVE ADDRESS
The global effective address points to a 12-bit half-word operand and may be formed through indexing and multilevel indirect addressing
TIMING, .mu.s
Look-Ahead StatusIndirect Addressing,.mu.s/level Complete None______________________________________1.5 2.0 3.5SHG -- Subtract half (G) Register O,R.sup.a R.sup.c R.sup.c 53 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Subtract Half Register is a short instruction used to rapidly subtract the left half of one general purpose register from the left half of another. An SHG can be used to clear the left half of a GPR to zero's.
OPERATION
The half-word subtrahend in R.sub.l.sup.c is subtracted from the half-word minuend in R.sub.l.sup.a, and the difference is stored in R.sub.l.sup.a. The full-word contents of R.sup.c are unchanged, and the contents of R.sub.r.sup.a also remain unchanged.
INDICATORS
The arithmetic anomalies indicator in the interrupt indicator register is set upon an overflow in the half-word difference. The condition code register is also set by the algebraic condition of the difference.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ 0.5 1.5SD -- Subtract Double O,R.sup.a *A,R.sup.x*R.sup.x 56 R.sup.a Address (2048 full-word pair)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Subtract Double is particularly useful for double precision arithmetic and is used to subtract a double-word length operand in storage from a double-word length operand in two general purpose registers. SD can be used to clear two registers to all zero's.
OPERATION
The contents of full-word storage location specified by the computed effective address together with those of the next higher address full-word are treated as a double length (46-bit + sign) operand. This operand is subtracted from the contents of the general purpose registers R.sup.a and R.sup.(a.sup.+1) mod 8 (which also contain a double length operand), and the double length difference is stored in R.sup.a and R.sup.(a.sup.+1) mod 8. Double length operands possess a single sign bit that is stored in bit position 0 of the most significant operand word. The least significant 23 bits of a double length operand are stored left-justified in the least significant word; bit 23 of this word is always zero.
INDICATORS
If the computed difference overflows, the arithmetic anomalies indicator in the interrupt indicator register will be set. The condition code register is set by the most significant difference word; i.e., by the final contents of R.sup.a.
EFFECTIVE ADDRESS
The global effective address, which may be formed by indexing and multilevel indirect addressing, points to the first or most significant full-word of a double-word operand.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 4.5 6.0SP -- Subtract Parallel O,R.sup.a *A,R.sup.x*R.sup.x 54 R.sup.a Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
The Subtract Parallel instruction is used to simultaneously subtract two adjacent half-words in storage from two half-words in a general purpose register. The two half-words in storage must be in the left and right halves of a full-word and cannot cross over a full-word boundary.
OPERATION
The right half-word of the contents of the global effective address are subtracted from R.sub.r.sup.a and the difference stored in R.sub.r.sup.a. The left half-word is subtracted from R.sub.l.sup.a and the difference stored in R.sub.l.sup.a.
INDICATORS
An overflow in the left half difference will cause the arithmetic anomalies indicator in the interrupt indicator register to be set. The condition code register is set by the left half difference.
EFFECTIVE ADDRESS
The global effective address points to a full-word and the least significant bit of the ADDRESS field and any referenced index register is not decoded. Indexing and indirect addressing are allowed.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 2.0 3.5SPG -- Subtract Parallel (G) Register O,R.sup.a R.sup.c R.sup.c 55 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Subtract Parallel Register is a short instruction used to simultaneously subtract two half-words in one general purpose register from two half-words in another general purpose register.
OPERATION
The contents of a R.sub.l.sup.c are subtracted from the contents of R.sub.l.sup.a and the result stored in R.sub.l.sup.a. The contents of R.sub.r.sup.c are subtracted from the contents of R.sub.r.sup.a and the difference stored in R.sub.r.sup.a. R.sup.c is left unchanged.
INDICATORS
The condition code register is set according to the left-half difference. The arithmetic anomalies indicator in the interrupt indicator, register is set if the left-half difference overflows.
EFFECTIVE ADDRESS
Indirect addressing and indexing may be specified in computing the multiple address. The least significant bit (No. 23) of the effective address is not decoded.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete______________________________________1.5 5.25MG -- Multiply Register O,R.sup.a R.sup.c R.sup.c 61 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
The Multiply Register instruction is used to form the double-word length product of two single-word length operands both located in general purpose registers. The product is stored in two consecutively addressed general purpose registers.
OPERATION
The contents of general purpose register R.sup.c (the multiplier) are multiplied by the contents of general purpose register R.sup.a (the multiplicand). The double-word length product is stored in general purpose register's R.sup.a and R.sup.(a.sup.+1) mod 8. R.sub.o.sup.a contains the most significant product word; R.sup.a is the product sign bit. R.sup.(a.sup.+1 mod 8) contains the least significant 23-bit product word; this word is left-justified with bit 23 always set to 0.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ 0.5 1.5M -- Multiply O,R.sup.a *A,R.sup.x*R.sup.x 60 R.sup.a Address (2048 full-word)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
The Multiply instruction is used to form the double-word length product of a single-word length multiplicand located in a general purpose register and a single-word length multiplier located in storage. The product is stored in two consecutively addressed general purpose registers.
OPERATION
The contents of general purpose register R.sup.a are multiplied by the contents of the computed effective address location. The double-word length product is stored into general purpose registers R.sup.a and R.sup.(a.sup.+1) mod 8. R.sup.a contains the most significant product word; R.sub.o.sup.a is the product sign bit. R.sup.(a.sup.+1) mod 8) contains the least significant 23-bit product word; this word is left-justified with bit 23 always set to 0.
INDICATORS
The final contents of R.sup.a are used to set the condition code register.
TIMING, .mu.s
Look-Ahead StatusComplete______________________________________4.75MT -- Multiply Truncated O,R.sup.a *A,R.sup.x*R.sup.x 21 R.sup.a Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Multiply Truncated is used to form a single-word length product of a single word length multiplicand located in a general purpose register by a single-word length multiplier located in storage. The most significant product word is stored in the general purpose register.
OPERATION
The contents of general purpose register R.sup.a are multiplied by the contents of the computed effective address location. The most significant product word is stored in general purpose register R.sup.a ; the least significant product half is lost. R.sup.(a.sup.+1) mod 8 is not changed.
INDICATORS
The final contents of R.sup.a are used to set the condition code register.
EFFECTIVE ADDRESS
Indirect Addressing and indexing may be specified in computing the multiplier address. The least significant bit (No. 23) of the effective address is not decoded.
TIMING, .mu.s
Look-Ahead StatusIndirect Addressing,.mu.s/level Complete______________________________________1.5 5.25MH -- Multiply Half O,R.sup.a *A,R.sup.x*R.sup.x 62 R.sup.a Address (4096 half-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Multiply Half is used to form the full-word length product of a left half-word multiplicand located in a general purpose register and a half-word multiplier located in storage. The product is stored in the general purpose register.
OPERATION
The contents of the left half of general purpose register R.sup.a (i.e., R.sub.l.sup.a) are multiplied by the contents of the half-word specified by the computed effective address. The full-word product is stored in general purpose register R.sup.a. The previous contents of R.sub.r.sup.a are lost.
INDICATORS
The final contents of R.sup.a are used to set the condition code register.
EFFECTIVE ADDRESS
Indirect Addressing and indexing may be used in computing the multiplier address. The least significant address bit indicates which storage word half is to be used; 0 refers to the left and 1 to the right.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete______________________________________1.5 3.75MHG -- Multiply Half Register O,R.sup.a R.sup.c R.sup.c 63 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
The Multiply Half Register instruction is used to form the full-word length product of two half-word operands that are both located in general purpose registers. The product is stored in a general purpose register.
OPERATION
The contents of the left half of general purpose register R.sup.a (the multiplicand) are multiplied by those of the left half of general purpose register R.sup.c (the multiplier). The full-word product is stored in general purpose register R.sup.a. The previous contents of R.sub.r.sup.a are lost.
INDICATORS
The final contents of R.sup.a are used to set the condition code register.
TIMING, .mu.s
Look-Ahead StatusComplete______________________________________3.25MHI -- Multiply Half, Immediate O,R.sup.a Y6 24 R.sup.a Immediate Operand0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Multiply Half, Immediate can be used to multiply the left half of a general purpose register by any half-word constant directly without the need of additional half-word operand storage space. The full-word product is stored in the general purpose register. MHI is particularly useful for scaling operations in half-word arithmetic.
OPERATION
The contents of the left half of general purpose register R.sup.a (the multiplicand) are multiplied by the instruction immediate operand, which is treated as a signed, half-word multiplier. The full-word length product is stored in general purpose register R.sup.a. The previous contents of R.sub.r.sup.a are lost.
INDICATORS
The final contents of R.sup.a are used to set the condition code register.
TIMING, .mu.s
Look-Ahead StatusComplete______________________________________3.25D -- Divide O,R.sup.a *A,R.sup.x*R.sup.x 76 R.sup.a Address (2096 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
The Divide instruction is used to divide a double-word length dividend located in two consecutive general purpose registers by a single-word length divisor located in storage. Both the single-word length quotient and remainder are stored in general purpose registers.
OPERATION
The contents of general purpose register R.sup.a and those of R.sup.(a.sup.+1) mod 8 are treated as a double-length dividend which is divided by the single-word length divisor in storage specified by the computed effective address. The single-word length quotient is stored in general purpose register R.sup.a and the single-word length remainder stored in R.sup.(a.sup.+1) mod 8. Saturation division is performed; the quotient is set (-1) or (1-2.sup..sup.-23) depending on operand signs whenever the fractional quotient range is exceeded, and the remainder is set to zero. The non-zero remainders have the same sign as the dividend.
INDICATORS
The final contents of R.sup.a are used to set the condition code register. If a division by zero is attempted or a saturated quotient generated, the arithmetic anomaly indicator bit is set to 1.
EFFECTIVE ADDRESS
Indirect Addressing and indexing may be specified in computing the divisor address. The least significant bit (No. 23) of the effective address is not decoded.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete______________________________________1.5 15.00DG -- Divide Registers by Register O,R.sup.a R.sup.c R.sup.c 77 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Divide Registers by Register is used to divide a double-word length dividend located in two consecutive general purpose registers by a single-word length divisor located in another general purpose register. Both quotient and remainder are saved. This instruction is shorter and faster than D.
OPERATION
The contents of general purpose register R.sup.a and those of R.sup.(a.sup.+) mod 8 are treated as a double-word length dividend which is divided by a single-word length divisor located in general purpose register R.sup.c. The single-word length quotient is stored in general purpose register R.sup.a, and the single-word length remainder stored in R.sup.(a.sup.+1) mod 8. Saturation division is performed where the quotient is set to (-1) or (1-2.sup..sup.-23) depending on operand signs whenever the fractional quotient range is exceeded, and the remainder set to zero. Non-zero remainders have the same sign as the dividend.
INDICATORS
The final contents of R.sup.a are used to set the condition code register. If a division by zero is attempted or a saturated quotient generated, the arithmetic anomaly indicator bit is set to 1.
TIMING, .mu.s
Look-Ahead StatusComplete______________________________________14.50DT -- Divide Truncated O,R.sup.a *A,R.sup.x*R.sup.x 37 R.sup.a Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
The Divide Truncated instruction is used to divide a single-word length dividend located in a general purpose register by a single-word length divisor located in storage. The single-word length quotient is stored in the general purpose register, and the remainder is lost. DT is preferred over D wherever 24-bit dividend precision is sufficient, since one general purpose register is freed.
OPERATION
The contents of general purpose register R.sup.a (the dividend are divided by those of the single-word length divisor specified by the computed effective address. The single-word length quotient is stored in general oyroise register R.sup.a, and the remainder is lost. Saturation division is performed where the quotient is set to (-1) or (1-2.sup..sup.-23) depending on operand signs whenever the fractional quotient range is exceeded. R.sup.(a.sup.+1) mod 8 is not changed.
INDICATORS
The final contents of R.sup.a are used to set the condition code register. If division by zero is attempted or a saturated quotient generated, the arithmetic anomaly indicator bit is set to 1.
EFFECTIVE ADDRESS
Indirect Addressing and indexing may be specified in computing the divisor address. The least significant bit (No. 23) of the effective address is not decoded.
TIMING, .mu.s
Indirect Address, Look-Ahead Status.mu.s/level Complete______________________________________1.5 15.00DHI -- Divide Half Immediate O,R.sup.a Y7 24 R.sup.a Immediate Operand0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Divide Half Immediate is used to divide a full-word length dividend located in a general purpose register by a half-word constant directly, without the need of additional half-word operand storage space. DHI is particularly useful for scaling operations in half-word arithmetic.
OPERATION
The contents of general purpose register R.sup.a are divided by the instruction immediate operand, which is treated as a signed, half-word divisor. The half-word quotient is stored in the left half of general purpose R.sup.a, and the half-word remainder in its right half. Saturation division is performed; the quotient is set to (-1) or (1-2.sup.11) depending on operand signs whenever the fractional quotient range is exceeded, and the remainder set to zero. Non-zero remainders have the same sign as the dividend.
INDICATORS
The final contents of R.sub.l.sup.a are used to set the condition code register. If a division by zero is attempted or a saturated quotient generated, the arithmetic anomaly indicator bit is set to 1.
TIMING, .mu.s
Look-Ahead StatusComplete8.50
LOGICAL INSTRUCTIONS
This instruction set has two types of logical instructions. The logical instructions that perform And, Or, Compare, or Clear operations involve two operands; the first is always located in one of the processor registers while the second is located in main memory, local store, a general purpose register, or an immediate operand field in the instruction format. The logical instructions that perform complementing or absolute value operations involve a single operand that is always located in a general purpose register. All logical instructions except CSW and OW set the condition code register with the results of the operation and thus provide the following information.
______________________________________Condition Code Setting, bits 1 2 Result Value______________________________________ 0 1 Negative 1 0 Zero 1 1 PositiveN -- AND Memory to Register 0,R.sup.a *A,R.sup.x*R.sup.x 74 R.sup.a Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
The And instruction is used to form the logical "AND" of a full-word storage location and a general purpose register and to store the result in that same register.
OPERATION
The contents of general purpose register R.sup.a are logically AND's with those of the storage location specified by the computed effective address. The result is returned to R.sup.a, and the storage location contents remain unchanged.
INDICATORS
The condition code register is set by the final contents of R.sup.a.
EFFECTIVE ADDRESS
Indexing and indirect addressing may be used in computing the effective address. A 24-bit operand is accessed. The least significant bit (No. 23) of the effective address is not decoded.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 2.0 3.5NG -- AND Register to Register O,R.sup.a R.sup.c R.sup.c 75 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
And Register to Register is used to form the logical "AND" of two full-word general purpose registers and to store the result in one. This instruction executes more quickly than N and can be stored in a half-word storage location.
OPERATION
The contents of general purpose register R.sup.a are logically AND'd with those of register R.sup.c. The result is stored in register R.sup.a, and the contents of R.sup.c remain unchanged.
INDICATORS
The condition code register is set by the final contents of R.sup.a.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ 0.5 1.5E -- Exclusive OR Memory to Register O,R.sup.a *A,R.sup.x*R.sup.x 66 R.sup.a Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Exclusive Or Memory to Register is used to form the logical exclusive "OR" of a full-word storage location and a general purpose register and to store the result in that same register.
OPERATION
The contents of general purpose register R.sup.a are logically "OR'd" (exclusively) with those of the storage location specified by the computed effective address. The result is returned to R.sup.a and the storage location contents remain unchanged.
INDICATORS
The condition code register is set by the final contents of R.sup.a.
EFFECTIVE ADDRESS
Indexing and indirect addressing may be used in computing the effective address. A 24-bit operand is accessed. The least significant bit (No. 23) of the effective address is not decoded.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 2.0 3.5NG -- AND Register to Register O,R.sup.a R.sup.c R.sup.c 75 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
And Register to Register is used to form the logical "AND" of two full-word general purpose registers and to store the result in one. This instruction executes more quickly than N and can be stored in a half-word storage location.
OPERATION
The contents of general purpose register R.sup.a are logically AND's with those of register R.sup.c. The result is stored in register R.sup.a, and the contents of R.sup.c remain unchanged.
INDICATORS
The condition code register is set by the final contents of R.sup.a.
TIMING, .mu.s
Look-Ahead StatusComplete None______________________________________0.5 1.5E -- Exclusive OR Memory to Register O,R.sup.a *A,R.sup.x*R.sup.x 66 R.sup.a Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Exclusive Or Memory to Register is used to form the logical exclusive OR of a full-word storage location and a general purpose register and to store the result in that same register.
OPERATION
The contents of general purpose register R.sup.a are logically OR'd (exclusively) with those of the storage location specified by the computed effective address. The result is returned to R.sup.a and the storage location contents remain unchanged.
INDICATORS
The condition code register is set by the final contents of R.sup.a.
EFFECTIVE ADDRESS
Indexing and indirect addressing may be used in computing the effective address. A 24-bit operand is accessed. The least significant bit (No. 23) of the effective address is not decoded.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 2.0 3.5O -- OR Memory to Register O,R.sup.a *A,R.sup.x*R.sup.x 64 R.sup.a Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
The Or Memory to Register instruction is used to form the logical inclusive OR of a full-word storage location and a general purpose register and to store the result in that same register.
OPERATION
The contents of general purpose register R.sup.a are logically OR'd (inclusively) with those of the storage location specified by the computed effective address. The result is returned to R.sup.a, and the storage location contents remain unchanged.
INDICATORS
The condition code register is set by the final contents of R.sup.a.
EFFECTIVE ADDRESS
Indexing and indirect addressing may be used in computing the effective address. A 24-bit operand is accessed. The least significant bit (No. 23) of the effective address is not decoded.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 3.0 3.5OG -- OR Register to Register O,R.sup.a R.sup.c R.sup.c 65 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Or Register to Register is used to form the logical inclusive OR of two full-word general purpose registers and to store the results in one. This instruction executes more quickly than 0 and can be stored in a half-word storage location.
OPERATION
The contents of general purpose register R.sup.a are logically OR'd (inclusively) with those of register R.sup.c. The result is stored in register R.sup.a, and the contents of R.sup.c remain unchanged.
INDICATORS
The condition code register is set by the final contents of R.sup.a.
TIMING, .mu.s
Look-Ahead StatusComplete______________________________________2.5OW -- OR Register to Working Register O,R.sup.c W.sup.a W.sup.a 67 R.sup.c 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
The Or Register to Working Register instruction is used to form the logical inclusive OR of a full-word general purpose register to a full-word working register and to store the result in the working register. OW is particularly useful for setting interrupt indicator mask bits in W.sup.3 (working register 3).
OPERATION
The contents of general purpose register R.sup.c are logically OR'd inclusively with those of working register W.sup.c. The result is returned to W.sup.a and the contents of R.sup.c remain unchanged.
INDICATORS
None.
TIMING, .mu.s
Look-Ahead StatusComplete None______________________________________0.5 1.5CSW -- Clear Selective Working O,R.sup.c W.sup.a W.sup.a 27 R.sup.c 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Clear Selective Working instruction is used to clear to zero individual bits within a working register as selected by set bits (i.e., 1's) in a general purpose register. CSW is particularly useful resetting interrupt indicator and interrupt mask bits.
OPERATION
The contents of general purpose register R.sup.c, logically inverted, are "AND'd" with the contents of working register W.sup.a, and the result is stored in W.sup.a. The contents of R.sup.a remain unchanged.
INDICATORS
None.
TIMING, .mu.s
Look-Ahead StatusComplete None______________________________________0.5 1.5K -- One's Complement Register O,R.sup.a 0 25 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
The One's Complement Register instruction is used to form the one's complement of the full-word contents of a general purpose register and to store the results in that same register.
OPERATION
The contents of general purpose register R.sup.a are replaced by their one's complement.
INDICATORS
The condition code register is set by the final contents of R.sup.a.
TIMING, .mu.s
Look-Ahead StatusComplete None______________________________________0.5 1.5KH -- One's Complement Register Left Half O,R.sup.a 2 25 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
One's Complement Register Left Hand is used to form the one's complement of a general purpose register's left half and store the result in the left half of the same register.
OPERATION
The contents of R.sub.l.sup.a are replaced by their one's complement. The contents of R.sub.r.sup.a remain unchanged.
INDICATORS
The condition code register is set by the final contents of R.sub.l.sup.a.
TIMING, .mu.s
Look-Ahead StatusComplete None______________________________________0.5 1.5T -- Two's Complement Register O,R.sup.a 1 25 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
The Two's Complement Register instruction is used to form the two's complement of the full-word contents of a general purpose register and to store the results in that same register.
OPERATION
The contents of general purpose register R.sup.a are replaced by their two's complement.
INDICATORS
The condition code register is set by the final contents of R.sup.a.
TIMING, .mu.s
Look-Ahead StatusComplete None______________________________________0.5 1.5TH -- Two's Complement Register Left Half O,R.sup.a 3 25 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Two's Complement Register Left Half is used to form the two's complement of a general purpose register's left half and to store the result in the left half of the same register.
OPERATION
The contents of R.sub.l.sup.a are replaced by their two's complement. The contents of R.sub.r.sup.a remain unchanged.
INDICATORS
The condition code register is set by the final contents of R.sub.l.sup.a.
TIMING, .mu.s
Look-Ahead StatusComplete None______________________________________0.5 1.5ABS -- Absolute Value of Register O,R.sup.a 5 25 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Absolute Value of Register is used to form the absolute value of the full-word contents of a general purpose register and to store the result in that same register.
OPERATION
The contents of general purpose register R.sup.a, treated as a signed two's complement number, are replaced by their absolute numerical value.
INDICATORS
The final contents of R.sup.a are used to set the condition code register.
TIMING, .mu.s
Look-Ahead StatusComplete None______________________________________0.5 1.5C -- Compare Register to Memory O,R.sup.a *A,R.sup.x*R.sup.x 70 R.sup.a Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Compare Register to Memory is used to arithmetically compare the full-word contents of a storage location to those of a general purpose register. It provides a means of setting the condition code register directly without altering either operand.
OPERATION
If the sign bits of the contents of the storage location specified by the computed effective address and the contents of general purpose register R.sup.a are the same, then the contents of the computed effective address are subtracted from the contents of general purpose register R.sup.a and the result sets the condition code register which indicates their relative magnitudes. If the sign bits of the contents of the computed effective address and the general purpose register are not the same, then the condition code register is set to the sign but of general purpose register R.sup.a. The contents of both R.sup.a and the computed effective address remain unchanged.
INDICATORS
The condition code register is set as described above under OPERATION.
EFFECTIVE ADDRESS
Indexing and indirect addressing may be used in computing the effective address. A 24-bit operand is accessed. The least significant bit (No. 23) of the effective address is not decoded.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 2.0 3.5CG -- Compare Register to Register O,R.sup.a R.sup.c R.sup.c 71 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
The Compare Register to Register instruction is used to arithmetically compare the contents of two general purpose registers. It provides a means of setting the condition code register directly without altering either operand. CG executes more quickly than C and can be stored in a half-word storage location.
OPERATION
If the sign bits of the contents of general purpose registers R.sup.a and R.sup.c are the same, then the contents of general purpose register R.sup.c are subtracted from those of general purpose register R.sup.a and the condition code register set to indicate their relative magnitudes. If the sign bits of the contents of general purpose registers R.sup.a and R.sup.c are not the same, then the condition code register is set to the sign bit of general purpose register R.sup.a. The contents of both general purpose registers R.sup.a and R.sup.c remain unchanged.
INDICATORS
The condition code register is set as described above under OPERATION.
TIMING, .mu.s
Look-Ahead StatusComplete None______________________________________0.5 1.5CH -- Compare Register Left Half to O,R.sup.a *A,R.sup.x Memory Half*R.sup.x 72 R.sup.a Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Compare Register Left Half to Memory Half is used to arithmetically compare a half-word storage location to the left half of a general purpose register. It provides a means of setting the condition code register directly without altering either operand.
OPERATION
If the sign bits of the contents of the half-word storage location specified by the computed effective address and the contents of general purpose register R.sup.a are the same, then the contents of the half-word location specified by the computed effective address are subtracted from the left half of general purpose register R.sup.a and the condition code register set properly to indicate their relative magnitudes. If the sign bits of the contents of the computed effective address and general purpose register are not the same, then the condition code register is set to the sign bit of general purpose register R.sup.a. The contents of both R.sup.a and the computed effective address remain unchanged.
INDICATORS
The condition code register is set as described above under OPERATION.
______________________________________CH -- Compare Register Left Half to O,R.sup.a *A,R.sup.x Memory Half______________________________________*R.sup.x 72 R.sup.a Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Compare Register Left Half to Memory Half is used to arithmetically compare a half-word storage location to the left half of a general purpose register. It provides a means of setting the condition code register directly without altering either operand.
OPERATION
If the sign bits of the contents of the half-word storage location specified by the computed effective address and the contents of general purpose register R.sup.a are the same, then the contents of the half-word location specified by the computed effective address are subtracted from the left half of general purpose register R.sup.a and the condition code register set properly to indicate their relative magnitudes. If the sign bits of the contents of the computed effective address and general purpose register are not the same, then the condition code register is set to the sign bit of general purpose register R.sup.a. The contents of both R.sup.a and the computed effective address remain unchanged.
INDICATORS
The condition code register is set as described above under OPERATION.
EFFECTIVE ADDRESS
Indexing and indirect addressing may be used in computing the effective address. A 12-bit operand is accessed. The least significant address bit indicates which storage word half is addressed; 0 refers to the left and 1 to the right half.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 2.0 3.5CHG -- Compare Half Register to Half Register O,R.sup.a R.sup.c R.sup.c 73 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
The Compare Half Register to Half Register instruction is used to arithmetically compare the contents of two general purpose register left halves. It provides a means of setting the condition code register directly without altering either operand.
OPERATION
If the sign bits of the contents of general purpose registers R.sup.a and R.sup.c are the same, then the contents of general purpose register R.sub.l.sup.c and the condition code register set to indicate their relative magnitudes. If the sign bits of the contents of general purpose registers R.sup.a and R.sup.c are not the the same, then the condition code register is set to the sign bit of general purpose register R.sup.a. The contents of both general purpose registers R.sup.a and R.sup.c remain unchanged.
INDICATORS
The condition code register is set as described above under OPERATION.
TIMING, .mu.s
Look-Ahead StatusComplete None______________________________________0.5 1.5CI -- Compare Immediate O,R.sup.a Y4 24 R.sup.a Immediate Operand0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
The Compare Immediate instruction is used to arithmetically compare the full contents of a general purpose register to a constant stored directly within the instruction word. This constant can range between -2048 and 2047 if considered as an integer value or between -2.sup.-.sup.12 and 2.sup.-.sup.12 -2.sup.-.sup.23 as a fractional value. CI can be executed more rapidly than C and is also more efficient of storage.
OPERATION
If the sign bits of the effective immediate operand and the contents of general purpose register R.sup.a are the same, then the effective immediate operand is subtracted from the contents of general purpose register R.sup.a and the condition code register set properly to indicate their relative magnitudes. If the sign bit of the effective immediate operand and general purpose register R.sup.a are not the same, then the condition code register is set to the sign bit of general purpose register R.sup.a. The contents of R.sup.a remain unchanged.
INDICATORS
The condition code register is set as described above under OPERATION.
EFFECTIVE IMMEDIATE OPERAND
BITS 12 through 23 of the effective immediate operand are identical to bits 12 through 23, respectively, of the immediate operand field. Bits 0 through 11 of the effective immediate operand are all identical to bit 12 of the IMMEDIATE OPERAND field (sign bit extension).
TIMING, .mu.s
Look-Ahead StatusComplete None______________________________________0.5 1.5CHI -- Compare Half Immediate O,R.sup.a Y5 24 R.sup.a Immediate Operand0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Compare Half Immediate is used to arithmetically compare the left half contents of a general purpose register to a constant stored directly within the instruction word. This constant can range between -2048 and 2047 if considered as an integer value, or between -2.sup.-.sup.12 and 2.sup.-.sup.12 -2.sup.-.sup.23 as a fractional value. CHI can be executed more quickly than CH and is also more efficient of storage.
OPERATION
If the sign bits of the effective immediate operand and the contents of general purpose register R.sup.1 are the same, then the effective immediate operand is subtracted from the contents of general purpose register R.sup.1 and the condition code register set properly to indicate their register magnitudes. If the sign bits of the effective immediate operand and general purpose are not the same, then the condition code register is set to the sign bit of general purpose register R.sup.1. The contents of R.sup.1 remain unchanged.
INDICATORS
The condition code register is set as described above under OPERATION.
EFFECTIVE IMMEDIATE OPERAND
The effective immediate operand is identical to the instruction IMMEDIATE OPERAND.
TIMING, .mu.s
Look-Ahead StatusComplete None______________________________________0.5 1.5CB -- Compare Bits O,R.sup.a *A,R.sup.x*R.sup.x 34 R.sup.a Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
The Compare Bits instruction is used to test for the set condition (i.e., 1) for those bits, in a general purpose register, selected by a mask word located in storage. This instruction is particularly useful in testing for specific bit patterns in data or control words.
OPERATION
For each bit set to 1 in the storage location mask word specified by the computed effective address, the corresponding bit is tested for the set condition. If all bits specified by the mask bit were set, the condition code register is set to 2 -- the equality state. If all bits were not set, the condition code register is set to 1. The mask word contents are not changed.
INDICATORS
The condition code register is set as described above under OPERATION.
EFFECTIVE ADDRESS
Indexing and indirect addressing may be used in computing the effective address. A 24-mask word is accessed. The least significant bit (No. 23) of the effective address is not decoded.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 3.0 3.5EXAMPLE 1: CB,1 Mask 1Before Execution After Execution(Mask 1) '01000507' '01000507'(R.sup.1) '01234567' '01234567'(CC) XX 10EXAMPLE 2: CB,1 Mask 2Before Execution After Execution(Mask 2) '00204013' '00204013'(R.sup.1) '01234567' '01234567'(CC) XX 01______________________________________
SHIFT INSTRUCTIONS
This instruction set contains nine shift instructions that perform arithmetic shifts, logical shifts, and rotations of 24-bit and 48-bit operands; a 24-bit normalizing shift is also provided.
All shift instructions except SLCT share a single operation code and use the following format. a a relative register are a a
______________________________________R.sup.x 22 R.sup.a OPE COUNT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
______________________________________Opcode Extender (OPE) Field Bit15 16 17 Shift Type______________________________________0 0 0 Shift Right, Arithmetic0 0 1 Shift Right, Logical0 1 0 Shift Right Double, Arithmetic0 1 1 Shift Right Double, Logical1 0 0 Shift Left, Cyclic1 0 1 Shift Left1 1 0 Shift Left Double, Cyclic1 1 1 Shift Left Double, Arithmetic______________________________________
Each instruction operates on one of the eight general purpose registers, which is specified in bits 9 through 11. Bits 18 through 23 comprise the 6-bit immediate count field, but this count can be modified by an indexing operation before execution of the shift instruction; in this case, the right-most 6 bits of the resulting effective count are used to specify the shift length. The count field has no sign bit; all counts are assumed to be positive in the direction specified by the opcode extender field.
Double-register shift operations treat the contents of two adjacent general purpose register pairs as a single double-word operand 48 bits in length. Double arithmetic operands possess a single sign bit, which is located in the second (low-order) register contains its most significant data bit; bit 23 of this register is arbitrary.
All shift instructions set the condition code register at the completion of the shift, to provide the following information:
Condition Code Setting1 2 Shift Type______________________________________0 1 Negative1 0 Zero (loss of arithmetic significance1 1 Positive______________________________________
In addition, if, during the execution of a left shift, SLCT and cyclic shift excepted, a change in the sign bit occurs, then bit 4 of the interrupt Indicator Register (w.sup.2) is set to signify that an arithmetic anomaly has occurred. This interrupt indicator is maskable under program control.
______________________________________SRA -- Shift Right, Arithmetic O,R.sup.a K,R.sup.x______________________________________R.sup.x 22 R.sup.a 0 0 0 Count0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Shift Right, Arithmetic is used to right shift single-word length arithmetic operands located in a general purpose register. The original sign bit is copied and inserted into the vacated bit positions. This instruction also provides a more rapid means of dividing by a power of two than the use of any divide instruction.
OPERATION
The contents of the specified general purpose register (R.sup.a) are shifted 1 bit position to the right -- the number of times specified by the effective count. At each step, the sign bit is copied into the vacated bit position (No. 0), and bit 23 is lost.
INDICATORS
The final contents of R.sup.a are used to set the condition code register.
EFFECTIVE COUNT
The effective count is a 6-bit quantity copied from the instruction count field but which may optionally be modified by indexing.
TIMING, .mu.s
Look-Ahead StatusComplete(K+.phi.+8)/8______________________________________ 1 for odd K.phi. = 0 for even KSRL -- Shift Right, Logical O,R.sup.a K,R.sup.xR.sup.x 22 R.sup.a 0 0 1 Count0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Shift Right, Logical is used to right-shift single-word length logical operands located in a general purpose register. Leading zeros are inserted into vacated bit positions.
OPERATION
The contents of the specified general purpose register (R.sup.a) are shifted 1 bit position to the right -- the number of times specified by the effective count. At each step, a zero is inserted into bit position 0 following the right shift, and bit 23 is lost.
INDICATORS
The final contents of R.sup.a are used to set the condition code register.
EFFECTIVE COUNT
The effective count is a 6-bit quantity copied from the instruction count field but which may optionally be modified by indexing.
TIMING, .mu.s
Look-Ahead StatusComplete(K+.phi.+8)/8______________________________________ 1 for odd K.phi. = 0 for even KSL -- Shift Left O,R.sup.a K,R.sup.xR.sup.x 22 R.sup.a 1 0 1 Count0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Shift Left is used to left shift single-word length arithmetic or logical operands located in a general purpose register. Zero's are inserted into the vacated bit positions.
OPERATION
The contents of the specified general purpose register (R.sup.a) are shifted 1 bit position to the left -- the number of times specified by the effective count. At each step, a zero is inserted into bit position 23 following the left shift, and bit 0 is lost.
INDICATORS
The final contents of R.sup.a are used to set the condition code register. If a change also occurs in the sign bit of R.sup.a, during the execution of the shift, then the arithmetic anomaly indicator of the Interrupt Indicator register (w.sup.2) is set.
EFFECTIVE COUNT
The effective count is a 6-bit quantity, copied from the instruction count field but which may be optionally modified through indexing.
TIMING, .mu.s
Look-Ahead StatusComplete______________________________________(K+4)/4SLC -- Shift Left, Cyclic O,R.sup.a K,R.sup.xR.sup.x 22 R.sup.a 1 0 1 Count0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Shift Left, Cyclic is used to rotate a single-length word operand located in a general purpose register. Rotation takes place to the left, and bit 0 is copied into bit 23 at each cycle.
OPERATION
The contents of the specified general purpose register (R.sup.a) are shifted 1 bit position to the left -- the number of times specified by the effective count. At each step, bit 0 is saved and inserted into the vacated bit 23 position.
INDICATORS
The final contents of R.sup.a are used to set the condition code register.
EFFECTIVE COUNT
The effective count is a 6-bit quantity copied from the instruction count field but which may optionally be modified through indexing.
TIMING, .mu.s
Look-Ahead StatusComplete______________________________________(K+4)/4SRDA -- Shift Right Double, Arithmetic O,R.sup.a K,R.sup.xR.sup.x 22 R.sup.a 0 1 0 Count0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Shift Right Double, Arithmetic is used to right shift double-length arithmetic operands located in consecutively addressed general purpose registers. The sign bit (bit 0 of the most significant register contents) is copied and inserted into the vacated bit positions.
OPERATION
The contents of the specified general purpose register (R.sup.a) and those of the register whose address is next higher in the register bank (R.sup.(a.sup.+ 1) mod 8) are jointly right shifted 1 bit position. This cycle is repeated as specified by the effective count (bit 23 of R.sup.a is always shifted into bit 0 of R.sup.(a.sup.+1) mod 8). At each step, the previous sign bit is copied into R.sup.a 's vacated bit 0 position, and bit 23 of R.sup.(a.sup.+1) mod 8 is lost.
INDICATORS
The final contents of R.sup.a are used to set the condition code register.
EFFECTIVE COUNT
The effective count is a 6-bit quantity copied from the instruction count field but which may optionally be modified by indexing.
TIMING, .mu.s
Look-Ahead StatusComplete______________________________________(K+.phi.+16)/8 1 for odd K.phi. = 0 for even KSRDL -- Shift Right Double, Logical O,R.sup.a K,R.sup.xR.sup.x 22 R.sup.a 0 1 1 Count0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Shift Right Double, Logical is used to right shift double-length logical operands located in consecutively addressed general purpose registers. Leading zeros are inserted into vacated bit positions.
OPERATION
The contents of the specified general purpose register (R.sup.a) and those of the register whose address is next higher in the register bank (R.sup.(a.sup.+1) mod 8) are jointly right shifted 1 bit position. This cycle is repeated as specified by the effective count (bit 23 of R.sup.a is always shifted into bit 0 of R.sup.(a.sup.+1) mod 8). At each step, a zero is inserted into bit 0 of R.sup.a following the right shift, and bit 23 of R.sup.(a.sup.+1) mod 8 is lost.
INDICATORS
The final contents of R.sup.a are used to set the condition code register.
EFFECTIVE COUNT
The effective count is a 6-bit quantity copies from the instruction count field but which may be optionally modified by indexing.
TIMING, .mu.s
Look-Ahead StatusComplete______________________________________(K+.phi.+16)/8 1 for odd K.phi. = 0 for even KSLD -- Shift Left Double O,R.sup.a K,R.sup.xR.sup.x 22 R.sup.a 1 1 1 Count0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Shift Left Double is used to left shift doublelength arithmetic or logical operands located in consecutively addressed general purpose registers. Zeros are inserted into the vacated bit positions.
OPERATION
The contents of the specified general purpose register (R.sup.a) and those of the register whose address is next higher in the register bank (R.sup.(a.sup.+1) mod 8) are jointly left shifted 1 bit position. This cycle is repeated as specified by the effective count (Bit 0 of R.sup.(a.sup.+1) mod 8 is always shifted into bit 23 of R.sup.a. At each step, a zero is inserted into bit position 23 of R.sup.(a.sup.+1) mod 8 following the left shift, and bit 0 of R.sup.a is lost.
INDICATORS
The final contents of R.sup.a are used to set the condition code register. If a change also occurs in the sign bit of R.sup.a during the execution of the shift, then the arithmetic anomaly indicator of the interrupt indicator register (w.sup.2) is set.
EFFECTIVE COUNT
The effective count is a 6-bit quantity copied from the instruction count field but which can optionally be modified by indexing.
TIMING, .mu.s
Look-Ahead StatusComplete______________________________________(K+8)/4SLDC -- Shift Left Double, Cyclic O,R.sup.a K,R.sup.xR.sup.x 22 R.sup.a 1 1 0 Count0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Shift Left Double, Cyclic is used to rotate a doublelength operand located in consecutively addressed general purpose registers. Rotation occurs to the left.
OPERATION
The contents of the specified general purpose register (R.sup.a) and those of the register whose address is next higher in the register bank (R.sup.(a.sup.+1) mod 8) are jointly left-shifted 1 bit position. This cycle is repeated as specified by the effective count. Bit 0 of R.sup.(a.sup.+1) mod 8 is copied into bit 23 of R.sup.a, while bit 0 of R.sup.a is copied into bit 23 of R.sup.(a.sup.+1) mod 8.
INDICATORS
The final contents of R.sup.a are used to set the condition code register.
EFFECTIVE COUNT
The effective count is a 6-bit quantity copied from the instruction count field, but which can be optionally modified by indexing.
TIMING, .mu.s
Look-Ahead StatusComplete______________________________________(K+8)/4SLCT -- Shift Left and Count O,R.sup.a R.sup.c R.sup.c 23 R.sup.a 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Shift Left and Count is useful for normalizing (or left justifying and counting) a single word operand located in a general purpose register. One bit left shift cycles are executed until bits 0 and 1 are not identical or until 23 shifts have occurred. Zero's are inserted into the vacated bit positions.
OPERATION
Bits 0 and 1 of the specified general purpose register (R.sup.a) are tested for equality. If they are identical, a sequence of 1 bit left shifts are performed until either the inequality condition is met or 23 shift cycles have occurred. Zero's are inserted into bit position 23 in each shift cycle. The number of cycles (possibly 0) are then loaded, right justified with leading zero's, into general purpose register R.sup.c. R.sup.c may also equal R.sup.a, in which case the count is retained but the shift register is lost. (Caution: SLCT should not be used as the next instruction in logical sequence after executing a BAL instruction, as the count register R.sup.c may not be properly initialized.)
The contents of R.sup.a following the last shift cycle are used to set the condition code register.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ (K+6)/4 (K+10)/4______________________________________
BRANCH INSTRUCTIONS
This instruction set contains nine branch instructions used to alter the program sequence either unconditionally or conditionally. These instructions permit unconditional branch capabilities, and a decrement and conditional branch instruction to facilitate loop control.
The set of branch instructions, can be used to alter the program sequence either unconditionally or conditionally. If a program branch is unconditional, the next instruction to be executed is located by the branch instruction's computed effective address. If the branch is conditional and the conditions for the branch are currently satisfied, then the next instruction executed is again located by the branch instruction's effective address; otherwise the next instruction to be executed is that instruction immediately following the branch instruction in the current program sequence.
The two unconditional branch instructions B and BAL, and BCT each have unique operation code assignments; the remaining six conditional branch instructions share a single operation code and use the following format.
______________________________________OPCODEExtender 31 ADDRESS (32, 768 Half-Words)______________________________________0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
Bit positions 0 through 2 contain an opcode extender field. This field, in effect, indicates by set bits one or more of the three mutually exclusive condition code register states to be tested for by the branch instruction. If the condition code register is in a state corresponding to a set bit in the extended opcode field when the conditional branch instruction is executed, the program branch is taken; otherwise the branch is not taken and the next sequential instruction executed. The correspondence between condition code states and opcode extender bits is given below:
CorrespondingCondition Code Extended OpcodeRegister State Indication Field BitK.sub.1 K.sub.2______________________________________0 1 < or negative 01 0 = or zero 11 1 > or positive 20 0 Never occurs None______________________________________
Thus, the bit pattern in the instruction opcode extender field specifies the conditions to be met by a conditional branch.
______________________________________OpcodeExtenderField Bits Mnemonic Branch Instruction Name0 1 2______________________________________1 0 0 BL Branch if less than1 1 0 BLE Branch if less than or equal1 0 1 BNE Branch if not equal0 1 0 BE Branch if equal0 1 1 BGE Branch if greater or equal0 0 1 BG Branch if greater than(1 1 1) -- (Branch unconditionally)(0 0 0) -- (No operation)BL -- Branch if Less Than O A100 31 Address (32,768 half-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Branch if Less Than is used to cause a program branch if the condition code register is currently set to its negative state.
OPERATION
The condition code register state is compared with the set bits of the instruction opcode extender field (i.e., bit 0). If the register is in a corresponding state (less than), then the instruction effective address is loaded into the program counter (w.sup.o). Otherwise, the program counter is incremented.
INDICATORS
None.
EFFECTIVE ADDRESS
The effective address is the instruction immediate address.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ (not taken) (not taken) (taken) 0.50 2.00 2.50BLE -- Branch if Less Than or Equal O A1 1 0 31 Address (32,768 half-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Branch if Less Than or Equal is used to cause a program branch if the condition code register is currently set to either its negative or zero state.
OPERATION
The condition code register state is compared with the set bits of the instruction opcode extender field (i.e., bits 0 and 1). IF the register is in a corresponding state (less than or equal to), then the instruction effective address is loaded into the program counter (w.sup.o). Otherwise, the program counter is incremented.
INDICATORS
None
EFFECTIVE ADDRESS
The effective address is the instruction immediate address.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ (not taken) (not taken) (taken) 0.50 2.00 2.50BNE -- Branch if Not Equal O A1 0 1 31 Address (32,768 half-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Branch if Not Equal is used to cause a program branch if the condition code register is currently set to either its negative or positive state.
OPERATION
The condition code register state is compared with the set bits of the instruction opcode extender field (i.e., bits 0 and 2). If the register is in a corresponding state (less than or greater than), then the instruction effective address is loaded into the program counter (w.sup.o). Otherwise, the program counter is incremented.
INDICATORS
None
EFFECTIVE ADDRESS
The effective address is the instruction immediate address.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ (not taken) (not taken) (taken) 0.50 2.00 2.50BE -- Branch if Equal To O A0 1 0 31 Address (32,768 half-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Branch if Equal To is used to cause a program branch if the condition code register is currently set to its zero state.
OPERATION
The condition code register state is compared with the set bits of the instruction opcode extender field (i.e., bit 1). If the register is in a corresponding state (equal), then the instruction effective address is loaded into the program counter (w.sup.o). Otherwise, the program counter is incremented.
INDICATORS
None
EFFECTIVE ADDRESS
The effective address is the instruction immediate address.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ (not taken) (not taken) (taken) 0.50 2.00 2.50BG -- Branch if Greater Than O A0 0 1 31 Address (32,768 half-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Branch if Greater Than is used to cause a program branch if the condition code register is currently set to its positive state.
OPERATION
The condition code register state is compared with the set bits of the instruction opcode extender field (i.e., bit 2). If the register is in a corresponding state (greater than), then the instruction effective address is loaded into the program (w.sup.o). Otherwise, the program counter is incremented.
INDICATORS
None
EFFECTIVE ADDRESS
The effective address is the instruction immediate address.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ (not taken) (not taken) (taken) 0.50 2.00 2.50BGE -- Branch if Greater or Equal O A0 1 1 31 Address (32,768 half-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Branch if Greater or Equal is used to cause a program branch if the condition code register is currently set to either its positive or zero state.
OPERATION
The condition code register state is compared with the set bits of the instruction opcode extender field (i.e., bits 1 and 2). If the register is in a corresponding state (greater than or equal to), then the instruction effective address is loaded into the program counter (w.sup.o). Otherwise, the program counter is incremented.
INDICATORS
None
EFFECTIVE ADDRESS
The effective address is the instruction immediate address.
TIMING .mu.s
Look-Ahead Status Complete None______________________________________ (not taken) (not taken) (taken) 0.50 2.00 2.50BCT -- Branch and Count O *A,R.sup.x*R.sup.x 32 Address (32,768 half-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Branch and Count is used to cause a program branch if a specific condition is met. A designated count is first decremented, and as long as the new value remains non-negative, the branch is taken. This instruction is used primarily to control programmed loops.
OPERATION
The contents of general purpose register R.sup.x are decremented by 2. If the new count value is positive or zero, the value is stored in register R.sup.x and the effective address loaded into the program counter (w.sup.o). If the new count value is negative, the value is discarded (i.e., R.sup.x is not changed), the program counter is incremented, and the next sequential program instruction executed. Any one of register R.sup.0 through R.sup.3 may be used as the count register R.sup.x.
INDICATORS
None
EFFECTIVE ADDRESS
Indirect addressing may be specified to modify the 15-bit immediate address field.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________ (not taken) (not taken) (taken)2.00 0.50 2.00 2.50B -- Branch Unconditionally O *A,R.sup.x*R.sup.x 30 Address (32,768 half-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Branch Unconditionally is used to alter a sequential program instruction stream and cause a program jump. This jump is usually to another memory location, but in general may be any HCM 231 system addressable location. The contents of the specified location will be treated as an instruction.
OPERATION
The effective instruction address is computed and loaded into the program counter; working register zero (w.sup.o). Instruction execution proceeds with the instruction located at the effective address.
INDICATORS
None
EFFECTIVE ADDRESS
Indirect addressing and indexing may be specified to modify the 15-bit immediate address field. The effective address can reference either a half- or full-word instruction beginning in either the left or right half of the specified location.
TIMING, .mu.s
Indirect Address,.mu.s/level Execution Time______________________________________2.00 2.00BAL -- Branch and Link O *A,R.sup.x* R.sup.x 33 Address (32,768 half-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
Branch and Link is used to alter sequential program execution and to allow a subsequent return to that sequence. This instruction is used primarily to enter subroutines. Returning to the calling program can be accomplished with an indirectly addressed or indexed B instruction; its computed effective address points to that location saving the program counter contents at the time of the subroutine call.
OPERATION
The updated contents of the program counter (w.sup.o) are loaded into the general purpose register specified by the instruction X field. (Any one of registers R.sup.0 through R.sup.3 may be selected, though R.sup.0 cannot be used if the subsequent return is made via indexing alone. The 18-bit program count is right justified in the general purpose register; leading bit positions are cleared to zeros.) The effective instruction address is then computed and loaded into the program counter. Instruction execution proceeds with the instruction located at the effective address.
INDICATORS
None
Indirect addressing may be specified to modify the 15-bit immediate address field. The effective address can reference either a half- or full-word instruction which may begin in either the left or right half of the specified location.
TIMING, .mu.s
Indirect Address,.mu.s/level Execution Time______________________________________2.00 2.00EXAMPLES:(1) BAL *JOE,1 Subroutine call . . . BU 00000.sub.0, 1 Subroutine return______________________________________
PROCESSOR CONTROL INSTRUCTIONS
This instruction set includes eight control instructions that can be used to enable or disable the interrupt system, lock or unlock low order memory cells, and set or reset BIT flags, as well as perform certain AGE functions.
The processor control instructions are used to exert control over the interrupt logic, system address interpretation, built-in-test flip-flop states, and to perform certain ground (test or preflight) computer operations. All control instructions except BIT are half-word instructions may be executed as required without altering any processor data storage location contents. Groups of control instructions are employed to accomplish these tasks.
Interrupt System Control -- Three instructions (ENT, DST, and DSIM) provide control over interrupt system operation. ENT and DST set and reset, respectively, the Tactical Interrupt enable flip-flop. DSIM disarms all interrupts during the following two instruction executions.
System Address Control -- SCM and SCP are used, respectively, to set a control flip-flop to its "memory" or "processor" position. In the processor position, system addresses below the local store address boundary are interpreted as referring to the appropriate cell or register contained within the processor, while in the memory position all system addresses are interpreted as referencing locations in main core memory.
Built-In-Test Mode Control -- BIT mode control is determined by the states of 12 distributed flip-flops that are selectively set or reset via the BIT instructions.
Aerospace Ground Equipment Operation -- The AGE and H instructions are used during ground or preflight operations in conjunction with external auxiliary checkout equipment; they are not employed in tactical computer modes. The processor control instructions are summarized in the following table.
______________________________________Instruction Name Mnemonic______________________________________Enable Tacticals ENTDisable Tacticals DSTDisable Interrupts Momentarily DSIMSet Control to Processor SCPSet Control to Memory SCMBuilt-in-Test BITAGE Control AGEHalt H______________________________________
Processor Control Instructions
The eight processor control instructions coordinate the interrupt system, system addressing, built-in-test, and the ground support equipment.
______________________________________ENT -- Enable Tacticals O 7 25 1 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Enable Tacticals is used to set the tactical interrupt control bit to the interrupt enable position. In this position, tactical interrupts are recognized by the processor unless they are either masked or the interrupt system is temporarily disarmed. Catastrophic interrupt recognition is not affected by this instruction, once an interrupt disarm interval ending after the second succeeding instruction has elapsed.
OPERATION
The tactical interrupt control flip-flop is set to one, and the interrupt disarm flip-flop is set to one. Barring subsequent interrupt system status changes, the disarm flip-flop will be reset to zero at the end of the second sequential instruction to be executed.
INDICATORS
None.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ 0.5 1.5DST -- Disable Tacticals O 7 25 0 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Disable Tacticals is used to reset the tactical interrupt control bit to the interrupt disable position. In this position, tactical interrupts will not be recognized by the processor even if they are unmasked and would be allowed otherwise. Catastrophic interrupt recognition is not affected by this instruction once an interrupt disarm interval ending after the second succeeding instruction has elapsed.
OPERATION
The tactical interrupt control flip-flop is reset to zero, and the interrupt disarm flip-flop is set to one. Barring subsequent interrupt system status changes, the disarm flip-flop will be reset to zero at the end of the second sequential instruction to be executed.
INDICATORS
None.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ 0.5 1.5DSIM -- Disable Interrupts Momentarily O 7 25 2 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Disable Interrupts Momentarily is used to temporarily disarm all interrupts, including the catastrophic interrupts from being permitted by the processor for the duration of the next two instructions to be executed. Then the interrupt system status reverts to its state before the DSIM instruction, unless the status has been altered during the two-instruction disarm period. This instruction is particularly useful as a means of allowing a subroutine return free from the possibility of interrupt occurrence.
OPERATION
The interrupt disarm flip-flop is set to one. Barring subsequent interrupt system status changes, the disarm flip-flop will be reset to zero at the end of the second sequential instruction to be executed.
INDICATORS
None
TIMING, .mu.s
Look-Ahead StatusComplete None______________________________________0.5 1.5SCP -- Set Control to Processor 07 25 40 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Set Control to Processor is used to set the processor main memory control bit to the processor address position. In this position, system addresses in the range of 0 to 127 fullwords refer to processor locations in the general purpose register bank (0 to 7), the working register bank (8 to 15), or local store cells (16 to 127), respectively, instead of the corresponding main memory locations. System addresses greater than 127 full words are not affected.
OPERATION
The processor main memory flip-flop is reset to 0.
INDICATORS
None.
TIMING, .mu.s
Look-Ahead StatusComplete None______________________________________0.5 1.5SCM -- Set Control to Memory 07 25 50 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Set Control to Memory is used to set the processor main memory control bit to the memory address position. In this position, system addresses in the range of 0 to 127 full-words refer to main memory locations instead of processor locations in the general purpose register or working register banks, or in the local store. System addresses greater than 127 full words are not affected.
OPERATION
The processor main memory flip-flop is set to 1.
INDICATORS
None.
TIMING, .mu.s
Look-Ahead StatusComplete None______________________________________0.5 1.5BIT -- Built-in-Test Y 36 Immediate Operand - Y0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
The Built-in-Test (BIT) instruction is used to set or reset one or more BIT flip-flops located throughout the computer and its associated I/O modules. Each flip-flop is assigned a BIT position in the instruction 12-bit immediate operand field, and its effect on the system is described below. The immediate operand field for operational tactical modes will be 3777.
In addition to the described test functions, the bit-12 flip-flop of the BIT instruction is forced to the one state at the power-on interrupt. This state will cause a no-go indication if the BIT instruction is not executed within 600 milliseconds with bit-12 reset.
OPERATION
Each of the BIT flip-flops is set or reset, depending on whether its corresponding Y-field bit is 1 or 0, respectively. The following BIT assignments have been made.
______________________________________BIT Flip-Flop Function and State______________________________________12 State 0 -- RDP and radar operational. State 1 -- Set RDP fault indicator and no-go lights on the BIT control panel and avionics status panel indicators latch on after 600 to 1800 milliseconds.13 State 0 -- Set I/O channel controller to test mode. State 1 -- Set I/O channel controller to tactical (normal) mode.14 State 0 -- Set BIT mode 041. State 1 -- Set tactical mode 041. Set with bit 15.15 State 0 -- Raise data valid to 041 unit for test data to enter RDP. State 1 -- Normal tactical operation of 041. Set with bit 14.16 Not used.17 State 0 -- Completes link between P-MUX register and C-MUX register for testing. State 1 -- Normal tactical operation of P-MUX channel.18 Not used.19 Not used.20 Not used.21 Not used.22 Not used.23 State 0 -- Set C-MUX to test mode. State 1 -- Set C-MUX to tactical mode.______________________________________
INDICATORS
None.
TIMING, .mu.s
Look-Ahead Status Complete None______________________________________ 0.5 1.5H -- Halt 0 6 25 0 1 2 3 4 5 6 7 8 9 10 11______________________________________
USAGE
Halt is used to halt the processor, if it is in the test mode, and await a start command. If the processor is not in the test mode, H performs a no-operation function.
OPERATION
(Operation details not finalized.)
INDICATORS
None.
TIMING, .mu.s
Look-Ahead Status Complete None 0.5 1.5
INPUT-OUTPUT CONTROL INSTRUCTIONS
This instruction set contains two I/O control instructions that are used in conjunction with the I/O system control units. I/O operations are performed in two modes:
1. Direct mode I/O, in which I/O operands are referenced directly by regular instructions via their system addresses, i.e., L, A, ST, etc.
2. Buffered mode I/O, in which I/O operands are transferred between the I/O system and memory (or processor) storage cells by autonomously operating I/O control units.
When buffered mode I/O is performed, the program controlled I/O control units are initiated, and possibly sampled or terminated, by the processor under program control. Two special I/O control instructions are used for these purposes.
Buffered I/O Transaction Initiation -- A buffered mode transation is initiated by transmitting a control word from the processor to the selected I/O control unit. A PCW instruction is executed and, in general, one PCW instruction is required for each transaction instance.
Buffered I/O Transaction Status Sampling -- The status of some I/O control units can be sampled as desired by the processor, with the option of terminating any currently executing transaction, using the LSC instruction.
______________________________________PCW: Place Control Word O,B *A,R.sup.x______________________________________*R.sup.x 17 B Address (2048 full-words)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
The Place Control Word instruction is used to initiate the action of a program controlled I/O control unit on a block of sequential I/O data items. Once initiated, the control unit performs the I/O transaction independently. They can accommodate data blocks of varying lengths, where data items themselves are either full- or half-word lengths.
OPERATION
The contents of the computed effective address are transmitted to the I/O control unit, specified by bits 9, 10 and 11 in the instruction. These contents are in the format corresponding to the type of control unit to be used.
INDICATORS
None.
EFFECTIVE ADDRESS
Indirect addressing and indexing may be specified, if desired, to form the effective address of the control word to be transmitted. The control word occupies a full memory word (24 bits). The least significant bit of the effective address formation is ignored in the address computation.
TIMING, .mu.s
Look-Ahead StatusIndirect Address,.mu.s/level Complete None______________________________________1.5 3.00 3.75EXAMPLE 1: PCW, 1 ABCBefore Execution After Execution(ABC) '0441 2500' '0441 2500'(I/O Controller XXXXXXXX '0441 2500'No. control reg.)LCW : Load Control Word O,R.sup.a Y20 R.sup.a S.A. C T I R X B0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23
USAGE
The Load Control Word instruction is used to determine the status of a selected I/O control unit. A 24-bit word containing status information is transmitted to a general purpose register.
OPERATION
The contents of the instruction's 12-bit y field (bits 12-23) are used to form the effective address, which is transmitted to the I/O control unit via the main bus. The control unit transmits its status information to the processor. The 24-bit status word sent by the control unit is loaded into general purpose register R.sup.a. The meaning of the control bits C, T and R, fields S.A. and B, and spare bit X are as follows:
Word Address H (i)S.A. C T I P Channel Subchannel X Word H (ii)R X Cont. All Zero's (iii)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22______________________________________23(i) Main Memory Address 0 0 0 0 0 0 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --(ii) Channel Controller Address 0 0 0 0 0 0 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --(ii) Direct Dependent Unit Address (Special I/O Module) 0 0 0 0 0 0 1 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --(iii) Input-Output Controller Address 0 0 0 0 1 0 1 1 0 -- -- -- 0 0 0 0 0 0 0 0 0 0 0 0 (a) 0 0 0 0 1 1 1 1 0 -- -- -- 0 0 0 0 0 0 0 0 0 0 0 0 (b) 0 0 0 0 1 1 1 0 0 -- -- -- 0 0 0 0 0 0 0 0 0 0 0 0______________________________________ (c) (a) Status Request (b) Status and Terminate Request (c) Assignment Command
__________________________________________________________________________ Bit PositionControl Name Control Address MeaningBit Word Word__________________________________________________________________________C Control Word Address Flag -- 4 C = 1 An independent I/O unit BitI I/O - Memory Partition Bit -- 6 I = 1 An I/O Address I = 0 A main memory addressP Channel Controller -- 7 P = 1 A channel controller Partition Bit address P = 0 An address external to any channel controllerR Block Transfer Controller -- 7 R = 1 A status request Status Request Bit R = 0 An I/O transmission assignment with no status requestH Half-Word Address Bit 23 23 H = 1 A least significant (right) word half H = 0 A most significant (left) word halfX Spare Control Bit -- 8 or 16 X = 0 (Hardwired)__________________________________________________________________________
INDICATORS
None.
EFFECTIVE ADDRESS
The effective address transmitted to the selected I/O control unit is formed by shifting the instruction y field contents (bits 12-23) to bit positions 0 through 11, respectively, and setting address bits 12 through 23 to zero. The control bits contained by the effective address are defined in the next section.
TIMING, .mu.s
Look-Ahead Status Complete 1.75EXAMPLE 1: LCW,7 `0261`Before Execution After Execution______________________________________(R.sup.7) XXXX XXXX 0441 0500(I/O Controller 0441 0500 0441 0500No. 11 control reg.)______________________________________
APPENDIX BPART I__________________________________________________________________________00630 ATV02 DATA 0 THETA(E) INITIAL PSD EL BY XT BO AT01200631 ATV03 DATA 0 THETA(D) INITIAL PSD AZ BY XT BO AT01300632 ATV04 DATA 0 L(E) EL B-2 AT01400633 ATV05 DATA 0 L(D) AZ B-2 AT015******** TRACKING FILTER VARIABLES FT002* FT003 BOUND 8 FT00400716 FTV0000 DATA,W 0 FT ROUT RETURN ADDRESS SAVE FT005 * FT00700720 FTV0001 DATA,W 0 R(TPA) FT B20 FT00800722 FTV0002 DATA,W 0 V(TPA) FPS B13 FT009 * FT01000724 FTV0010 DATA,H 0 T SECS B-3 (FILTER PER) FT01100725 FTV0011 DATA,H 0 T(NEW) SECS B-3 FT01200726 FTV0012 DATA,W 0 T(INS) SECS B1 FT012 10 * FT012 2000730 FTV0020 DATA 0 C(INS) INS F.C. COUNTER B11 FT012 30 * FT012 4000731 FTV0030 DATA 0 SNR(D) B6 FT012 50 * FT01300733 FTV0101 DATA,W 0 R(GC) FT B20 (RNG GATE CMD) FT0140073400736 FTV0102 DATA,W 0 V(GC) FPS B13 (VEL GATE CMD) FT01500740 FTV01021 DATA,W 0 V(GC)(OLD) FT015 10******** INDEPENDENT RNG AND VEL TRACKERS' GAINS FT121* FT12200744 FTV1501 DATA,H 0 K1(R) RANGE(R) GAIN ND B1 FT12300745 FTV1502 DATA,H 0 K2(R) VEL(R) GAIN FPS/FT B4 FT12400746 FTV1503 DATA,H 0 K3(R) ACCEL(R) GAIN FPS**2/FT B5 FT12500747 DATA,H 0 SPARE FT126 * FT12700750 FTV1512 DATA,H 0 K2(V) VEL(V) GAIN ND B2 FT12800751 FTV1513 DATA,H 0 K3(V) ACCEL(V) GAIN FPS**2/FPS B5 FT129* FT130******** KALMAN ANGLE TRACKER STATE VARIABLES FT201* FT20200754 FTV2011 DATA,W 0 EPS(P)(E) RADS B-2 FT20300756 FTV2012 DATA,W 0 OMEGA(LSP)(E) RADS/SEC B1 FT20400760 FTV2013 DATA,W 0 A(TP)(D) FPS**2B11 FT20500762 FTV2014 DATA,W 0 S(P)(E) RADS B-2 FT206 * FT20700764 FTV2021 DATA,W 0 EPS(P)(D) RADS B-2 FT20800766 FTV2022 DATA,W 0 OMEGA(LSP)(D) RADS/SEC B1 FT20900770 FTV2023 DATA,W 0 A(TP)(-E) EPS**2 B11 FT21000772 FTV2024 DATA,W 0 S(P)(D) RADS B-2 FT211* FT212******** KALMAN ANGLE TRACKER STATE TRANSITION MATRIX FT213* FT21400774 FTV2112 DATA,W 0 PHI(A)12 SEC B-2 FT21500776 FTV2113 DATA,W 0 PHI(A)13 SEC**2/FT B-17 FT21601000 FTV2122 DATA,W 0 PHI(A)22 ND B1 FT21701002 FTV2123 DATA,W 0 PHI(A)23 SEC/FT B-12 FT21801004 FTV2133 DATA,W 0 PHI(A)33 ND B1 FT21901006 FTV2144 DATA,W 0 PHI(A)44 ND B1 FT220* FT221******** KALMAN ANGLE TRACKER CO-VARIANCE MATRIX FT222* FT22301010 FTU2211 DATA,W 0 M(A)11 (RADS)**2 B-9 FT22401012 FTV2212 DATA,W 0 M(A)12 (RADS)*(RADS/SEC) B-8 FT22501014 FTV2213 DATA,W 0 M(A)13 (RADS)*(FPS**2) B2 FT22601016 FTV2214 DATA,W 0 M(A)14 (RADS)**2 B-9 FT22701210 FTV2222 DATA,W 0 M(A)22 (RADS/SEC)**2 B-8 FT22801022 FTV2223 DATA,W 0 M(A)23 (RADS/SEC)*(FPS**2) B3 FT22901024 FTV2224 DATA,W 0 M(A)24 (RADS/SEC)*(RADS) B-8 FT23001026 FTV2233 DATA,W 0 M(A)33 (FPS**2)**2 B13 FT23101030 FTV2234 DATA,W 0 M(A)34 (FPS**2)*(RADS) B2 FT23201032 FTV2244 DATA,W 0 M(A)44 (RADS)**2 B-9 FT233* FT234******** KALMAN ANGLE TRACKER TEMPORARY STORAGE FT235* FT235 1001034 FTV2400 DATA,W 0 FT TEMP0 FT23601036 FTV2401 DATA,W 0 FT TEMP1 FT23701040 FTV2402 DATA,W 0 FT TEMP2 FT23801042 FTV2403 DATA,W 0 FT TEMP3 FT23901044 FTV2404 DATA,W 0 FT TEMP4 FT240* FT241******** KALMAN ANGLE TRACKER GAINS FT242* FT24301046 FTV2501 DATA,W 0 K(A)1 EPS GAIN ND B1 FT24401050 FTV2502 DATA,W 0 K(A)2 OMEGA GAIN 1/SEC B4 FT24501052 FTV2503 DATA,W 0 K(A)3 AT GAIN FPS**2 B15 FT24601054 FTV2504 DATA,W 0 K(A)4 S GAIN ND B1 FT247* FT248******** KALMAN ANGLE TRACKER MOTION COMPENSATION FT24901056 FTV2611 DATA,W 0 L(E)1 RADS B-2 FT25301060 FTV2612 DATA,W 0 L(E)2 RADS/SEC B1 FT254 * FT25501062 FTV2621 DATA,W 0 L(D)1 RADS B-2 FT25601064 FTV2622 DATA,W 0 L(D)2 RADS/SEC B1 FT257 * FT257 1001066 FTV2631 DATA,H 0 ETA(T1)(AI01 AT T1) FT257 2001067 FTV2632 DATA,H 0 ETA(T2)(AI01 AT T2) FT257 3001070 FTV2633 DATA,W 0 ETA(DOT) RADS/SEC B3 FT257 40* FT258******** KALMAN ANGLE TRACKER MISC VARIABLES FT259* FT26001072 FTV2700 DATA,W 0 SIGMA(S)**2 B-9 FT26101074 FTV2701 DATA,W 0 TAU(S) SECS B1 FT26201076 FTV2702 DATA,W 0 RADOME COMPENSATION (EL) RADS B-2 FT26301100 FTV2703 DATA,W 0 RADOME COMPENSATION (AZ) RADS B-2 FT26401102 FTV2704 DATA,H 0 KE (EL DISCR SLOPE) B1 FT26501103 FTV2705 DATA,H 0 KD (AZ DISCR SLOPE) B1 FT26601104 FTV2706 DATA,W 0 RESIDUAL (EL) RADS B-3 FT26701106 FTV2707 DATA,W 0 RESIDUAL (AX) RADS B-3 FT268 * FT269 * FT300******** OWN SHIP VARIABLES FT301* FT30201110 FTV3001 DATA,W 0 AI(R)(ANT COORDS) FPS**2B11 FT30301112 FTV3002 DATA,W 0 AI(E) B11 FT30401114 FTV3003 DATA,W 0 AI(D) B11 FT305 * FT30601116 FTV3111 DATA,W 0 V(N)1 FPS B12 INS VEL BUFFER FT30701120 FTV3112 DATA,W 0 V(E)1 FPS B12 FT30801122 FTV3113 DATA,W 0 V(V)1 FPS B11 FT309 * FT31001124 FTV3201 DATA,W 0 SIN(ETA) INS TWO ANTENNA- FT31101126 FTV3202 DATA,W 0 COS(ETA) XFM BUFFER FT31201130 FTV3203 DATA,W 0 SIN(EPS) FT31301132 FTV3204 DATA,W 0 COS(EPS) FT31401134 FTV3205 DATA,W 0 SIN(PHI+PHIG) FT31501136 FTV3206 DATA,W 0 COS(PHI+PHIG) FT31601140 FTV3207 DATA,W 0 SIN(THETA) FT31701142 FTV3208 DATA,W 0 COS(THETA) FT31801144 FTV3209 DATA,W 0 SIN(PSI) FT31901146 FTV3210 DATA,W 0 COS(PSI) FT320* FT321* SNR VARIABLES - SNV01 THRU SNV07 ARE SNR PARAMETERS SN40001203 SNV01 DATA 0 .sup.. SNR(EARLY RNG/LOW VEL) B6 SN40101204 SNV03 DATA 0 3 .sup.. SNR (RNG) B6 SN40301205 SNV04 DATA 0 4 .sup.. SNR (AZ) B6 SN40401206 SNV05 DATA 0 5 .sup.. SNR (EL) B6 SN40501207 SNV06 DATA 0 6 .sup.. SNR (VEL) B6 SN406* ANY CELL PREFIXED SNV08 ARE SNR SUMS SN40801212 SNV082 DATA,W 0 SUM(2) SN40901214 SNV086 DATA,W 0 SUM(6) SN41001216 SNV084 DATA,W 0 SUM(4) SN41101220 SNV087 DATA,W 0 SUM(7) SN41201222 SNV083 DATA,W 0 SUM(3) SN41301224 SNV085 DATA,W 0 SUM(5) SN41401226 SNV081 DATA,W 0 SUM(1) SN41501230 SNV089 DATA,W 0 SUM(9) = ALTERNATE SUM(1) SN41601232 SNV09 DATA,W 0 HPRF 11 NARROW FLTR HIT/MISS COUNT SN41701234 SNV10 DATA,W 0 RETURN ADDRESS FOR SN ROUTINE SN41802276 FTV1001 DATA,W 0 R(TPR) FT B20 FT10302300 DATA,W 0 R(TPR) LEAST SIGNIFICANT WORD FT103 * FT10402302 FTV1002 DATA,W 0 V(TPR) FPS B13 FT10502304 FTV1003 DATA,W 0 A(TPR) FPS**2 B11 FT106 * FT10702306 FTV1012 DATA,W 0 V(TPV) FPS B13 FT10802310 FTV1013 DATA,W 0 A(TPR) FPS**2 B11 FT109 * FT110 * FT001 ******** TRACKING FILTER CONSTANTS FT002 * FT003 * FT100 ******** INDEPENDENT RNG AND VEL TRACKERS' GAINS FT101 * FT102 * FT10304630 FTK101 EQU $ MPRF SNR1 < SNR(R) < SNR2 (SET 1) FT10404631 DATA FX'0.sup.. 130B1' K1(R) I/T FT10504631 DATA FX'0.sup.. 150B4' K2(R) I/T FT10604632 DATA FX'0.sup.. 000B5' K3(R) I/T FT10704633 DATA FX'-.sup.. 150B2' K2(V) I/T FT10804634 DATA FX'-.sup.. 500B5' K3(V) I/T FT10904635 FTK103 EQU $ MPRF.sup.. SNR3 < SNR(R) (SET3). FT11604635 DATA FX'0.sup.. 050B1' K1(R) I/T FT11704636 DATA FX'0.sup.. 100B4' K2(R) I/T FT11804637 DATA FX'0.sup.. 000B5' K3(R) I/T FT11904640 DATA FX'- 150B2' K2(V) I/T FT12004641 DATA FX'- 800B5' K3(V) I/T FT12104642 FTK104 EQU $ MPRF SNR1 < SNR(R) < SNR5 (SET 4) FT12204642 DATA FX'0.sup.. 150B1' K1(R) F/T FT12304643 DATA FX'0.sup.. 100B4' K2(R) F/T FT12404644 DATA FX'0.sup.. 030B5' K3(R) F/T FT12504645 DATA FX'0.sup.. 700B2' K2(V) F/T FT12604646 DATA FX'2.sup.. 000B5' K3(V) F/T FT12704647 FTK106 EQU $ MPRF.sup.. SNR6 < SNR(R) (SET 6) FT13404647 DATA FX'0.sup.. 060B1' K1(R) F/T FT13504650 DATA FX'0.sup.. 080B4' K2(R) F/T FT13604651 DATA FX'0.sup.. 030B5' K3(R) F/T FT13704652 DATA FX'0.sup.. 400B2' K2(V) F/T FT13804653 DATA FX'1.sup.. 800B5' K3(V) F/T FT13904700 FTK200 GAD ANV4 IAOW FOR FETCHING 6 GIMBAL VAR'S FT20304702 FTK201 GAD FTV3201 POINTER TO INS-ANT XFM BUFFER. FT204* FT205* FT247******** ANGLE TRACKER INITIAL TRACK GAINS FT248* FT24904704 FTK250 DATA FX'0.sup.. 8B1' R(TPA)<R1 GAINS FT25004705 DATA FX'4.sup.. B4' FT25104760 DATA FX'=2000.sup.. B15' FT25204707 DATA FX'0.sup.. 15B1' FT253 * FT25404710 DATA FX'0.sup.. 20B1' B1 < R(TPA).sup.. SNR(D) .SNR(D) > C4 GAINS FT25504711 DATA FX'0.sup.. 67B4' FT25604712 DATA FX'=1000.sup.. B15' FT25704713 DATA FX'0.sup.. 92B1' FT258 * FT25904714 DATA FX'0.sup.. 12B1' R1 < R(TPA).sup.. SNR(D) <C4 FT26004715 DATA FX'0.sup.. 17B4' FT26104716 DATA FX'= 100.sup.. B15' FT262__________________________________________________________________________
PART II
* AT101******** AT A/A TRACK ANTENNA CONTROL ******** AT102******** AT103* AT10442521 AT EQU $ AT10542521 LG,0 3 SAVE RETURN ADDRESS IN RO AT105 1042526 LI,2 6'0124' AI10 INDEX AT10642530 L,4 *UNK3 BUFFERED AZ PSD OUTPUT THETA (D) AT107 * 5OUSEC DELAY AT10842532 STH,4 AI10 TO BUFFER AT10942534 AI,2 2 AI11 INDEX AT11042536 L,4 *UNK3 BUFFERED EL PDS OUTPUT THETA(E) BO AT111 * 50 USEC DELAY AT11242540 STH,4 AI11 TO BUFFER AT113 * START EL DRIVE CALCULATIONS AT14442554 ATL060 LI,1 0 INDEX FOR AT VAR IN EL AT14542556 LI,2 0'0010' 0A004 INDEX AT14642560 LI,3 0 INDEX FOR FT VAR IN EL AT14742562 LH,4 AI11 THETA(E) BO AT148 * COMMON EL/AZ DRIVE CALCULATIONS AT14942564 ATL070 LH,5 ATV02,1 PREVIOUS THETA(E)/(D) BO AT15042566 STH,4 ATV02,1 UPDATE THETA(E)/(D) BO AT15142570 SHG,4 5 DELTA THETA(E)/(D) BO AT152 * PSD SCALING 10/1.sup.. 75*57.sup.. 296) = .sup.. 100 AT152 142571 MHI,4 FX'-0.sup.. 1BO' CONVERT TO RADS, CORRECT AI POLARITY AT15342573 SL,4 2 B-2 AT15442575 A,4 FTV2011,3 +EPS(P)(E)/(D)B-2 AT15542577 ST,4 FTV2011,3 NEW EPS(P)(E)/(D) RADS B-2 AT15642601 AH,4 ATV04,1 + L(E)1 OR L(D)1 RADS B-2 AT15742603 MHI,4 FX'15.sup.. B6' *K(2) B4 AT15842605 L,5 FTV2012,3 OMEGA(LSP)(E)/(D) B1 AT15942607 SRA,5 3 B4 AT16042611 AG,4 5 B4 AT16142612 LHI,6 FX'0.sup.. 69813B0' AT16242614 SRA,6 4 40 DEG/SEC B4 AT16342616 DT,4 R6 BO AT16442620 SLC,7 24 DELAY FOR AO AT164 1042622 STH,4 *UNK3 OUTPUT EL/AZ DRIVE AT16542624 CI,1 1 BOTH EL/AZ CALCULATIONS COMPLETED? AT16642626 BE ATL080 YES AT16742630 STH,4 AO04 TO BUFFER AT168 * START AZ DRIVE CALCULATIONS DURING EL DRIVE AO TIME AT16942632 LI,1 1 INDEX FOR AT VAR IN AZ AT17042634 LI,2 0'0006' AO03 INDEX AT17142636 LI,3 8 INDEX FOR FT VAR IN AZ AT17242640 LH,4 THETA(D) BO AT17342642 8 ATLO70 AT174 * AT17542644 ATL080 STH,4 A003 TO BUFFER AT17642646 LI,1 0'0066' AT17742650 BCT $.sup.. 1 66 USEC DELAY TO COMPLETE AZ AT17842652 I,1 0'1000' AT17942654 CSW,1 2 CLEAR ADA COMPLETE AT18042655 BU *0 RETURN AT181 * FT001 ******** TRACKING FILTER PROGRAM FT002 * FT00346713 FT ST,0 FTV0000 SAVE RET ADDRESS TO XT FT00446715 LH,4 XTF001 `INITIAL TRK` FLAG FT00546717 BEZ FTL1010 BR IF F/T FT00646721 STHI,0 FTV0020 I/T. SET C(INS)=0 FT00746723 BU FTL1050 FT008 * FT00946725 FTL1010 LR,1 FTV0020 F/T.sup.. C(INS) TO R1(R) FT01046727 BNEZ FTL1020 BR IF NOT 1ST TIME F/T FT01146731 L,4 INDA 1ST TIME F/T. SAVE 1ST VEL SET FT01246733 L,5 IND5 FT01346735 L,6 IND6 FT01446737 STD,4 FTV3111 V(N),V(E) TO V(N)1,V(E)1FPSB12 FT01546741 ST,6 FTV3113 V(V) TO V(V)1 FPS B11 FT01646743 STI,0 FTV0012 T(INS)=0 FT01746745 STHI,1 FTV0020 C(INS)=1 FT01846747 LI,1 18 FT018 1046751 FTL1015 STI,0 FTV2211,1 CLEAR ALL M(A)'S FT018 1546753 BCT FTL1015,1 FT018 2046755 LHI,1 FX'0.sup.. 0001B-9' INITIALIZE DIAGONAL FT018 2546757 ST,1 FTV2211 M(A)11 FT018 3046761 LHI,2 FX'0.sup.. 0004B-8' FT018 3546763 ST,2 FTV2222 M(A)22 FT018 4046765 LHI,3 FX'4000.sup.. B13' FT018 4546767 ST,3 FTV2233 M(A)33 FT018 5046771 L,4 FTV2700 FT018 5546773 SRA,4 1 1/2*SIGMA(S)**2 B-9 FT018 6046775 ST,4 FTV2244 M(A)44 FT018 6546777 LH,4 FTV2632 FT018 7047001 STH,4 FTV2631 SET ETA(1)=ETA(2) FT018 7547003 BU FTL1040 FT019 * FT02047005 FTL1020 LH,4 FTV0010 F/T,NOT 1ST TIME .sup.. T TO R4 B-3 FT01247007 SRA,4 4 T(PREVIOUS FILTER PER) TO B1 FT02247011 ATM,4 FTV0012 T(INS)=T(INS)+T SECS B1 FT02347013 AI,1 1 C(INS)=C(INS)+T FT02447015 STR,1 FTV0020 SAVE FT02547017 CI,1 3 FT02647021 BNE FTL1030 BR IF C(INS) N.sup.. E.sup.. 3 FT02747023 L,4 IND3 C(INS)=3.sup.. SAVE INS-ANT XFM TERMS. FT02847025 BAL SC,3 FT02947027 ST,4 FTV3209 SIN(PSI) FT03047031 ST,6 FTV3210 COS(PSI) FT03147033 LM,0,0 *FTK200 PICK UP ANV* THRU ANV11 FT03247035 LD,4 ANV12 S,C(PHI+PHIG) TO R4,R5 FT03347037 STM,0,0 *FTK201 SAVE IN XFM BUFFER FT03447041 BU FTL1040 FT035 * FT03647043 FTL1030 CI,1 5 C(INS)N.sup.. E.sup.. 3.sup.. COMPARE TO FT03747045 BL FTL1040 BR IF C(INS) L.sup.. T.sup.. 5 FT03847047 STHI,1 FTV0020 C(INS)=5.sup.. SET C(INS)=1 FT03947051 BAL FTS8,0 COMPUTE 0.sup.. S.sup.. ACCEL IN ANY FT040S * FT04147053 FTL1040 LH,4 FTV0010 FT04247055 LH,6 FTV2632 ETA(2) FT042 1047057 LHG,5 6 SAVE IN R5 FT042 2047060 SH,6 FTV2631 ETA(2)=ETA(1) FT042 3047062 MHI,6 FX'1.sup.. 13446B1' TO RADS AT B1 FT042 4047064 SL,6 1 to B0 FT042 5047066 DT,6 R4 DELTA(ETA)/T(OLD) RADS/SEC B3 FT042 6047070 ST,6 FTV2633 ETA(DOT) RADS/SEC B3 FT042 7047072 STH,5 FTV2631 SET ETA(1)=ETA(2) FT042 8047074 AH,4 FTV0011 FT04347076 SRL,4 1 FT04447100 STH,4 FTV0010 T=1/2*(T(OLD)+T(NEW) SECSB-3 FT045 * FT046 * FT049**** R(TPA),V(TPA),SNR(D) SELECTION FT050 * FT05147112 L,1 FTV1001 R(TPR) TO R1 FT05547114 L,2 FTV1012 V(TPV) TO R2 FT05647116 LH,3 SNV03 SNR(RNG) TO R3 FT05747130 LH,4 XTF001 MPRF, `INITIAL TRK`FLAG FT06147132 BEZ FTL1120 BR IF F/T FT06247134 FTL1070 L,2 FTV1002 MPRF I/T, V(TPR) TO R2 FT06347136 BU FTL1120 FT064 * FT08247202 FTL1120 CHI,1 8 RTPA GE 4096 FT AT B20 ? FT08347204 BGE FTL1125 DONT LIMIT RTPA IF GE FT083 1047206 LHI,1 8 LIMIT RTPA TO 4096 FT AT B20 FT083 2047210 FTL1125 STD,1 FTV0001 SAVE RTPA AND VTPA FT083 3047212 STH,3 FTV0030 R3 TO SNR(D) FT084 * FT085 *** CONTROLLER PARAMETERS FT086 * FT08747216 FTL1130 LH,4 XTF001 `INITIAL TRK` FLAG FT08847220 BNEZ FTL1140 BR IF I/T FT08947222 LHI,1 FX'0.sup.. 3B2' F/T.sup.. B2 TO R1 FT09047224 LHI,2 FX'-.sup.. 3B2' C2 to R2 FT09147226 BU FTL1150 FT09247230 FTL1140 LHI,1 FX'0.sup.. 3B2' I/T .sup.. B1 TO R1 FT09347232 LHI,2 FX'-.sup.. 3B2' C1 to R2 FT09447234 FTL1150 LH,4 ATV04 L(E) RADS B-2 FT09547236 MHG,4 1 B*L(E) B0 FT09647237 LH,6 FTV2011 EPS(E) RADS B-2 FT09747241 MHG,6 2 C*EPS(E) BO FT09847242 AG,4 6 B*L(E)+C*EPS(E) BO FT09947243 SL,4 2 to B-2 FT10047245 STH,4 ATV04 NEW L(E) RADS B-2 FT10147247 LH,4 ATV05 L(D) RADS B-2 FT10247251 MHG,4 1 B*L(D) BO FT10347252 LH,6 FTV2021 EPS(D) RADS B-2 FT10447254 MHG,6 2 C*EPS(D) BO FT10547255 AG,4 6 B*L(D)+C*EPS(D) BO FT10647256 SL,4 2 TO B-2 FT10747260 STH,4 ATV05 NEW L(D) RADS B-2 FT108 * FT109 *** SCINTILLATION PARAMETERS FT110 * FT11147262 BAL FTS1,0 COMPUTE SIGMA(S)**2 AND TAU(S) FT117 * FT12147264 FTL1190 BAL FTS2,0 COMPUTE STATE TRANS MATRIX PHI(A) FT122 * FT12347266 FTL1200 BAL FTS3,0 COMPUTE MOTION COMPENSATION FT124 * FT12547270 FTL1210 LH,4 XTF008 `DATA VALID` FLAG FT12647272 BEZ FTL1230 BR IF DISCR DATA NOT VALID FT12747274 LH,4 FTV0030 SNR(D) FT12847276 CH,4 FTV0031 SNR(D): EXTRAP THRES FT12947300 BL FTL1230 BR IF SNR(D) L.sup.. T.sup.. THRSH FT13047302 STHI,0 FTF201 RESET `ANGLE XTRAP` FT13147304 LH,4 XTF001 `INITIAL TRK`FLAG FT13247306 BNEZ FTL1220 BR IF I/T.sup.. SKIP RADOME COMP FT13347310 BAL FTS4,0 CALL RADOME COMP FT13447312 FTL1220 BAL FTS5,0 COMPUTE DISCR SLOPES AND RESIDUALS FT13547314 BU FTL1240 FT136 * FT13747316 FTL1230 STHI,-1 FTF201 SET `ANGLE XTRAP` FT13847320 STI,0 FTV2704 SET KE=0, KD=0 FT13947322 STI,0 FTV2706 SET RESIDUAL(EL)=0 FT14047324 STI,0 FTV2707 SET RESIDUAL(AZ)=0 FT141 * FT142 *** GAINS,CO-VARIANCE UPDATE ETC. FT143 * FT14447326 FTL1240 LH,4 XTF001 `INITIAL TRK` FLAG FT14547330 BNEZ FTL1290 BR IF I/T TO I/T GAIN SELECT FT14647332 LH,4 FTF202 `M(A) LARGE` FLAG FT14747334 BEZ FTL1250 BR IF M(A) NOT LARGE FT14847336 LH,4 FTF201 `ANGLE XTRAP` FLAG FT14947340 BNEZ FTL1340 BR IF ANGLE XTRAP (FREEZE M(A) FT15047342 STHI,0 FTF202 RESET `M(A) LARGE` FLAG FT15147344 FTL1250 BAL FTS6,0 KALMAN GAIN AND CO-VARIANCE UPDATE FT15247346 L,6 FTV2222 NEW M(A)22 FT152 1047350 L,4 FTV2211 NEW M(A)11 FT15347352 CHI,4 FX'0.sup.. 0015B-9' FT15447354 BG FTL1260 BR IF M(A)11 > C11 FT15547356 CHI,6 FX'0.sup.. 003B-8' FT15747360 BLE FTL1340 BR IF M(A)22 > C22 FT158 * FT16047362 FTL1260 STHI-1 FTF202 M(A)11 OR M(A)22 TOO LARGE .sup.. SET FLAG FT16147364 LHI,1 FX'0.sup.. 980' C13 TO R1 FT16247366 MG,4 1 FT16347367 ST,4 FTV2211 M(A)11=C13(M(A)11 FT16447371 MG,6 1 FT16547372 ST,6 FTV2222 M(A)22=C13(M(A)22 FT16647374 M,1 FTV2212 FT16747376 ST,1 FTV2212 M(A)13=C13(M(A)12 FT16847400 BU FTL1340 FT169 * FT17047402 FTL1290 L,4 FTV0001 R(TPA) TO R4 FT17547404 CHI,4 FX'20000.sup.. B20' FT17647406 BGE FTL1300 BR IF R(TPA) G.sup.. E.sup.. RNG1 FT17747410 LI,1 3 R(TPA) < RNG1 .sup.. SET INDEX IN R1 FT17847412 BU FTL1320 FT17947414 FTL1300 LH,4 FTV0030 SNR(D) B6 FT18047416 CHI,4 FX'4.sup.. B6' FT180 1047420 BL FTL1310 BR IF SNR(D) < C4 FT18147422 LI,1 7 R(TPA) > R1,SNR(D) > C4 FT18247424 BU FTL1320 FT18347426 FTL1310 LI,1 11 R(TPA) > R1,SNR(D) < C4 FT184 * FT184 1047430 FTL1320 LI,2 6 4 ITERATIONS FT18547432 FTL1330 LH,4 FTK250,1 PICK UP SELECTED GAIN SET FT18647434 ST,4 FTV2501,2 TO ANGLE GAIN VARIABLES FT18747436 AI,1 -1 FT18847440 BCT FTL1330,2 FT18947442 FTL1340 BAL FTS7,0 UPDATE ANGLE STATE VECTORS FT191 * FT401******** RANGE AND RANGE RATE TRACKING FILTER PROGRAM FT402 * FT40347450 FTL2000 LH,1 XTF008 `DATA VALID` FT41147452 BE FTL2540 BRANCH IF DATA NOT VALID FT41247454 LH,4 SNV03 SNR(R) B6 FT413 *** MPRF FT415 1047462 CHI,4 FX'1 0B6'.sup.. SNR(R) : EXTRAP THRES FT41647464 BL FTL2500 BRANCH IF SNR(R) < SNR1 FT41747466 FTL2210 LH,0 XTF001 `INITIAL TRACK` FLAG FT41847470 BEZ FTL2250 BRANCH IF GINAL TRACK FT41947472 FTL2220 CHI,4 FX'5.sup.. 0B6' SNR2=5.sup.. 0 AT B6 FT42047474 BL FTL2240 BRANCH IF SNR(R) < SNR2 FT42147476 LI,1 FTK103 LOAD R1 TO PICK UP SET 3 CONSTANTS FT42447500 LHI,2 FX'1.sup.. 0B1' K(RDOT)(F) FT424 1047502 BU FTL2600 FT42547504 FTL2240 LI,1 FTK101 LOAD R1 TO PICK UP SET 1 CONSTANTS FT42847506 LHI,2 FX'1.sup.. 0B1' K(RDOT)(F) FT428 1047510 BU FTL2600 FT429 * MPRF F/T FT429 1047512 FTL2250 CHI,4 FX'5.sup.. 0B6' SNR5 = 5.sup.. 0 AT B6 FT43047514 BL FTL2270 BRANCH IF SNR(R) < SNR5 FT43147516 LI,1 FTK106 LOAD R1 TO PICK UP SET 6 CONSTANTS FT43447520 LHI,2 FX'0.sup.. 85B1' K(RDOT)(F) FT434 1047522 BU FTL2600 FT43547524 FTL2270 LI,1 FTK104 LOAD R1 TO PICK UP SET 4 CONSTANTS FT43847526 LHI,2 FX'0.sup.. 35B1' K(RDOT)(F) FT438 1047530 BU FTL2600 FT439 * FT490 10 *** TOO LOW SNR(R) = MPRF FT490 20 * FT490 3047646 FTL2500 LH,0 XTF001 `INITIAL TRACK` FLAG FT49147650 BNEZ FTL2540 BRANCH IF INITIAL TRACK FT49247652 FTL2520 LD,1 FTV1012 V(TPV) FPS B13 / A(TPV) FPS**2 B11 FT49347654 STD,1 FTV1002 V(TPR)) FPS B13 / A(TPR FPS**2 B11 FT494 * FT494 10 *** DATA NOT VALID OR TOO LOW SNR FT494 20 * FT494 3047656 FTL2540 LHI,7 FX'0 1BO' 1/TA = .1SEC AT BO FT49547660 FTL2560 SG,5 5 DELTA R(M) = 0 FT49647661 SG,6 6 DELTA V(M) = 0 FT49747662 BU FTL2690 FT498 * FT498 10 *** PICK UP SELECTED GAIN SET AND SAVE FT498 20 * FT498 3047664 FTL2600 SHG,1 1 CLEAR THE LEFT HALF OF R1 FT49947665 LR,5 1,1 K2(R) B4 TO RIGHT HALF OF R5 FT50047667 AH,5 0,1 K1(R) B1 TO LEFT HALF OF R5 FT50147671 ST,5 FTV1501 STORE K1(R) B1 and K2(R) B5 FT50247673 LH,6 2,1 K3(R) B5 TO LEFT HALF OF R6 FT50347675 STH,6 FTV1503 STORE K3(R) B5 FT50447677 LR,7 4,1 K3(V) B5 TO RIGHT HALF OF R7 FT50547701 AH,7 3,1 K2(V) B2 TO LEFT HALF OF R7 FT50647703 ST,7 FTV1512 STORE K2(V) B2 and K3(V) B5 FT50747705 FTL2610 LHI,7 FX'0.sup.. 33333BO' 1/TA=.33333 SEC AT FT50847713 LH,4 DSV03 DELTA R AT BO FT52447715 K,4 CHANGE SIGN OF DELTA R FT524 1047716 MT,4 XTV044 *RBIN(BUFFERED) IN FT AT B11' FT52547720 LG,5 4 R5 = DELTA R(M) FT B11 FT52647721 L,6 XTV045 FW=PRF/16(BUFFERED) HZ B10 FT52747727 FTL2680 MH,6 DSV02 *DELTA V(DSCR) AT BO FT53047731 MT,6 RFV003 *(LAMBDA/2) AT B-4 FT53147733 L,4 FTV1012 FT531 1047735 S,4 FTV01021 V(TPV)-V(GC)(OLD) B13 FT531 2047737 MG,2 4 K(RDOT)(F)*(V(TPV)-V(GC)(OLD)) B14 FT531 3047740 SLD,2 8 to B6 FT531 4047742 SG,6 2 FT531 50 * R6 IS DELT V(M) FPS B6 FT53247743 FTL2690 STD,5 FTV2401 TEMP1 IS DELTA R(M) AT B11 FT533* FTV2402 TEMP2 IS DELTA V(M) AT B6 FT534* FT535* SET UP R2 AND R5 FT53647745 FTL2700 LH,5 FTV0010 *R4 = T SEC B-3 FT53747747 LG,2 5 R2 =T SEC B-3 FT53847750 MG,2 5 R2 = (1/2)(T**2) SEC**2 B-7 FT54047751 LHI,3 FX'0.sup.. 0B-4' R3 = W(F)**2 (RAD/SEC)**2 B-4 FT54147753 MGH,3 5 *R3 = (W(F)**2)*T 1/SEC B-7 FT54247754 MHG,7 5 R7 = T(1/TA) B-3 FT54347755 SRA,7 3 BO FT543 1047757 LG,4 7 FT54447760 MT,4 R7 (T/TA)**2 BO FT544 1047762 SRA,4 1 FT544 2047764 SG,4 7 FT544 3047765 A,4 UNK1 R4 = 1-(T/TA)+1/2(T/TA)**2 BO FT54547767 FTL2710 LH,0 XTF005 `RANGE AVAILABLE` FLAG FT545 1047771 BEZ FTL2750 BRANCH IF RANGE IS NOT AVAILABLE FT545 2047777 FTL2720 LH,6 FTV1501 R6 = K1(R) ND B1 FT54850001 M,6 FTV2401 R67=K1(R)*DELTA R(M) FT B12 FT54950003 L,0 FTV1003 RO = A(TPR) FPS**2 B11 FT55050005 S,0 FTV3001 RO = A(TPR)-AI(R) FPS**2 B11 FT55150007 MG,0 2 R)=R2*(A(TPR)=AI(R) FT B4 FT55250010 SRDA,0 8 RO=R2*(A(TPR)-AI(R)) FT B12 FT55350012 AD,6 0 R67=R6+RO = SUM FT B12 FT55450014 L,0 FTV1002 RO=V(TPR) FPS B13 FT55550016 MG,0 5 RO=T*V(TPR) FT B10 FT55650017 SRDA,0 2 RO=T*V(TPR) FT B12 FT55750021 AD,6 0 R67=R6 + R0 = SUM FT B12 FT55850023 SRDA,6 8 R67=SUM FT B20 FT55950025 AD,6 FTV1001 R67=R(TPR) + SUM FT B20 FT56050027 STD,6 FTV1001 R(TPR) FT B20 FT561 * FT56250031 LH,6 FTV1502 R6=K2(R) FPS/FT B4 FT56350033 M,6 FTV2401 R67=K2(R) *DELTA R(M) FPS B15 FT56450035 SLD,6 2 R67=K2(R)*DELTA R(M) FPS B13 FT56550037 L,0 FTV1003 R0 = A(TPR) FPS**2 B11 FT56750041 S,0 FTV3001 RO = A(TPR)-AI(R) FPS**2 B11 FT56850043 MG,0 5 R01=T*(A(TPR)-AI(R)) FPS B8 FT56950044 SR8,0 5 RO = T*(A(TPR)-AI(R)) FPS B13 FT57050046 AG,6 0 R6 = RO + R6 = SUM FPS B13 FT57150047 L,0 FTV1001 RO = R(TPR) FT B20 FT57250051 MG,0 3 R01 = R(TPR)*(W(F)**2)*T FPS B13 FT57350052 AG,6 0 R6 = RO+R6 = SUM FPS B13 FT57450053 ATM,6 FTV1002 V(TPR) = V(TPR)OLD + SUM FPS B13 FT575 * FT57750055 LH,6 FTV1503 R6 = K3(R) FPS**2/FT B5 FT57850057 M,6 FTV2401 R67 = K3(R)*DELTA R(M) FPS**2 B16 FT57950061 SLD,6 5 R67=K3(R)*DELTA R(M) FPS**2 B11 FT58050063 L,0 FTV1003 RO = A(TPR) FPS**2 B11 FT58150065 MG,0 4 RO = (1-T(1/TA))*A(TPR) FPS**2 B11 FT58250066 AG,6 0 R6 = A(TPR)(NEW) FTS**2 B11 FT58350067 ST,6 FTV1003 A(TPR) FPS**2 B11 FT584 * FT58550071 S,6 FTV3001 R6 = A(TPR)-AI(R) FPS**2 B11 FT58650073 LH,0 FTV0011 R0 = T(NEW) SEC B-3 FT58750075 MG,6 0(1/2)T(NEW)*(A(TPR)-AI(R)) FPS B7 FT58850076 SRA,6 6 FPS B13 FT58950100 A,6 FTV1002 R6 = R6 + V(TPR) FPS B13 FT59050102 MG,6 0 *T(NEW) FT B10 FT59150103 SRA,6 10 R6 = SUM T B20 FT59250105 A,6 FTV1001 R6 = R(TPR) + SUM FT B20 FT59350107 ST,6 FTV0101 R(GC)(TI+1) FR B20 FT594 * FT59550115 FTL2760 LH,0 XTF006 `VELOCITY AVAILABLE` FLAG FT597 1050117 BEZ FTL2900 RANCH IF VELOCITY IS NOT AVAILABLE FT597 2050121 FTL2770 LH,6 FTV1512 R6 = K2(V) ND B2 FT59850123 M,6 FTV2402 R67=K2(V)*DELTA V(M) FPS B8 FT59950125 SRA,6 5 R6 = K2(V)*DELTA V(M) FPS B13 FT60050127 L,0 FTV1001 RO = R(TPR) FT B20 FT60150131 MG,0 3 RO = R(TPR)*(W(F)**2)*T FPS B13 FT60250132 AG,6 0 R6 = SUM FPS B13 FT60350133 L,0 FTV1013 RO = A(TPV) FPS**2 B11 FT60450135 S,0 FTV3001 R0 = A(TPV) -AI(R) FPS**2 B11 FT60550137 MG,0 5 RO = T*(A(TPV)-AI(R)) FPS B8 FT60850140 SRA,0 5 RO = T*(A(TPV)-AI(R)) FPS B13 FT60950142 AG,6 0 R6 = SUM FPS B13 FT61050143 ATM,3 FTV1012 V(TPV)=V(TPV)+SUM FPS B13 FT611 * FT61350145 LH,0 FTV1513 R) = K3(V) FPS**2/FPS B5 FT61450147 MT,0 FTV2402 RO = K3(V)*DELTA V(M) FPS**2 B11 FT61550151 MT,4 FTV1013 R4 = (1-T/TA)*A(TPV) FPS**2 B11 FT61650153 AG,0 4 RO = RO + R4 FPS**2 B11 FT61750154 ST,0 FTV1013 A(TPV) FPS**2 B11 FT618 * FT61950156 L,2 FTV0102 SAVE V(GC) IN FT619 1050160 ST,2 STV01021 V(GC)(OLD) FT619 2050162 MT,3 FTV1001 R3 = R(TPR)*T(W(F)**2) FPS B13 FT62050164 S,0 FTV3001 RO = A(TPV)-AI(R) FPS**2 B11 FT62150166 LH,2 FTV0011 R2 = T(NEW) SEC B-3 FT621 1050170 MG,0 2 R0 = T(NEW)*(A(TPV)-AI(R)) FPS B8 FT62250171 SRA,0 5 R0 = T(NEW)*(A(TPV)-AI(R)) FPS B13 FT62350173 AG,0 3 R0 = R0 + R3 = SUM FPS B13 FT62450174 A,0 FTV1012 RO=V(TPV) + SUM FPS B13 FT62550176 ST,0 FTV0102 V(GC) FPS B13 FT62650200 BU FTL2900 FT627 * FT65950277 FTL2900 LH,4 FTV0011 FT66050301 STH,4 FTV0010 SET T=R(NEW) FT66150303 LI,4 0'3777' R4 = 256 FT B20 FT66250305 C,4 FTV1001 COMPARE WITH R(TPR) FT66350307 BL FTL2910 BRANCH IF R(TPR) > 256 FT FT66450311 ST,4 FTV1001 R(TPR) = R4 FT66550313 FTL2910 BU *FTV0000 RETURN FT666* FTS01******** TRACKING FILTER SUB-ROUTINES FTS02* FTS03* FTS101******** FTSR01-COMPUTE SIGMA(S)**2 and TAU(S) FTS102******** RETURN ADDRESS IN RO FTS103* FTS10450315 FTS1 L,6 FTV0001 R(TPA) TO R6.sup.. B20 FTS10550317 MG,6 6 R**2 B40 FTS10650320 LI,4 FX'130.sup.. B9' ALPHA2 to R4.sup.. F.sup.. W.sup.. SCALE= 12 + 9 = 21 FTS10750322 SG,5 5 CLEAR R5 FTS10850323 SRDA,4 10 ALPHA2 TO B31 FTS10950325 DG,4 6 ALPHA 2/R**2 AT B(31-40)=B-9 FTS11050326 ST,4 FTV2700 SIGMA(S)**2 B-9 FTS111 * ENTER HERE FOR TAU(S) ONLY. FTS11250330 FTS1L10 L,4 FTV0002 V(TPA) TO R4.sup.. B13 FTS11350332 SRA,4 1 TO B14 FTS11450334 ABS,4 FTS11550335 BAL SO,3 SQ RT (.vertline.V.vertline.) TO R6.sup.. B7 FTS11650337 SRA,6 5 TO B12 FTS11750341 LHI,4 FX'0.sup.. 00346B=7' ALPHA 3 TO R4 FTS11850343 M,4 FTV0001 ALPHA3*R(TRP) B13 FTS11950345 DG,4 6 ALPHA3*R/(RT(.vertline.V.vertline.)) FTS12050346 LHI,6 FX'0.sup.. 8B1' ALPHA1 TO R6 FTS12150350 CG,4 6 R4:ALPHA1 FTS12250351 BL FTS1L20 BR IF R4 L.T. ALPHA1 FTS12350353 ST,6 FTV2701 TAU(S)=ALPHA1 B1 FTS12450355 BU *0 EXIT FTS12550357 FTS1L20 ST,4 FTV2701 TAU(S)=ALPHA3*R/(RT(.vertline.V.vertline.)) FTS12650361 BU *0 EXIT FTS127* FTS201******** FTSR02-COMPUTE PHI(A) MATRIX FTS202******** RETURN ADDRESS IN RO FTS203* FTS20450363 FTS2 LHI,1 FX'1.sup.. 0B1' 1 AT B1 TO R1 FTS20550365 LHI,2 FX'0.sup.. 3333B0' ALPHA(T) TO R2 B0 FTS20650367 LH,3 FTV0010 T (FILTER PER) TO R3.SECS B-3 FTS207 * FTS20850371 LG,6 3 FTS20950372 MHG,6 2 X=ALPHA(T)*T IN R6.sup.. B-3 FTS21050373 SRA,6 4 TO B1 FTS21150375 LG,4 6 FTS21250376 MG,4 6 X**2 AT B2=(X**2)/2 AT B1 FTS21350377 SG,4 6 FTS21450400 AG,4 1 FTS21550401 ST,4 FTV2133 PHI(A)33-10X+(X**2)/2 B1 FTS216 * FTS21750403 LG,6 3 T TO R6 B-3 FTS21850404 SRA,6 5 TO B2 FTS21950406 DT,6 FTV2701 Y=T/TAU(S) IN R6. B1 FTS22050410 LG,4 6 FTS22150411 MG,4 6 Y**2 AT B2=(Y**2)/2 AT B1 FTS22250412 SG,4 6 FTS22350413 AG,4 1 FTS22450414 ST,4 FTV2144 PHI(A)44=1-Y+(Y**2)/2 B1 FTS225 * FTS22650416 LG,6 3 T TO R6 B-3 FTS22750417 M,6 FTV0002 T*V(TPA) B10 FTS22850421 SRDA,6 8 TO B18 FTS22950423 D,6 FTV0001 Z=T*V(TAP)/R(TPA) IN R6. B-2 FTS23050425 SRA,6 3 TO B1 FTS2301050427 SG,1 6 1-Z IN R1. B1 FTS23150430 LG,4 3 T TO R4 FTS23250431 MG,4 1 FTS23350432 ST,4 FTV2112 PHI(A)12=T*(1-Z) B-2 FTS234 * FTS23550434 MG,6 1 X*(1-Z) IN R6. B2 FTS23650435 SL,6 2 2Z*(1-Z) AT B1 FTS23750437 T,6 FTS23850440 AHI,6 FX'1.sup.. 0B1' FTS23950442 ST,6 FTV2122 PHI(A)22=1-2Z*(1-Z) B1 FTS240 * FTS24150444 LG,6 3 T TO R6 B-3 FTS24250445 T,6 FTS24350446 MG,6 3 -T**2 B-6 FTS24450447 SRDA,6 10 (-T**2)/2 AT B3 FTS24550451 D,6 FTV0001 /R(TAP) AT B20 FTS246 * FTS24850455 SRDA,4 10 PHI(A)12 TO B8 FTS24950457 D,4 FTV0001 PHI(A)12/R(TAP) B-12 FTS25050461 T,4 FTS25150462 SRA,2 5 ALPHA(T) TO B5 FTS25250464 MG,6 2 ALPHA(T)*PHI(A)13 B-12 FTS25350465 SG,4 6 FTS25450466 ST,4 FTV2123 PHI(A)23=-PHI12/R-ALPHA(T) *PHI13 FTS25550470 BU *0 EXIT FTS256* FTS301******** FTSR03-COMPUTE MOTION COMPENSATION L(E) AND L(D) FTS302******** RETURN ADDRESS IN RO FTS303 * FTS30450472 FTS3 LH,1 AI05 EL RATE AI TO R1 FTS30550474 MHI,1 FX'0.sup.. 69813B0' WA(E) RADS/SEC B0 FTS30650476 LH,2 AI04 AZ RATE AI TO R2 FTS30750500 MHI,2 Fx'0.sup.. 69813B0' WA(D) RADS/SEC B0 FTS30850502 LH,3 FTV0010 T(FILTER PER) TO $3. SECS B-3 FTS30950504 LG,4 3 FTS31050505 T,4 FTS31150506 SRA,4 1 -T SECS B-2 FTS31250510 LG,6 4 FTS31350511 MG,4 1 FTS31450512 ST,4 FTV2611 L(E)1=-T*WA(E) RADS B-2 FTS31550514 MG,6 2 FTS31650515 ST,6 FTV2621 L(D)1=-T*WA(D) RADS B-2 FTS31750517 LH,4 XTF001 `INITIAL TRK` FLAG FTS31850521 BEZ FTS3L10 BR IF FINAL TRK FTS31950523 BU *0 INITIAL TRK. EXIT FTS320* FINAL TRK. COMPUTE WA(R) AND REST OF L TERMS FTS32150525 FTS3L1o ST,0 FTV2400 SAVE RET ADDRESS FTS32250527 LH,0 AI12 ROLL RATE AI TO RO FTS32350531 MHI,0 FX'8.sup.. 31109B4' WOG RADS/SEC B4 FTS32450533 SRA,1 2 WA(E) TO B2 FTS32550535 SRA,2 3 WA(D) TO B3 FTS326 * FTS32750537 L,4 FTV2633 ETA(DOT) RADS/SEC B3 FTS32850541 SG,4 2 ETA(D)T-WA(D) B3 FTS33650542 M,4 ANV6 (ETA(D)T)-WA(D))*SIN(EPS) B4 FTS33750544 AG,4 0 + WOG FTS33850545 L,6 ANV7 COS(EPS) TO R6 FTS33950547 M,1 ANV4 FTS34050551 MG,1 6 WA(E)*SIN(ETA)*COS(EPS) B4 FTS34150552 AG,4 1 N In R4 RADS/SEC R4 FTS34250553 M,6 ANV5 5 D=COS(EPS)*COS(ETA) IN R6 B2 FTS34350555 SL,6 1 TO B1 FTS34450557 DT,4 R6 WA(R) RADS/SEC B3 FTS34550561 LG,0 4 WA(R) TO R0 FTS34750562 MG,4 3 T*WA(R) RADS B0 FTS34850563 LG,6 4 FTS34950564 ST,4 DPUV37 *** THETA(R) TO DPU RADS B0 FTS349250566 M,4 FTV2021 (T*WA(R))*EPS(D) RADS B-2 FTS35050570 ATM,4 FTV2611 L(E)1+R4 TO L(E)1 FTS35150572 M,6 FTV2011 FTS35250574 T,6 -(T*WA(R))*EPS(E) RADS B-2 FTS35350575 ATM,6 FTV2621 L(D)1+R6 TO L(D)1 FTS354 * FTS35550577 MG,3 3 FTS35650600 SRA,3 1 (T*8AT)/2 B-6 FTS35750602 L,4 FTV3003 AI(D) FPS**2 B11 FTS35850604 SG,5 5 FTS35950605 SRDA,4 13 TO B24 FTS36050607 D,4 FTV0001 AI(D)/R(TPA) B4 FTS36150611 LG,6 0 FTS36250612 M,6 FTV2022 WA(R)*WLS(D) B4 FTS36350614 AG,4 6 FTS36450615 LG,6 4 AI(D)/R+WA(R)*WLS(D) IN R4 AND R6 FTS36550616 MG,4 3 ((T**2)/2)*R4 B(-6+4)=B-2 FTS36650617 ATM,4 FTV2611 L(E)1 COMPLETE RADS B-2 FTS36750621 M,6 FTV2112 PHI(A)12*R6 B(-2+4)=B2 FTS36850623 SL,6 1 TO B1 FTS36950625 ST,6 FTV2612 L(E)2 RADS/SEC B1 FTS370 * FTS37150627 L,4 FTV3002 AI(E) FPS**2 B11 FTS37250631 SG,5 5 FTS37350632 SRDA,4 13 TO B24 FTS37450634 D,4 FTV0001 AI(E)/R(TPA) B4 FTS37550636 LG,6 0 FTS37650637 M,6 FTV2012 WA(R)*WLS(E) B4 FTS37750641 AG,4 6 FTS37850642 LG,6 4 AI(E)/R+WA(R)*WLS(E) IN R4 AND R6 FTS37950643 MG,4 3 FTS38050644 T,4 -((T**2)/2)8*4 B(-6+4)=B-2 FTS38150645 ATM,4 FTV2621 L(D)1 COMPLETE RADS B-2 FTS38250647 M,6 FTV2112 FTS38350651 T,6 -PHI(A)12*R6 B(-2+4)-B2 FTS38450652 SL,6 1 TO B1 FTS38550654 ST,6 FTV2622 L(D)2 RADS/SEC B1 FTS38650656 BU *FTV2400 EXIT FTS387 * FTS401******** FTSR04-COMPUTE RADOME COMPENSATION FTS402******** RETURN ADDRESS IN R0 FTS403 * FTS40450660 FTS4 ST,0 FTV2400 SAVE RET ADDRESS TEMP 0 FTS40550662 LM,2,6 *FTK200 LOAD GIMBAL VAR'S ALL B+1 FTS40650664 MG,7 4 COS(PHIG)*SIN(EPS) TO R7 B+2 FTS40750665 SL,7 2 TO B0 FTS40850667 MG,7 3 *COS(ETA), PROD B-1 FTS40950670 MG,3 5 COS(EPS)*COS(ETA) TO R3 B+2 FTS41050671 SL,3 1 TO B1 FTS41150673 MI,2 R6 SIN(PHIG)*SIN(ETA) B+2 FTS41250675 SL,2 1 TO B1 FTS41350677 SG,2 7 -COS(PHIG)*SIN(EPS)*COS(ETA) B1 FTS41450700 MHI,2 FX'0.sup.. 10192B-3' *SIN(SIG') B-3' PROD B-2 FTS41650702 SRA,2 3 TO B+1 FTS41750704 MHI,3 FX'0.sup.. 994798+0' COS(SIG')*COS(EPS) *CPS(ETA) B+1 FTS41850706 AG,2 3 COS(DELTA) B+1 FTS41950707 LG,4 2 FTS42050710 MG,4 2 COS(DELTA)**2 B+2 FTS42150711 T,4 =COS**2 FTS42250712 AHI,4 FX'1.sup.. 0B+2' 1-COS(DELTA**2 B-2 FTS42350714 BAL SQ,3 G) CALC SIN(DELTA) IN R6 B-1 FTS42450716 ST,6 FTV2401 SIN(DELTA) TO TEMP 1 B+1 FTS425 * FTS42650720 LM,7,6 (FTK200 LOAD GIMBAL SINES,COSINES B1 FTS42750722 LHI,5 FX'0.sup.. 10192B-3' SIN(SIG') B-3 FTS42850724 LHI,6 FX'0.sup.. 9947980' COS(SIG') B0 FTS42950726 SRA,6 3 SIN(SIG') B0 FTS43050730 MT,0 R3 FTS43150732 MT,0 R5 S(SIG')*S(PHIG)*C(ETA) B2 FTS43250734 MT,7 R2 FTS43350736 MT,7 R6 C(SIG')*C(EPS)*S(ETA) B2 FTS43450740 SG,0 7 FTS43550741 DT,0 FTV2401 SIN(LAMBDA) IN R0 B1 FTS43650743 MG,2 4 FTS43750744 MG,2 5 S(SIG')*C(PHIG)*C(EPS) B2 FTS43850745 MG,6 1 C(SIG')*S(EPS) B1 FTS43950746 SRA,6 1 B2 FTS44050750 AG,2 6 FTS44150751 DT,2 FTV2401 COS(LAMBDA) IN R2 B1 FTS442 * FTS44350753 L,4 FTV2401 SIN(DELTA) B1 FTS44450755 LG,6 4 FTS44550756 CHI,4 FX'0.sup.. 174B1' SIN(DELTA) : 0.sup.. 174 FTS44650760 BLE FTS4L10 BR IF L.sup.. E.sup.. FTS44750762 CHI,4 FX'0.sup.. 422B1' SIN(DELTA) : 0.sup.. 422 FTS44850753 BLE FTS4L20 BR IF L.sup.. E.sup.. FTS44950766 MHI,4 FX'0.sup.. 00045B-5' REGION 3 FTS45050770 AHI,4 FX'0.sup.. 00051B-4' DELTA(EL) RADS B-4 FTS45150772 MHI,6 FX'-.sup.. 00202B-5' FTS45250774 AHI,6 FX'0.sup.. 00266B-4' DELTA(AZ) RADS B-4 FTS45350776 BU FTS4L30 FTS45451000 FTS4L10 MHI,4 FX'0.sup.. 00575B-5' DELTA(EL) RADS B-4 REGION 1 FTS45551002 MHI,6 FX'0.sup.. 00977B-5' DELTA(AZ) RADS B-4 FTS45651004 BU FTS4L30 FTS45751006 FTS4L20 MHI,4 FX'-.sup.. 00121B-5' REGION 2 FTS45851010 AHI,4 FX'0.sup.. 00121B-4' DELTA(EL) RADS B-4 FTS45951012 MHI,6 FX'0.sup.. 00040B-5' FTS46051014 AHI,6 FX'0.sup.. 00163B-4' DELTA(AZ) RADS B-4 FTS461 * FTS46251016 FTS4L30 MG,4 2 DELTA(EL)*COS(LAMBDA) B-3 FTS46351017 MG,4 4 SQUARE B-6 FTS46451020 MG,6 0 DELTA(AZ)*SIN(LAMBDA) B-3 FTS46551021 MG,5 6 SQUARE B-6 FTS46651022 AG,4 6 DELTA**2 B-6 R4 FTS47651023 BAL SQ,3 TO CALC DELTA B-3 R4 FTS47750125 MG,0 6 DELTA(RD)=SIN(LAMBDA)*DELTA B-2 R0 FTS47851026 T,0 CHG SIGN DELTA(RD) B-2 FTS47951027 ST,0 FTV2703 DELTA(RD) B-2 FTS48051031 MG,6 2 COS(LAMBDA)*DELTA B-2 R6 FTS48151032 ST,6 FTV2702 DELTA(RE) B-2 FTS48251034 B *FTV2400 RETURN FTS483* FTS501******** FTSR05 - COMPUTE DISCR SLOPES AND RESIDUALS FTS502******** RETURN ADDRESS IN RO FTS503* FTS50451036 FTS5 LH,2 TXV15 DCAL FROM BIT MATRIX B1 FTS50551040 LHG,4 2 D(CAL) TO R4 FTS50651041 LH,6 SNVO5 SNR(EL) B6 FTS5075l043 CHI,6 FX'2.sup.. 25B6' FTS50851045 BG FTS5L10 BR IF SNR(EL) > THRSH FTS50951047 MHI,6 FX'0.sup.. 44B0' KE1*SNR(EL) B6 FTS51051051 MG,4 6 KE1*SNR(EL)*D(CAL)=KE B7 FTS51151052 SL,4 6 TO B1 FTS51251054 FTS5L10 STH,4 FTV2704 KE B1 FTS513 * FTS51451056 L,6 FTV2011 EPS(P)(E) RADS B-2 FTS51551060 A,6 FTV2014 +S(P)(E) FTS51651062 A,6 FTV2702 +DELTA(R)(E) FTS51751064 MG,6 4 KE*(EPS(E)+S(E)+DELTA(E)) B-1 FTS51851065 LH,4 DSV05 DELTA(EL) DSCR B1 FTS51951067 MHI,4 FX'0.sup.. 030B-2' *C10.sup.. PROD IN RADS AT FTS52051071 SG,4 6 RESIDUAL (EL) RADS B-1 FTS52151072 SL,4 2 TO B-3 FTS52251074 ST,4 FTV2706 RESIDUAL (EL) RADS B-3 FTS523 * FTS52451076 LH,6 SNV04 SNR(AZ) B6 FTS52551100 CHI,6 FX'2.sup.. 25B6' FTS52651102 BG FTS5L20 BR IF SNR(AZ) > THRSH FTS52751104 MHI,6 FX'0.sup.. 44BO' (KD1*SNR(AZ) B6 FTS52851106 MG,2 6 KD1*SNR(AZ)*D(CAL=KD B7 FTS52951107 SL,2 6 TO B1 FTS53051111 FTS5L20 STH,2 FTV2705 KD B1 FTS531 * FTS53251113 L,6 FTV2021 EPS(P)(D) RADS B-2 FTS53351115 A,6 FTV2024 +S(P)(D) FTS53451117 A,6 FTV2703 +DELTA(R)(D) FTS53551121 MG,6 2 KD*(EPS(D)+S(D)+DELTA(D)) B-1 FTS53651122 LH,4 DSV04 DELTA(AZ) DSCR B1 FTS53751124 MHI,4 FX'0.sup.. 030B-2' *C10.sup.. PROD IN RADS AT FTS53851126 SG,4 6 RESIDUAL (AZ) RADS B-1 FTS53951127 SL,4 2 TO B-3 FTS54051131 ST,4 FTV2707 RESIDUAL (AZ) RADS B-3 FTS54151133 BU *0 RETURN FTS542 * FTS601******** FTSR06-COMPUTE KALMAN GAINS K(A) AND FTS602******** UPDATE THE CO-VARIANCE MATRIX M(A) FTS603******** RETURN ADDRESS IN RO FTS604 * FTS60551135 FTS6 ST,0 FTV2400 SAVE RET ADDRESS FTS60651137 LHI,6 FX'1.sup.. 0B1' NZ TO R6 FTS6061051141 LH,0 FTV2704 FTS60751153 AH,0 FTV2705 FTS60851145 SRL,0 1 KA=1/2(KE+KD) KD) B1 FTS60951147 BEZ FTS6L20 BR IF KA=0 FTS61051151 LD,1 FTV2211 M(A)11,M(A)12 TO R1,R2 FTS61151153 LD,3 FTV2213 M(A)13,M(A)14 TO R3,R4 FTS61251155 L,5 FTV2234 M(A)24 TO R5 FTS61351157 LD,6 FTV2234 M(A)34,M(A)44 TO R6,R7 FTS61451161 SRA,1 1 RE-SCALE M(A)'S FTS61551163 SRA,2 1 FTS61651165 SRA,3 1 FTS61751167 SRA,4 1 FTS61851171 SRA,5 1 FTS61951173 SRA,6 1 FTS62051175 SRA,7 1 FTS62151177 AG,1 4 ZM1=M(A)11+M(A)14 B-8 FTS62251200 AG,2 5 ZM2=M(A)12+M(A)24 B-7 FTS62351201 AG,3 6 ZM3=M(A)13+M(A)34 B3 FTS62451202 AG,4 7 ZM4=M(A)14+M(A)44 B-8 FTS625 * FTS62651203 SRA,1 1 ZM1 TO B-7 FTS62751205 LG,6 2 FTS62851206 MT,6 FTV2112 PHI(H)12*ZM2 B-9 FTS62951210 SRA,6 2 TO B-7 FTS63051212 LG,7 3 FTS63151213 MT,7 FTV2113 PHI(A)13*ZM3 B-14 FTS63251215 SRA,7 7 TO B-7 FTS63351217 AG,6 7 FTS63451220 AG,6 1 ZM1+PHI(A)12*ZM2+PHI(A)13*ZM3= FTS63551221 ST,6 FTV2401 Z(A)11 B=7 FTS63651223 MT,3 FTV2122 PHI(A)22*ZM2 B-6 FTS63751225 LG,6 3 FTS63851226 MT,6 FTV2123 PHI(A)23*ZM3 B-9 FTS63951230 SRA,6 3 TO B-6 FTS64051232 AG,6 2 PHI(A)22*ZM2+PHI(A)23*ZM3- FTS64151233 ST,6 FTV2402 Z(A)21 B-6 FTS64251235 MT,3 FTV2133 PHI(A)33*ZM3 B4 FTS64351237 SL,3 1 TO B3 FTS64451241 ST,3 FTV2403 Z(A)31=PHI(A)33*ZM3 B3 FTS64551243 LG,6 4 FTS64651244 MT,6 FTV2144 PHI(A)44*ZM4 B-7 FTS64751246 SL,6 1 TO B-8 FTS64851250 ST,6 FTV2404 Z(A)41=PHI(A)44*ZM4 B-8 FTS649 * FTS65051252 SRA,4 1 ZM4 TO B-7 FTS65151254 AG,1 4 ZM1+ZM4 B-7 FTS65251255 LG,6 0 FTS65351256 MG,6 0 KA**2 B2 FTS65451257 MG,6 1 (KA**2)*(ZM1+ZM4) B-5 FTS65551260 LI,4 FX'0.sup.. 00011B-12' RAO TO R4. F.W. SCALE = B0 FTS65651262 LH,1 XTV029 KFC=PS/FC B11 FTS6561051264 SL,1 6 TO B5 FTS6562051266 DT,4 R1 RAO/KFC B-5 FTS6563051270 LH,1 SNV04 FTS65751272 AH,1 SNV05 FTS65851274 SRL,1 1 SNR(ANGLE)=1/2(SNR(AZ)+SNR(EL) B6 FTS65951276 CHI,1 FX'1.sup.. 0B6' SNR(ANGLE):1 FTS66051300 BL FTS6L10 BR IF SNR(ANGLE) L.T. THRSH FTS66151302 MG,1 1 SNR(ANGLE)**2 B12 FTS66251303 SG,5 5 0 TO R5 FTS6621051304 SRDA,4 12 RAO/KFC TO B7 FTS66351306 DG,4 1 (RAO/KFC)/SNR(ANGLE)**2 B-5 FTS66451307 AI,4 134 +B=RA B-5. (B=.5E-6 B-5) FTS66551311 FTS6L10 AG,6 4 DENOM=RA+(KA**2)*(ZM1+ZM4) B-5 FTS666 * FTS66751312 FTS6L20 LI,1 3 FTS66851314 LI,2 6 3 ITERATIONS FTS66951316 FTS6L30 LG,4 0 KA TO R4 B1 FTS67051317 M,4 FTV2401,2 KA*(Z(A)41,Z(A)31,Z(A)21, Z(A)11) FTS67151321 ST,4 FTV2401,2 B-7,B4,B-5,B-6 FTS67251323 SRDA,4 0,1 B-4,B10,B-1,B-4 FTS67351325 DG,4 6 KA*Z(A)/DENOM B1,B15,B4,B1 FTS67451325 ST,4 FTV2501,2 K(A)4,K(A)3,K(A)2,K(A)1 FTS67551330 LG,1 2 FTS67651331 BCT FTS6L30,2 FTS677 * FTS678******** UPDATE THE CO-VARIANCE MATRIX,M(A) FTS679 * FTS68051333 FTS6L40 LD,0 FTV2212 M(A)12,M(A)13 TO R0,R1 B-8,B2 FTS68151335 L,2 FTV2223 M(A)23 TO R2 B3 FTS68251337 L,3 FTV2233 M(A)33 TO R3 B13 FTS68351341 SRA,1 1 M(A)13 TO B3 FTS68451343 L,4 FTV2112 PHI(A)12 TO R4 B-2 FTS68551345 LG,6 4 TO R6 FTS68651346 M,4 FTV2222 PHI(A)12*M(A)22 B-10 FTS68751350 SRA,4 2 TO B-8 FTS68851352 AG,0 4 M(A)12+PHI(A)12*M(A)22 B-8 FTS68951353 MG,6 2 PHI(A)12*M(A)23 B1 FTS69051354 SRA,6 2 TO B3 FTS69151356 AG,1 6 M(A)13+PHI(A)12*M(A)23 B3 FTS69251361 LG,6 4 TO R6 FTS69451362 MG,4 2 PHI(A)13*M(A)23 B-14 FTS69551363 SRA,4 6 TO B-8 FTS69651365 AG,0 4 D12=M12+PHI12*M22+PHI13*M23 B-8 FTS69751366 MG,6 3 PHI(A)13*M(A)33 B-4 FTS69851367 SRA,6 7 TO B3 FTS69951371 AG,1 6 D13-M13+PHI12*M23+PHI13*M33 B3 FTS6A051372 MT,2 FTV2122 PHI(A)22*M(A)23 B4 FTS6A151374 MT,3 FTV2123 (PHI(A)23*M(A)33 B1 FTS6A251376 SRA,3 3 TO B4 FTS6A351400 AG,3 2 D23=PHI22*M23+PHI23*M33 B4 FTS6A4 ** FTS6A551401 LI,4 0'0002' QS=.466E-9 B-9 FTS6A651403 A,4 FTV2211 M(A)11+QS B-9 FTS6A751405 L,6 FTV2501 FTS6A851407 M,6 FTV2401 K1*(KA*Z11) B(1-6)=B-5 FTS6A951411 SLD,6 4 TO B-9 FTS6B051413 SG,4 6 FTS6B151414 L,6 FTV2213 M(A)13 B2 FTS6B251416 SRA,6 2 TO B4 FTS6B351420 LG,7 1 D13 B3 FTS6B451421 SRA,7 1 TO B4 FTS6B551423 AG,6 7 M13+D13 B4 FTS6B651424 M,6 FTV2113 PHI13*(M13+D13) B-13 FTS6B751426 SRA,6 4 TO B-9 FTS6B851430 AG,4 6 FTS6B951431 L,6 FTV2212 M(A)12 B-8 FTS6C051433 SRA,6 1 TO B-7 FTS6C151435 LG,7 0 D12 B-8 FTS6C251436 SRA,7 1 TO B-7 FTS6C351440 AG,6 7 M12+D12 B-7 FTS6C451441 M,6 FTV2112 PHI12*(M12+D12) B-9 FTS6C551443 AG,4 6 FTS6C651444 St,4 FTV2211 M(A)11 UPDATED B-9 FTS6C7 * FTS6C851446 L,4 FTV2122 PHI(A)22 B1 FTS6C951450 MG,4 4 FTS6D051451 M,4 FTV2222 (PHI22)**2)*M22 B(2-8)=B-6 FTS6D151453 L,6 FTV2502 FTS6D251455 M,6 FTV2402 K2*(KA8Z21) B(4-5)=B-1 FTS6D351457 SLD,6 5 TO B-6 FTS6D451461 SD,4 R6 FTS6D551463 LG,6 3 D23 B4 FTS6D651464 SRA,6 2 TO B6 FTS6D751466 SRA,2 2 R2 TO B6 FTS6D851470 AG,6 2 FTS6D951471 M,6 FTV2123 PHI23*(PHI22(M23+D23) B-6 FTS6E051473 AD,4 R6 NEW M(A)22 In R4,R5 B-6 FTS6E151475 SLD,4 2 FTS6E251477 ST,4 FTV2222 M(A)22 UPDATED B-8 FTS6E3 * FTS6E451501 L,4 FTV2133 PHI(A)33 B1 FTS6E551503 MG,4 4 FTS6E651504 M,4 FTV2233 ((PHI33)**2)*M33 B15 FTS6E751506 L,6 FTV2503 FTS6E851510 M,6 FTV2403 K3*(KA*731) B(15+4)=B19 FTS6E951512 SLD,6 5 TO B15 FTS6F051514 SD,4 R6 FTS6F151516 SLD,4 2 R4,R5 TO B13 FTS6F251520 LH,6 FTV0010 T B-3 FTS6F351522 MHI,6 FX'2670.sup.. B13' ALPHA4*T=Q33 B10 FTS6F451524 SRA,6 3 TO B13 FTS6F551526 AG,4 6 FTS6F651527 ST,4 FTV2233 M(A)33 UPDATED B13 FTS6F7 * FTS6F851531 L,4 FTV2144 PHI(A)44 B1 FTS6F951533 MG,4 4 FTS6G051534 M,4 FTV2244 ((PHI44)**2)*M44 B-7 FTS6G151536 L,6 FTV2504 FTS6G251540 M,6 FTV2404 K4*(KA*Z41) B(1-7)=B- 6 FTS6G351542 SLD,6 1 TO B-7 FTS6G451544 SD,4 R6 FTS6G551546 SLD,4 2 R4,R5 TO B-9 FTS6G651550 LH,6 FTv0010 T B-3 FTS6G751552 SRA,6 5 TO B1 FTS6G851554 M,6 FTV2700 FTS6G951556 D,6 FTV2701 Q44-T*SIGMA(S)**2/TAU(S) B-9 FTS6H051560 AG,4 6 FTS6H151561 ST,4 FTV2244 M(A)44 UPDATED B-9 FTS6H2 * FTS6H351563 MT,0 FTV2122 PHI22*D12 B-7 FTS6H451565 L,4 FTV2123 FTS6H551567 MG,4 1 PHI23*D13 B-9 FTS6H651570 SRA,4 2 TO B-7 FTS6H751572 AG,4 0 FTS6H851573 L,6 FTV2501 FTS6H951575 M,6 FTV2402 K1*(KA*Z21) B(1-5)=B-4 FTS6I051577 SLD,6 3 TO B-7 FTS6I151601 SG,4 6 FTS6I251602 SL,4 1 FTS6I351604 ST,4 FTV2212 M(A)12 UPDATED B-8 FTS6I4 * FTS6I551606 M,1 FTV2133 PHI33*D13 B4 FTS6I651610 L,6 FTV2501 FTS6I751612 M,6 FTV2403 K1*(KA*Z31) B(1+4)=B5 FTS6I851614 SDL,6 1 TO B4 FTS6I951616 SD,1 R6 NEW M(A)13 IN R1,R2 B4 FTS6J051620 SLD,1 2 FTS6J151622 ST,1 FTV2213 M(A)13 UPDATED B2 FTS6J2 ** FTS6J351624 L,4 FTV2144 PHI(A)44 B1 FTS6J451626 L,0 FTV2234 M(A)34 B2 FTS6J551630 MG,0 4 D43=PHI44*M34 B3 FTS6J651631 SL,0 1 TO B2 FTS6J751633 L,1 FTV2224 M(A)24 B-8 FTS6J851635 MG,1 4 D42=PHI44*M24 B-7 FTS6J951636 SL,1 1 TO B-8 FTS6K0 ** FTS6K151640 M,4 FTV2214 PHI44*M14 B-8 FTS6K251642 L,6 FTV2112 FTS6K351644 MG,6 1 PHI12*D42 B-10 FTS6K451645 SRA,6 2 TO B-8 FTS6K551647 AG,4 6 FTS6K651650 L,6 FTV2113 FTS6K751652 MG,6 0 PHI13*D43 B-15 FTS6K851653 SRA,6 7 TO B-8 FTS6K951655 AG,4 6 FTS6L051656 L,6 FTV2501 FTS6L151660 M,6 FTV2404 K1*(KA*Z41) B(1-7)=B-6 FTS6L251662 SLD,6 2 TO B-8 FTS6L351665 SG,4 6 FTS6L451665 SL,4 1 FTS6L551667 ST,4 FTV2214 M(A)14 UPDATED B-9 FTS6L6 * FTS6L751671 M,3 FTV2133 PHI33*D23 B5 FTS6L851673 L,6 FTV2502 FTS6L951674 M,6 FTV2403 K2*(KA*Z31) B(4+4)=B8 FTS6M051677 SLD,6 3 TO B5 FTS6M151701 SD,3 R6 NEW M(A)23 IN R3,R4 B5 FTS6M251703 SLD,3 2 FTS6M351705 ST,3 FTV2223 M(A)23 UPDATED B3 FTS6M4 * FTS6M551707 M,1 FTV2122 PHI22*D42 B-7 FTS6M651711 L,6 FTV2123 FTS6M751713 MG,6 0 PHI23*D43 B-10 FTS6M851714 SRA,6 3 TO B-7 FTS6M951716 AG,1 6 FTS6N051717 L,6 FTV2502 FTS6N151721 M,6 FTV2404 K2*(KA*Z41) B(4-7)=B-3 FTS6N251723 SLD,6 4 TO B-7 FTS6N351725 SG,1 6 FTS6N451726 SL,1 1 FTS6N551730 ST,1 FTV2224 M(A)24 UPDATED B-8 FTS6N6 * FTS6N751732 M,0 FTV2133 PHI33*D43 B3 FTS6N851734 L,6 FTV2503 FTS6N951736 M,6 FTV2404 K3*(KA-Z41) B(15-7)=B8 FTS6P151740 SLD,6 5 TO B3 FTS6P251742 SG,0 6 FTS6P351743 SL,0 1 FTS6P451745 ST,0 FTV2234 M(A)34 UPDATED B2 FTS6P551747 BU *FTV2400 EXIT FTS6P6 * FTS701******** FTSR07-COMPUTE NEW PREDICTED ANGLE STATE VECTORS FTS702 ******** RETURN ADDRESS IN R0 FTS703 * FTS70451751 FTS7 ST,0 FTV2400 SAVE RET ADDRESS FTS70551753 LI,1 2 SET INDICES FOR AZ FTS70651755 LI,2 4 FTS70751757 LI,3 8 FTS70851761 FTS7L10 L,0 FTV2706,1 RESIDUAL TO R0 RADS B-3 FTS70951763 L,4 FTV2012,3 FTS71051765 M,4 FTV2112 PHI(A)12*OMEGA(LSP) B-1 FTS71151767 SLD,4 1 TO B-2 FTS71251771 L,6 FTV2013,3 FTS71351773 M,6 FTV2113 PHI(A)13*A(TP) B-6 FTS71451775 SRA,6 4 TO B-2 FTS71551777 AG,4 6 FTS71652000 A,4 FTV2011,3 +EPS(P) FTS71752002 A,4 FTV2611,2 +L1 FTS71852004 LG,6 0 FTS71952005 M,6 FTV2501 K(A)1*RESIDUAL B-2 FTS72052007 AG,4 6 FTS72152010 ST,4 FTV2011,3 NEW EPS(P) RADS B-2 FTS722 * FTS72352012 L,4 FTV2012,3 FTS72452014 M,4 FTV2122 PHI(A)22*OMEGA(LSP) B2 FTS72552016 SG,6 6 FTS72652017 LHI,7 O'2000' FTS72752021 AD,4 R6 ROUND R4,R5 FTS72852023 SLD,4 1 TO B1 FTS72952025 L,6 FTV2013,3 FTS73052027 M,6 FTV2123 PHI(A)23*A(TP) B-1 FTS73152031 SRA,6 2 TO B1 FTS73252033 AG,4 6 FTS73352034 A,4 FTV2612,2 +L2 FTS73452036 LG,6 0 FTS73552037 M,6 FTV2502 K(A)2*RESIDUAL B1 FTS73652041 AG,4 6 FTS73752042 ST,4 FTV2012,3 NEW OMEGA(LSP) RADS/SEC B1 FTS738 * FTS73952044 L,4 FTV2013,3 FTS73052046 M,4 FTV2133 PHI(A)33*A(TP) B12 FTS74152050 LG,6 0 FTS74252051 M,6 FTV2503 K(A)3*RESIDUAL B12 FTS74352053 AD,4 R6 FTS74452055 SLD,4 1 TO B11 FTS74552057 ST,4 FTV2013,3 NEW A(TP) FPS**2 B11 FTS746 * FTS7461052061 L,4 FTV2014,3 FTS74752063 M,4 FTV2144 PHI(A)44*S(P) B-1 FTS74852065 SLD,4 1 TO B-2 FTS74952067 LG,6 0 FTS75052070 M,6 FTV2504 K(A)4*RESIDUAL B-2 FTS75152072 AG,4 6 FTS75252073 ST,4 FTV2014,3 NEW S(P) RADS B-2 FTS753 * FTS75452075 SG,2 2 R2=0 SET INDICES FOR EL FTS75552076 SG,3 3 R3=0 FTS75652077 BCT FTS7L10,1 R1=0 FTS75752101 BU *FTV2400 EXIT FTS758 * FTS801******** FTSR08-COMPUTE OWNSHIP ACCELERATION IN ANTENNA COORDS FTS802 ******** RETURN ADDRESS IN R0 FTS803 * FTS80452103 FTS8 ST,0 FTV2400 SAVE RET ADDRESS FTS80552105 L,4 IND4 V(N)2 TO R4 FTS80652107 L,5 IND5 V(E)2 TO R5 FTS80752111 L,6 IND6 V(V)2 TO R6 FTS80852113 LD,1 FTV3111 V(N)1,V(E)1 TO R1,R2 FTS80952115 L,3 FTV3113 V(V)1 TO R3 FTS81052117 STD,4 FTV3111 V(N)2,V(E)2 TO V(N)1,V(E)1 FTS81152121 ST,6 FTV3113 V(V)2 TO V(V)1 FTS812 * FTS81352123 SG,4 1 V(N)2-V(N)1 FPS B12 FTS81452124 SG,5 2 V(E)2-V(E)1 FPS B12 FTS81552125 SG,6 3 V(V)2-V(V)1 FPS B11 FTS81652126 T,6 FTS81752127 SRA,6 1 V(D)2-V(D)1 FPS B12 FTS81852131 DT,4 FTV0012 AI(N) FPS**2 B11 OS ACCEL IN NED FTS81952133 DT,5 FTV0012 AI(E) FPS**2 B11 FTS82052135 DT,6 FTV0012 AI(D) FPS**2 B11 FTS82152137 LG,1 4 AI(N) TO R1 FTS82252140 LG,2 5 AI(E) TO R2 FTS8221052141 ST,6 FTV3003 FTS82352143 STI,0 FTV0012 CLEAR T(INS) FTS824 * FTS82552145 L,4 FTV3209 SIN(PSI) TO R4 FTS82652147 L,6 FTV3210 COS(PSI) TO R6 FTS82752151 BAL SR,3 PSI XFRM FTS82952153 ST,4 FTV3002 A(JS) TO MEMORY FTS83052155 LG,2 4 A(IS) TO R2 FTS83152156 L,1 FTV3003 AI(D) TO R1 FTS832 * FTS83352160 L,4 FTV3207 SIN(THETA) TO R4 FTS83452162 L,6 FTV3208 COS(THETA) TO R6 FTS83552164 BAL SR,3 THETA XFRM FTS83652166 ST,6 FTV3001 A(I) TO MEMORY FTS83752170 LG,2 4 A(K') TO R2 FTS83852171 L,1 FTV3002 A(JS) TO R1 FTS839 * FTS84052173 L,4 FTV3205 SIN(PHI+PHIG) TO R4 FTS84152175 L,6 FTV3206 COS(PHI+PHIG) TO R6 FTS84252177 BAL SR,3 PHI+PHIG XFRM FTS84352201 ST,4 FTV3002 A(E') TO MEMORY FTS84452203 LG,1 5 A(D') TO R1 FTS84552204 L,2 FTV3001 A(I) TO R2 FTS846 * FTS84752206 L,4 FTV3203 SIN(EPS) TO R4 FTS84852210 L,6 FTV3204 COS(EPS) TO R6 FTS84952212 BAL SR,3 EPS XFRM FTS85052214 ST,4 FTV3003 AI(D) EPS**2 B11 FTS85152216 LG,1 5 A(R') TO R1 FTS85252217 L,2 FTV3002 A(E') TO R2 FTS853 * FTS85452221 L,4 FTV3201 SIN(ETA) TO R4 FTS85552223 L,6 FTV3202 COS(ETA) TO R6 FTS85652225 BAL SR,3 ETA XFRM FTS85752227 STD,4 FTV3001 AI(R),AI(E) FPS**2 B11 FTS85852231 BU *FTV2400 EXIT FTS859 * FTI001******** TRACKING FILTER INITIALIZATION FTI002******** RETURN ADDRESS IN RO FTI003 * FTU00452237 FTI LH,1 AQV09 RT=RNG HIT BIN NO. FR AQII B11 FTI00752241 LH,2 AQV18 FT=VEL HIT FIL NO. FR AQII B11 FTI00852243 LH,3 FTV0010 T SECS B-3 FTI00952245 L,6 VGV3 VT FPS B12 FTI01052247 SRA,6 1 FTI01152251 T,6 -VG FPS B13 FTI012 * FTI201******** MPRF TRACKING FILTER INITIALIZATION FTI202 * FTI20352306 FTIL20 MT,1 XTV044 R1 = RBIN*RT FT B22 FTI20452310 SL,1 2 R1 = RBIN*RT FT B20 FTI20552312 LH,4 DNV10 R4 = DELTA(RT) FT B11 FTI20652314 MHI,4 FX'-.43B0' R4=-.43 DELTA (RT) B11 FTI2061052316 SRA,4 9 B20 FTI2062052320 AG,1 4 R1=RBIN*RT-.43 DELTA(RT) B20 FTI2063052321 ST,1 FTV1001 R(TPR)-INITIAL RNG FT B20 FTI20752323 ST,6 FTV1002 V(TPR)=-VG FPS B13 FTI20852325 MG,6 3 T*V(TPR) FT B10 FTI20952326 SRA,6 10 TO B20 FTI21052330 AG,1 6 FTI21152331 ST,1 FTV0101 RGC=R(TPR)+T*V(TPR) FT B20 FTI212 * FTI21352333 MT,2 XTV045 *PRF/16 AT B10.sup.. PROD AT B21 FTI21452335 MT,2 RFV003 *(LAMBDA/2) AT B-4.PROD AT B17 FTI21552337 SL,2 4 TO B13 FTI21652341 FTIL25 ST,2 FTV1012 V(TPV) FPS B13 FTI21752343 ST,2 FTV0102 VGC=V(TPV) B13 FTI21852345 BU FTIL40 TO COMMON I.C. FTI219 * FTI401******** COMMON TRACKING FILTER INITIALIZATION.(ALL PRF'S) FTI402 * FTI40452414 FTIL40 LHI,4 FX'1.sup.. B6' SET A-PRIORI SNR'S FOR 1ST LONG FC FTI40552416 STH,4 SNV03 SNR(RNG) FTI40652420 STH,4 SNV04 SNR(AZ) FTI40752422 STH,4 SNV05 SNR(EL) FTI40852424 STH,4 SNV06 SNR(VEL) FTI409 * FTI41052426 STH,5 FTF102 `HI BR 1ST`=(R5)=`VS`(NOT USED=M,L) FTI41152430 STHI,1 FTV1601 I.C. MED BR COUNT (N=1) FTI41352432 BU *0 RETURN TO XT FTI414
APPENDIX CRange TrackerC.sub.1 =C.sub.3 0 0 (R>50,000 ft) (R.ltoreq.50,000 ft)C.sub.2 -0.333 (-0.1 for extrapolation) max__________________________________________________________________________ k.sub.1.sup.a 0.15 0.08 2Initial k.sub.2.sup.a 0.3 0.18 2Track k.sub. 3.sup.a 0.0 0.0 8 R.sub.o SNR < 7 db R.sub.o SNR max .gtoreq. 7 db k.sub.1.sup.b 0.15 0.12 2Final k.sub.2.sup.b 0.16 0.2 8Track k.sub.3.sup.b 0.05 0.13 32 R.sub.o SNR < 7 db R.sub.o SNR .gtoreq. 7 db SNR1 1.0 1Velocity Tracker max__________________________________________________________________________ K.sub.2.sup.d -0.15 -0.23 4Initial K.sub.3.sup.d -0.8 -2 32Track k.sub.Rf. 1 1 2 R.sub. o SNR < 7 db R.sub.o SNR .gtoreq. 7 db max K.sub.2.sup.e 0.7 1.0 8Final K.sub.3.sup.e 3.0 5.0 32Track k.sub.Rf. 0.35 0.85 2 R.sub.o SNR<7db R.sub.o SNR.gtoreq.7 dbAngle Track max__________________________________________________________________________K.sub.al 0.8 0.2 0.12 2K.sub.a2 4 0.67 0.17 15K.sub.a3 -2.times.10.sup.3 -10.sup.3 -100 2.sup.15K.sub.a4 0.15 0.02 0 2 R(0)<R.sub.1 R.sub.1 <R(0)and R.sub.1 <R(0)and SNR(D).gtoreq.C.sub.4 SNR(D)<C.sub.4 SNR(D)=SNR.sub.R maxR.sub.1 2.times.10.sup.4 5.times.1.sup.4C.sub.4 4 20C.sub.10 0.03 0.1Antenna Controller Parameters max__________________________________________________________________________K.sub.2 15 60a.sub.1, a.sub. 2 1.0 1.0b.sub.1, b.sub.2 0.3 4C.sub.1, C.sub.2 -0.3 4Angular Scintillation max__________________________________________________________________________.alpha..sub.1 0.8 2.alpha..sub.2 130 500.alpha..sub.3 0.0025 1Q.sub.a Matrix max__________________________________________________________________________Q.sub.s 0.4.times.10.sup.-.sup.9 10.sup.-.sup.7.alpha..sub.4 2670 8.times.10.sup.3A, H, K Matrices max__________________________________________________________________________a.sub.T 0.33 1k.sub.e0 0 0k.sub.e1 0.44 1k.sub.e2 0 0k.sub.d0 0 0K.sub.d1 0.44 1k.sub.d2 0 0R.sub.a0 1.1.times.10.sup.-.sup.4 2.sup.-.sup.12S.sub.2 (Initial SNR) 1 10b 0.5.times.10.sup.-.sup.6 10.sup.7L.sub.e and L.sub.d Vectors max__________________________________________________________________________K.sub.g -0.1 1C.sub.15 0.7 0.1C.sub.14 0.834 2Radome Errors (Typical)A 0.0010 radB 0.0007C 0.0009D 0.0017E 0.0018F 0.0009Initialization of Full Track max__________________________________________________________________________m.sub.1 10.sup.-.sup.4 5.times.10.sup.-.sup.4m.sub.3 4.times.10.sup.3 5.times.10.sup.3m.sub.2 4.times.10.sup.-.sup.4 3.9.times.10.sup.3Reinitialization max__________________________________________________________________________C.sub.11 1.5.times.10.sup.-.sup.3 1.9.times.10.sup.-.sup.3C.sub.12 3.times.10.sup.-.sup.3 3.9.times.10.sup.-.sup.3C.sub.13 0.9 1__________________________________________________________________________
APPENDIX D
* UV001 * SUBROUTINE UV (UNAMBIGUOUS VELOCITY) UV002 * UV003 * RESULT IN (R4) = VTCORR(CORRECTED VELOCITY) B13 UV004 * UV00554505 UV L,4 FTV1002 VTPR B13 UV00654507 L,0 RFV004 LAMDA H RECIP B5 UV00754511 MG,4 0 -FDP B18 UV00854512 M,0 FTV1012 FDAP B18 UV00954514 AG,4 0 FDAP-FDP B18 UV01054515 L,1 XTV018 UV01154517 SL,1 1 FMLC B18 UV011054521 AG,4 1 FMLC+FDAP-FDP B18 UV01254522 M,4 DNV04 NR OF PRFS AWAY = (ABOVE)/MPRF B10 UV01654524 SRA,4 1 B11 UV01754526 L,7 UVK00 250.5 B11 FOR RND AND POS TRANSF UV018 1054530 AG,4 7 ADD 250 B11 FOR POSITIVE TRANSF UV01954531 LHG,4 4 TRUNC POSITIVE EXPRESSION UV02054532 SHG,4 7 TRANSF BACK BY -250 B11 UV02154533 M,4 DNV03 (NR PRFS AWAY)*MPRF=DOPPLER B25 UV02254535 SLD,4 7 DPLR OF PRFS AWAY B18 UV02354537 SG,4 0 DPLR OF PRFS AWAY - FDAP B18 UV02454540 SG,4 1=FDC=DPLRPRFSAWAY-FDAP=FMLC B18 UV02554541 M,4 RFV003 VTCORR B14 UV02854543 AG,4 4 SCALE VTCORR AT B13 UV028 1054544 LI,5 0'7177' BIT 15,16 OFF UV028 2054546 N,5 RSP1 SET DPLR COMPENSATION = 00 UV028 3054550 ST,5 RSP1 UV028 4054552 BU 0,3 UV029

Number	Name	Date	Kind
3646554	Fierston et al.	Feb 1972
3688313	Kern	Aug 1972

System for resolving velocity ambiguity in pulse-doppler radar

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